1/* 2 * Copyright (c) 2010-2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 34 unchanged lines hidden (view full) --- 43 44#include <algorithm> 45#include <string> 46 47#include "arch/utility.hh" 48#include "base/loader/symtab.hh" 49#include "base/cp_annotate.hh" 50#include "config/the_isa.hh" |
51#include "cpu/checker/cpu.hh" |
52#include "cpu/o3/commit.hh" 53#include "cpu/o3/thread_state.hh" 54#include "cpu/base.hh" 55#include "cpu/exetrace.hh" 56#include "cpu/timebuf.hh" 57#include "debug/Activity.hh" 58#include "debug/Commit.hh" 59#include "debug/CommitRate.hh" 60#include "debug/ExecFaulting.hh" 61#include "debug/O3PipeView.hh" 62#include "params/DerivO3CPU.hh" 63#include "sim/faults.hh" 64#include "sim/full_system.hh" 65 |
66using namespace std; 67 68template <class Impl> 69DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit, 70 ThreadID _tid) 71 : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid) 72{ 73} --- 654 unchanged lines hidden (view full) --- 728 DPRINTF(Commit, "Interrupt detected.\n"); 729 730 // Clear the interrupt now that it's going to be handled 731 toIEW->commitInfo[0].clearInterrupt = true; 732 733 assert(!thread[0]->inSyscall); 734 thread[0]->inSyscall = true; 735 |
736 if (cpu->checker) { 737 cpu->checker->handlePendingInt(); 738 } |
739 740 // CPU will handle interrupt. 741 cpu->processInterrupts(interrupt); 742 743 thread[0]->inSyscall = false; 744 745 commitStatus[0] = TrapPending; 746 --- 385 unchanged lines hidden (view full) --- 1132 // Check if the instruction caused a fault. If so, trap. 1133 Fault inst_fault = head_inst->getFault(); 1134 1135 // Stores mark themselves as completed. 1136 if (!head_inst->isStore() && inst_fault == NoFault) { 1137 head_inst->setCompleted(); 1138 } 1139 |
1140 // Use checker prior to updating anything due to traps or PC 1141 // based events. 1142 if (cpu->checker) { 1143 cpu->checker->verify(head_inst); 1144 } |
1145 1146 if (inst_fault != NoFault) { 1147 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n", 1148 head_inst->seqNum, head_inst->pcState()); 1149 1150 if (iewStage->hasStoresToWB(tid) || inst_num > 0) { 1151 DPRINTF(Commit, "Stores outstanding, fault must wait.\n"); 1152 return false; 1153 } 1154 1155 head_inst->setCompleted(); 1156 |
1157 if (cpu->checker) { 1158 // Need to check the instruction before its fault is processed 1159 cpu->checker->verify(head_inst); 1160 } |
1161 1162 assert(!thread[tid]->inSyscall); 1163 1164 // Mark that we're in state update mode so that the trap's 1165 // execution doesn't generate extra squashes. 1166 thread[tid]->inSyscall = true; 1167 1168 // Execute the trap. Although it's slightly unrealistic in --- 358 unchanged lines hidden --- |