1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 658 unchanged lines hidden (view full) --- 667 generateTrapEvent(0); 668 669 // Clear the interrupt now that it's been handled 670 toIEW->commitInfo[0].clearInterrupt = true; 671 interrupt = NoFault; 672 } else { 673 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n"); 674 } |
675 } else if (cpu->check_interrupts(cpu->tcBase(0)) && |
676 commitStatus[0] != TrapPending && 677 !trapSquash[0] && 678 !tcSquash[0]) { 679 // Process interrupts if interrupts are enabled, not in PAL 680 // mode, and no other traps or external squashes are currently 681 // pending. 682 // @todo: Allow other threads to handle interrupts. 683 --- 739 unchanged lines hidden --- |