1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 624 unchanged lines hidden (view full) --- 633 // Check for interrupts 634 ////////////////////////////////////// 635 636#if FULL_SYSTEM 637 // Process interrupts if interrupts are enabled, not in PAL mode, 638 // and no other traps or external squashes are currently pending. 639 // @todo: Allow other threads to handle interrupts. 640 if (cpu->checkInterrupts && |
641 cpu->check_interrupts(cpu->tcBase(0)) && |
642 !trapSquash[0] && 643 !tcSquash[0]) { 644 // Tell fetch that there is an interrupt pending. This will 645 // make fetch wait until it sees a non PAL-mode PC, at which 646 // point it stops fetching instructions. 647 toIEW->commitInfo[0].interruptPending = true; 648 649 // Wait until the ROB is empty and all stores have drained in --- 763 unchanged lines hidden --- |