1/* |
2 * Copyright 2014 Google, Inc. |
3 * Copyright (c) 2010-2014 ARM Limited 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license --- 1090 unchanged lines hidden (view full) --- 1101 // drainImminent to disable interrupts 1102 DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]); 1103 squashAfter(tid, head_inst); 1104 cpu->commitDrained(tid); 1105 drainImminent = true; 1106 } 1107 } 1108 |
1109 bool onInstBoundary = !head_inst->isMicroop() || 1110 head_inst->isLastMicroop() || 1111 !head_inst->isDelayedCommit(); 1112 1113 if (onInstBoundary) { 1114 int count = 0; 1115 Addr oldpc; 1116 // Make sure we're not currently updating state while 1117 // handling PC events. 1118 assert(!thread[tid]->noSquashFromTC && 1119 !thread[tid]->trapPending); 1120 do { 1121 oldpc = pc[tid].instAddr(); 1122 cpu->system->pcEventQueue.service(thread[tid]->getTC()); 1123 count++; 1124 } while (oldpc != pc[tid].instAddr()); 1125 if (count > 1) { 1126 DPRINTF(Commit, 1127 "PC skip function event, stopping commit\n"); 1128 break; 1129 } |
1130 } 1131 1132 // Check if an instruction just enabled interrupts and we've 1133 // previously had an interrupt pending that was not handled 1134 // because interrupts were subsequently disabled before the 1135 // pipeline reached a place to handle the interrupt. In that 1136 // case squash now to make sure the interrupt is handled. 1137 // 1138 // If we don't do this, we might end up in a live lock situation |
1139 if (!interrupt && avoidQuiesceLiveLock && 1140 onInstBoundary && cpu->checkInterrupts(cpu->tcBase(0))) |
1141 squashAfter(tid, head_inst); 1142 } else { 1143 DPRINTF(Commit, "Unable to commit head instruction PC:%s " 1144 "[tid:%i] [sn:%i].\n", 1145 head_inst->pcState(), tid ,head_inst->seqNum); 1146 break; 1147 } 1148 } --- 399 unchanged lines hidden --- |