544d543
< toIEW->commitInfo[tid].branchMispredict = false;
545a545
> toIEW->commitInfo[tid].squashInst = NULL;
587c587,588
< DefaultCommit<Impl>::squashAfter(ThreadID tid, uint64_t squash_after_seq_num)
---
> DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst,
> uint64_t squash_after_seq_num)
596a598
> toIEW->commitInfo[tid].squashInst = head_inst;
604c606
< toIEW->commitInfo[tid].branchMispredict = false;
---
> toIEW->commitInfo[tid].mispredictInst = NULL;
804c806,808
< DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
---
> if (fromIEW->mispredictInst[tid]) {
> DPRINTF(Commit,
> "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
806c810
< fromIEW->mispredPC[tid],
---
> fromIEW->mispredictInst[tid]->instAddr(),
807a812,816
> } else {
> DPRINTF(Commit,
> "[tid:%i]: Squashing due to order violation [sn:%i]\n",
> tid, fromIEW->squashedSeqNum[tid]);
> }
838,839d846
< toIEW->commitInfo[tid].branchMispredict =
< fromIEW->branchMispredict[tid];
843a851
> toIEW->commitInfo[tid].squashInst = NULL;
847,849c855
< toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
<
< if (toIEW->commitInfo[tid].branchMispredict) {
---
> if (toIEW->commitInfo[tid].mispredictInst) {
991c997
< squashAfter(tid, head_inst->seqNum);
---
> squashAfter(tid, head_inst, head_inst->seqNum);