121,123d120
< checkEmptyROB[i] = false;
< trapInFlight[i] = false;
< committedStores[i] = false;
341d337
< toIEW->commitInfo[i].emptyROB = true;
480c476,477
< trapInFlight[tid] = true;
---
>
> thread[tid]->trapPending = true;
487d483
< assert(!trapInFlight[tid]);
502c498
< 0 : rob->readHeadInst(tid)->seqNum - 1;
---
> 0 : rob->readHeadInst(tid)->seqNum - 1;;
539d534
< trapInFlight[tid] = false;
588,591d582
< // Clear the bit saying if the thread has committed stores
< // this cycle.
< committedStores[tid] = false;
<
647d637
< #if FULL_SYSTEM
650c640
< DefaultCommit<Impl>::handleInterrupt()
---
> DefaultCommit<Impl>::commit()
651a642,647
>
> //////////////////////////////////////
> // Check for interrupts
> //////////////////////////////////////
>
> #if FULL_SYSTEM
660,665d655
< Fault new_interrupt = cpu->getInterrupts();
< assert(new_interrupt == interrupt);
<
< // Clear the interrupt now that it's going to be handled
< toIEW->commitInfo[0].clearInterrupt = true;
<
678a669,670
> // Clear the interrupt now that it's been handled
> toIEW->commitInfo[0].clearInterrupt = true;
683,686c675,678
< } else if (commitStatus[0] != TrapPending &&
< cpu->check_interrupts(cpu->tcBase(0)) &&
< !trapSquash[0] &&
< !tcSquash[0]) {
---
> } else if (cpu->check_interrupts(cpu->tcBase(0)) &&
> commitStatus[0] != TrapPending &&
> !trapSquash[0] &&
> !tcSquash[0]) {
702,703d693
< }
< #endif // FULL_SYSTEM
705,716d694
< template <class Impl>
< void
< DefaultCommit<Impl>::commit()
< {
<
< #if FULL_SYSTEM
< // Check for any interrupt, and start processing it. Or if we
< // have an outstanding interrupt and are at a point when it is
< // valid to take an interrupt, process it.
< if (cpu->check_interrupts(cpu->tcBase(0))) {
< handleInterrupt();
< }
734d711
< assert(commitStatus[tid] != TrapPending);
779d755
<
843a820,823
> if (rob->isEmpty(tid)) {
> toIEW->commitInfo[tid].emptyROB = true;
> }
>
846,847d825
< if (rob->isEmpty(tid))
< checkEmptyROB[tid] = true;
849,866d826
<
< // ROB is only considered "empty" for previous stages if: a)
< // ROB is empty, b) there are no outstanding stores, c) IEW
< // stage has received any information regarding stores that
< // committed.
< // c) is checked by making sure to not consider the ROB empty
< // on the same cycle as when stores have been committed.
< // @todo: Make this handle multi-cycle communication between
< // commit and IEW.
< if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
< !iewStage->hasStoresToWB() && !committedStores[tid]) {
< checkEmptyROB[tid] = false;
< toIEW->commitInfo[tid].usedROB = true;
< toIEW->commitInfo[tid].emptyROB = true;
< toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
< wroteToTimeBuffer = true;
< }
<
1008a969,970
> head_inst->setAtCommit();
>
1018c980,987
< if (inst_num > 0 || iewStage->hasStoresToWB()) {
---
> // Hack to make sure syscalls/memory barriers/quiesces
> // aren't executed until all stores write back their data.
> // This direct communication shouldn't be used for
> // anything other than this.
> if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
> head_inst->isQuiesce()) &&
> iewStage->hasStoresToWB())
> {
1020a990,992
> } else if (inst_num > 0 || iewStage->hasStoresToWB()) {
> DPRINTF(Commit, "Waiting to become head of commit.\n");
> return false;
1033,1038d1004
< if (inst_num > 0 || iewStage->hasStoresToWB()) {
< DPRINTF(Commit, "Waiting for all stores to writeback.\n");
< return false;
< }
<
< assert(head_inst->uncacheable());
1062,1064d1027
< // Check if the instruction caused a fault. If so, trap.
< Fault inst_fault = head_inst->getFault();
<
1066c1029
< if (!head_inst->isStore() && inst_fault == NoFault) {
---
> if (!head_inst->isStore()) {
1077a1041,1043
> // Check if the instruction caused a fault. If so, trap.
> Fault inst_fault = head_inst->getFault();
>
1084a1051
> head_inst->setCompleted();
1093,1094d1059
< head_inst->setCompleted();
<
1120,1126d1084
< if (head_inst->traceData) {
< head_inst->traceData->setFetchSeq(head_inst->seqNum);
< head_inst->traceData->setCPSeq(thread[tid]->numInst);
< head_inst->traceData->finalize();
< head_inst->traceData = NULL;
< }
<
1151c1109,1110
< head_inst->traceData->finalize();
---
> head_inst->traceData->dump();
> delete head_inst->traceData;
1167,1170d1125
< // If this was a store, record it for this cycle.
< if (head_inst->isStore())
< committedStores[tid] = true;
<
1215,1216c1170
< commitStatus[tid] != ROBSquashing &&
< commitStatus[tid] != TrapPending) {
---
> commitStatus[tid] != ROBSquashing) {