731,732c731,732
< InstSeqNum bdelay_done_seq_num;
< bool squash_bdelay_slot;
---
> InstSeqNum bdelay_done_seq_num = squashed_inst;
> bool squash_bdelay_slot = fromIEW->squashDelaySlot[tid];
734,752c734,736
< if (fromIEW->branchMispredict[tid]) {
< if (fromIEW->branchTaken[tid] &&
< fromIEW->condDelaySlotBranch[tid]) {
< DPRINTF(Commit, "[tid:%i]: Cond. delay slot branch"
< "mispredicted as taken. Squashing after previous "
< "inst, [sn:%i]\n",
< tid, squashed_inst);
< bdelay_done_seq_num = squashed_inst;
< squash_bdelay_slot = true;
< } else {
< DPRINTF(Commit, "[tid:%i]: Branch Mispredict. Squashing "
< "after delay slot [sn:%i]\n", tid, squashed_inst+1);
< bdelay_done_seq_num = squashed_inst + 1;
< squash_bdelay_slot = false;
< }
< } else {
< bdelay_done_seq_num = squashed_inst;
< squash_bdelay_slot = true;
< }
---
> if (!squash_bdelay_slot)
> bdelay_done_seq_num++;
>
1120c1104
< renameMap[tid]->setEntry(head_inst->destRegIdx(i),
---
> renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1199a1184
> int tid = inst->threadNumber;
1203,1204c1188
< "skidBuffer.\n", inst->readPC(), inst->seqNum,
< inst->threadNumber);
---
> "skidBuffer.\n", inst->readPC(), inst->seqNum, tid);
1209c1193
< inst->readPC(), inst->seqNum, inst->threadNumber);
---
> inst->readPC(), inst->seqNum, tid);