2c2
< * Copyright (c) 2004-2005 The Regents of The University of Michigan
---
> * Copyright (c) 2004-2006 The Regents of The University of Michigan
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< *
< * Authors: Kevin Lim
30a29,32
> #include <algorithm>
> #include <string>
>
> #include "base/loader/symtab.hh"
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< #include "cpu/o3/commit.hh"
---
> #include "cpu/checker/cpu.hh"
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> #include "cpu/o3/commit.hh"
> #include "cpu/o3/thread_state.hh"
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> using namespace std;
>
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< SimpleCommit<Impl>::SimpleCommit(Params ¶ms)
< : dcacheInterface(params.dcacheInterface),
< iewToCommitDelay(params.iewToCommitDelay),
< renameToROBDelay(params.renameToROBDelay),
< renameWidth(params.renameWidth),
< iewWidth(params.executeWidth),
< commitWidth(params.commitWidth)
---
> DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
> unsigned _tid)
> : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
44c46
< _status = Idle;
---
> this->setFlags(Event::AutoDelete);
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< SimpleCommit<Impl>::regStats()
---
> DefaultCommit<Impl>::TrapEvent::process()
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> // This will get reset by commit if it was switched out at the
> // time of this event processing.
> commit->trapSquash[tid] = true;
> }
>
> template <class Impl>
> const char *
> DefaultCommit<Impl>::TrapEvent::description()
> {
> return "Trap event";
> }
>
> template <class Impl>
> DefaultCommit<Impl>::DefaultCommit(Params *params)
> : squashCounter(0),
> iewToCommitDelay(params->iewToCommitDelay),
> commitToIEWDelay(params->commitToIEWDelay),
> renameToROBDelay(params->renameToROBDelay),
> fetchToCommitDelay(params->commitToFetchDelay),
> renameWidth(params->renameWidth),
> iewWidth(params->executeWidth),
> commitWidth(params->commitWidth),
> numThreads(params->numberOfThreads),
> switchedOut(false),
> trapLatency(params->trapLatency),
> fetchTrapLatency(params->fetchTrapLatency)
> {
> _status = Active;
> _nextStatus = Inactive;
> string policy = params->smtCommitPolicy;
>
> //Convert string to lowercase
> std::transform(policy.begin(), policy.end(), policy.begin(),
> (int(*)(int)) tolower);
>
> //Assign commit policy
> if (policy == "aggressive"){
> commitPolicy = Aggressive;
>
> DPRINTF(Commit,"Commit Policy set to Aggressive.");
> } else if (policy == "roundrobin"){
> commitPolicy = RoundRobin;
>
> //Set-Up Priority List
> for (int tid=0; tid < numThreads; tid++) {
> priority_list.push_back(tid);
> }
>
> DPRINTF(Commit,"Commit Policy set to Round Robin.");
> } else if (policy == "oldestready"){
> commitPolicy = OldestReady;
>
> DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
> } else {
> assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
> "RoundRobin,OldestReady}");
> }
>
> for (int i=0; i < numThreads; i++) {
> commitStatus[i] = Idle;
> changedROBNumEntries[i] = false;
> trapSquash[i] = false;
> xcSquash[i] = false;
> }
>
> fetchFaultTick = 0;
> fetchTrapWait = 0;
> }
>
> template <class Impl>
> std::string
> DefaultCommit<Impl>::name() const
> {
> return cpu->name() + ".commit";
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::regStats()
> {
> using namespace Stats;
68,79d150
< commitCommittedBranches
< .name(name() + ".commitCommittedBranches")
< .desc("The number of committed branches")
< .prereq(commitCommittedBranches);
< commitCommittedLoads
< .name(name() + ".commitCommittedLoads")
< .desc("The number of committed loads")
< .prereq(commitCommittedLoads);
< commitCommittedMemRefs
< .name(name() + ".commitCommittedMemRefs")
< .desc("The number of committed memory references")
< .prereq(commitCommittedMemRefs);
84c155
< n_committed_dist
---
> numCommittedDist
89a161,227
>
> statComInst
> .init(cpu->number_of_threads)
> .name(name() + ".COM:count")
> .desc("Number of instructions committed")
> .flags(total)
> ;
>
> statComSwp
> .init(cpu->number_of_threads)
> .name(name() + ".COM:swp_count")
> .desc("Number of s/w prefetches committed")
> .flags(total)
> ;
>
> statComRefs
> .init(cpu->number_of_threads)
> .name(name() + ".COM:refs")
> .desc("Number of memory references committed")
> .flags(total)
> ;
>
> statComLoads
> .init(cpu->number_of_threads)
> .name(name() + ".COM:loads")
> .desc("Number of loads committed")
> .flags(total)
> ;
>
> statComMembars
> .init(cpu->number_of_threads)
> .name(name() + ".COM:membars")
> .desc("Number of memory barriers committed")
> .flags(total)
> ;
>
> statComBranches
> .init(cpu->number_of_threads)
> .name(name() + ".COM:branches")
> .desc("Number of branches committed")
> .flags(total)
> ;
>
> //
> // Commit-Eligible instructions...
> //
> // -> The number of instructions eligible to commit in those
> // cycles where we reached our commit BW limit (less the number
> // actually committed)
> //
> // -> The average value is computed over ALL CYCLES... not just
> // the BW limited cycles
> //
> // -> The standard deviation is computed only over cycles where
> // we reached the BW limit
> //
> commitEligible
> .init(cpu->number_of_threads)
> .name(name() + ".COM:bw_limited")
> .desc("number of insts not committed due to BW limits")
> .flags(total)
> ;
>
> commitEligibleSamples
> .name(name() + ".COM:bw_lim_events")
> .desc("number cycles where commit BW limit reached")
> ;
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< SimpleCommit<Impl>::setCPU(FullCPU *cpu_ptr)
---
> DefaultCommit<Impl>::setCPU(FullCPU *cpu_ptr)
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>
> // Commit must broadcast the number of free entries it has at the start of
> // the simulation, so it starts as active.
> cpu->activateStage(FullCPU::CommitIdx);
>
> trapLatency = cpu->cycles(trapLatency);
> fetchTrapLatency = cpu->cycles(fetchTrapLatency);
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< SimpleCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
---
> DefaultCommit<Impl>::setThreads(vector<Thread *> &threads)
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> thread = threads;
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
> {
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< SimpleCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
---
> DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
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> DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n");
> fetchQueue = fq_ptr;
>
> // Setup wire to get instructions from rename (for the ROB).
> fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
> {
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< SimpleCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
---
> DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
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< SimpleCommit<Impl>::setROB(ROB *rob_ptr)
---
> DefaultCommit<Impl>::setFetchStage(Fetch *fetch_stage)
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> fetchStage = fetch_stage;
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
> {
> iewStage = iew_stage;
> }
>
> template<class Impl>
> void
> DefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr)
> {
> DPRINTF(Commit, "Commit: Setting active threads list pointer.\n");
> activeThreads = at_ptr;
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
> {
> DPRINTF(Commit, "Setting rename map pointers.\n");
>
> for (int i=0; i < numThreads; i++) {
> renameMap[i] = &rm_ptr[i];
> }
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::setROB(ROB *rob_ptr)
> {
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< SimpleCommit<Impl>::tick()
---
> DefaultCommit<Impl>::initStage()
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< // If the ROB is currently in its squash sequence, then continue
< // to squash. In this case, commit does not do anything. Otherwise
< // run commit.
< if (_status == ROBSquashing) {
< if (rob->isDoneSquashing()) {
< _status = Running;
< } else {
< rob->doSquash();
---
> rob->setActiveThreads(activeThreads);
> rob->resetEntries();
157,163c347,402
< // Send back sequence number of tail of ROB, so other stages
< // can squash younger instructions. Note that really the only
< // stage that this is important for is the IEW stage; other
< // stages can just clear all their state as long as selective
< // replay isn't used.
< toIEW->commitInfo.doneSeqNum = rob->readTailSeqNum();
< toIEW->commitInfo.robSquashing = true;
---
> // Broadcast the number of free entries.
> for (int i=0; i < numThreads; i++) {
> toIEW->commitInfo[i].usedROB = true;
> toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
> }
>
> cpu->activityThisCycle();
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::switchOut()
> {
> switchPending = true;
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::doSwitchOut()
> {
> switchedOut = true;
> switchPending = false;
> rob->switchOut();
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::takeOverFrom()
> {
> switchedOut = false;
> _status = Active;
> _nextStatus = Inactive;
> for (int i=0; i < numThreads; i++) {
> commitStatus[i] = Idle;
> changedROBNumEntries[i] = false;
> trapSquash[i] = false;
> xcSquash[i] = false;
> }
> squashCounter = 0;
> rob->takeOverFrom();
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::updateStatus()
> {
> // reset ROB changed variable
> list<unsigned>::iterator threads = (*activeThreads).begin();
> while (threads != (*activeThreads).end()) {
> unsigned tid = *threads++;
> changedROBNumEntries[tid] = false;
>
> // Also check if any of the threads has a trap pending
> if (commitStatus[tid] == TrapPending ||
> commitStatus[tid] == FetchTrapPending) {
> _nextStatus = Active;
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< } else {
< commit();
168a406,593
> if (_nextStatus == Inactive && _status == Active) {
> DPRINTF(Activity, "Deactivating stage.\n");
> cpu->deactivateStage(FullCPU::CommitIdx);
> } else if (_nextStatus == Active && _status == Inactive) {
> DPRINTF(Activity, "Activating stage.\n");
> cpu->activateStage(FullCPU::CommitIdx);
> }
>
> _status = _nextStatus;
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::setNextStatus()
> {
> int squashes = 0;
>
> list<unsigned>::iterator threads = (*activeThreads).begin();
>
> while (threads != (*activeThreads).end()) {
> unsigned tid = *threads++;
>
> if (commitStatus[tid] == ROBSquashing) {
> squashes++;
> }
> }
>
> assert(squashes == squashCounter);
>
> // If commit is currently squashing, then it will have activity for the
> // next cycle. Set its next status as active.
> if (squashCounter) {
> _nextStatus = Active;
> }
> }
>
> template <class Impl>
> bool
> DefaultCommit<Impl>::changedROBEntries()
> {
> list<unsigned>::iterator threads = (*activeThreads).begin();
>
> while (threads != (*activeThreads).end()) {
> unsigned tid = *threads++;
>
> if (changedROBNumEntries[tid]) {
> return true;
> }
> }
>
> return false;
> }
>
> template <class Impl>
> unsigned
> DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
> {
> return rob->numFreeEntries(tid);
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
> {
> DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
>
> TrapEvent *trap = new TrapEvent(this, tid);
>
> trap->schedule(curTick + trapLatency);
>
> thread[tid]->trapPending = true;
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::generateXCEvent(unsigned tid)
> {
> DPRINTF(Commit, "Generating XC squash event for [tid:%i]\n", tid);
>
> xcSquash[tid] = true;
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::squashAll(unsigned tid)
> {
> // If we want to include the squashing instruction in the squash,
> // then use one older sequence number.
> // Hopefully this doesn't mess things up. Basically I want to squash
> // all instructions of this thread.
> InstSeqNum squashed_inst = rob->isEmpty() ?
> 0 : rob->readHeadInst(tid)->seqNum - 1;;
>
> // All younger instructions will be squashed. Set the sequence
> // number as the youngest instruction in the ROB (0 in this case.
> // Hopefully nothing breaks.)
> youngestSeqNum[tid] = 0;
>
> rob->squash(squashed_inst, tid);
> changedROBNumEntries[tid] = true;
>
> // Send back the sequence number of the squashed instruction.
> toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
>
> // Send back the squash signal to tell stages that they should
> // squash.
> toIEW->commitInfo[tid].squash = true;
>
> // Send back the rob squashing signal so other stages know that
> // the ROB is in the process of squashing.
> toIEW->commitInfo[tid].robSquashing = true;
>
> toIEW->commitInfo[tid].branchMispredict = false;
>
> toIEW->commitInfo[tid].nextPC = PC[tid];
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::squashFromTrap(unsigned tid)
> {
> squashAll(tid);
>
> DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
>
> thread[tid]->trapPending = false;
> thread[tid]->inSyscall = false;
>
> trapSquash[tid] = false;
>
> commitStatus[tid] = ROBSquashing;
> cpu->activityThisCycle();
>
> ++squashCounter;
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::squashFromXC(unsigned tid)
> {
> squashAll(tid);
>
> DPRINTF(Commit, "Squashing from XC, restarting at PC %#x\n", PC[tid]);
>
> thread[tid]->inSyscall = false;
> assert(!thread[tid]->trapPending);
>
> commitStatus[tid] = ROBSquashing;
> cpu->activityThisCycle();
>
> xcSquash[tid] = false;
>
> ++squashCounter;
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::tick()
> {
> wroteToTimeBuffer = false;
> _nextStatus = Inactive;
>
> if (switchPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
> cpu->signalSwitched();
> return;
> }
>
> list<unsigned>::iterator threads = (*activeThreads).begin();
>
> // Check if any of the threads are done squashing. Change the
> // status if they are done.
> while (threads != (*activeThreads).end()) {
> unsigned tid = *threads++;
>
> if (commitStatus[tid] == ROBSquashing) {
>
> if (rob->isDoneSquashing(tid)) {
> commitStatus[tid] = Running;
> --squashCounter;
> } else {
> DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
> "insts this cycle.\n", tid);
> }
> }
> }
>
> commit();
>
171,174c596,630
< // Writeback number of free ROB entries here.
< DPRINTF(Commit, "Commit: ROB has %d free entries.\n",
< rob->numFreeEntries());
< toIEW->commitInfo.freeROBEntries = rob->numFreeEntries();
---
> threads = (*activeThreads).begin();
>
> while (threads != (*activeThreads).end()) {
> unsigned tid = *threads++;
>
> if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
> // The ROB has more instructions it can commit. Its next status
> // will be active.
> _nextStatus = Active;
>
> DynInstPtr inst = rob->readHeadInst(tid);
>
> DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
> " ROB and ready to commit\n",
> tid, inst->seqNum, inst->readPC());
>
> } else if (!rob->isEmpty(tid)) {
> DynInstPtr inst = rob->readHeadInst(tid);
>
> DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
> "%#x is head of ROB and not ready\n",
> tid, inst->seqNum, inst->readPC());
> }
>
> DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
> tid, rob->countInsts(tid), rob->numFreeEntries(tid));
> }
>
>
> if (wroteToTimeBuffer) {
> DPRINTF(Activity, "Activity This Cycle.\n");
> cpu->activityThisCycle();
> }
>
> updateStatus();
179c635
< SimpleCommit<Impl>::commit()
---
> DefaultCommit<Impl>::commit()
180a637
>
185,190d641
< // Process interrupts if interrupts are enabled and not in PAL mode.
< // Take the PC from commit and write it to the IPR, then squash. The
< // interrupt completing will take care of restoring the PC from that value
< // in the IPR. Look at IPR[EXC_ADDR];
< // hwrei() is what resets the PC to the place where instruction execution
< // beings again.
192c643,646
< if (//checkInterrupts &&
---
> // Process interrupts if interrupts are enabled, not in PAL mode,
> // and no other traps or external squashes are currently pending.
> // @todo: Allow other threads to handle interrupts.
> if (cpu->checkInterrupts &&
194,199c648,654
< !cpu->inPalMode(readCommitPC())) {
< // Will need to squash all instructions currently in flight and have
< // the interrupt handler restart at the last non-committed inst.
< // Most of that can be handled through the trap() function. The
< // processInterrupts() function really just checks for interrupts
< // and then calls trap() if there is an interrupt present.
---
> !cpu->inPalMode(readPC()) &&
> !trapSquash[0] &&
> !xcSquash[0]) {
> // Tell fetch that there is an interrupt pending. This will
> // make fetch wait until it sees a non PAL-mode PC, at which
> // point it stops fetching instructions.
> toIEW->commitInfo[0].interruptPending = true;
201,202c656,681
< // CPU will handle implementation of the interrupt.
< cpu->processInterrupts();
---
> // Wait until the ROB is empty and all stores have drained in
> // order to enter the interrupt.
> if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
> // Not sure which thread should be the one to interrupt. For now
> // always do thread 0.
> assert(!thread[0]->inSyscall);
> thread[0]->inSyscall = true;
>
> // CPU will handle implementation of the interrupt.
> cpu->processInterrupts();
>
> // Now squash or record that I need to squash this cycle.
> commitStatus[0] = TrapPending;
>
> // Exit state update mode to avoid accidental updating.
> thread[0]->inSyscall = false;
>
> // Generate trap squash event.
> generateTrapEvent(0);
>
> toIEW->commitInfo[0].clearInterrupt = true;
>
> DPRINTF(Commit, "Interrupt detected.\n");
> } else {
> DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
> }
207c686
< // Check for squash signal, handle that first
---
> // Check for any possible squashes, handle them first
210,215c689
< // Want to mainly check if the IEW stage is telling the ROB to squash.
< // Should I also check if the commit stage is telling the ROB to squah?
< // This might be necessary to keep the same timing between the IQ and
< // the ROB...
< if (fromIEW->squash) {
< DPRINTF(Commit, "Commit: Squashing instructions in the ROB.\n");
---
> list<unsigned>::iterator threads = (*activeThreads).begin();
217c691,692
< _status = ROBSquashing;
---
> while (threads != (*activeThreads).end()) {
> unsigned tid = *threads++;
219c694,704
< InstSeqNum squashed_inst = fromIEW->squashedSeqNum;
---
> if (fromFetch->fetchFault && commitStatus[0] != TrapPending) {
> // Record the fault. Wait until it's empty in the ROB.
> // Then handle the trap. Ignore it if there's already a
> // trap pending as fetch will be redirected.
> fetchFault = fromFetch->fetchFault;
> fetchFaultTick = curTick + fetchTrapLatency;
> commitStatus[0] = FetchTrapPending;
> DPRINTF(Commit, "Fault from fetch recorded. Will trap if the "
> "ROB empties without squashing the fault.\n");
> fetchTrapWait = 0;
> }
221c706,714
< rob->squash(squashed_inst);
---
> // Fetch may tell commit to clear the trap if it's been squashed.
> if (fromFetch->clearFetchFault) {
> DPRINTF(Commit, "Received clear fetch fault signal\n");
> fetchTrapWait = 0;
> if (commitStatus[0] == FetchTrapPending) {
> DPRINTF(Commit, "Clearing fault from fetch\n");
> commitStatus[0] = Running;
> }
> }
223,224c716,723
< // Send back the sequence number of the squashed instruction.
< toIEW->commitInfo.doneSeqNum = squashed_inst;
---
> // Not sure which one takes priority. I think if we have
> // both, that's a bad sign.
> if (trapSquash[tid] == true) {
> assert(!xcSquash[tid]);
> squashFromTrap(tid);
> } else if (xcSquash[tid] == true) {
> squashFromXC(tid);
> }
226,227c725,730
< // Send back the squash signal to tell stages that they should squash.
< toIEW->commitInfo.squash = true;
---
> // Squashed sequence number must be older than youngest valid
> // instruction in the ROB. This prevents squashes from younger
> // instructions overriding squashes from older instructions.
> if (fromIEW->squash[tid] &&
> commitStatus[tid] != TrapPending &&
> fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
229,231c732,735
< // Send back the rob squashing signal so other stages know that the
< // ROB is in the process of squashing.
< toIEW->commitInfo.robSquashing = true;
---
> DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
> tid,
> fromIEW->mispredPC[tid],
> fromIEW->squashedSeqNum[tid]);
233c737,739
< toIEW->commitInfo.branchMispredict = fromIEW->branchMispredict;
---
> DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
> tid,
> fromIEW->nextPC[tid]);
235c741
< toIEW->commitInfo.branchTaken = fromIEW->branchTaken;
---
> commitStatus[tid] = ROBSquashing;
237c743
< toIEW->commitInfo.nextPC = fromIEW->nextPC;
---
> ++squashCounter;
239c745,747
< toIEW->commitInfo.mispredPC = fromIEW->mispredPC;
---
> // If we want to include the squashing instruction in the squash,
> // then use one older sequence number.
> InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
241,242c749,779
< if (toIEW->commitInfo.branchMispredict) {
< ++branchMispredicts;
---
> if (fromIEW->includeSquashInst[tid] == true)
> squashed_inst--;
>
> // All younger instructions will be squashed. Set the sequence
> // number as the youngest instruction in the ROB.
> youngestSeqNum[tid] = squashed_inst;
>
> rob->squash(squashed_inst, tid);
> changedROBNumEntries[tid] = true;
>
> toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
>
> toIEW->commitInfo[tid].squash = true;
>
> // Send back the rob squashing signal so other stages know that
> // the ROB is in the process of squashing.
> toIEW->commitInfo[tid].robSquashing = true;
>
> toIEW->commitInfo[tid].branchMispredict =
> fromIEW->branchMispredict[tid];
>
> toIEW->commitInfo[tid].branchTaken =
> fromIEW->branchTaken[tid];
>
> toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
>
> toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
>
> if (toIEW->commitInfo[tid].branchMispredict) {
> ++branchMispredicts;
> }
243a781
>
246c784,786
< if (_status != ROBSquashing) {
---
> setNextStatus();
>
> if (squashCounter != numThreads) {
254,261c794,810
< // If the ROB is empty, we can set this stage to idle. Use this
< // in the future when the Idle status will actually be utilized.
< #if 0
< if (rob->isEmpty()) {
< DPRINTF(Commit, "Commit: ROB is empty. Status changed to idle.\n");
< _status = Idle;
< // Schedule an event so that commit will actually wake up
< // once something gets put in the ROB.
---
> //Check for any activity
> threads = (*activeThreads).begin();
>
> while (threads != (*activeThreads).end()) {
> unsigned tid = *threads++;
>
> if (changedROBNumEntries[tid]) {
> toIEW->commitInfo[tid].usedROB = true;
> toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
>
> if (rob->isEmpty(tid)) {
> toIEW->commitInfo[tid].emptyROB = true;
> }
>
> wroteToTimeBuffer = true;
> changedROBNumEntries[tid] = false;
> }
263d811
< #endif
266,268d813
< // Loop that goes through as many instructions in the ROB as possible and
< // tries to commit them. The actual work for committing is done by the
< // commitHead() function.
271c816
< SimpleCommit<Impl>::commitInsts()
---
> DefaultCommit<Impl>::commitInsts()
275,278c820,824
< // Note that commit will be handled prior to the ROB so that the ROB
< // only tries to commit instructions it has in this current cycle, and
< // not instructions it is writing in during this cycle.
< // Can't commit and squash things at the same time...
---
> // Note that commit will be handled prior to putting new
> // instructions in the ROB so that the ROB only tries to commit
> // instructions it has in this current cycle, and not instructions
> // it is writing in during this cycle. Can't commit and squash
> // things at the same time...
281,282c827
< if (rob->isEmpty())
< return;
---
> DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
284,285d828
< DynInstPtr head_inst = rob->readHeadInst();
<
287a831,832
> DynInstPtr head_inst;
>
290,294c835,836
< while (!rob->isEmpty() &&
< head_inst->readyToCommit() &&
< num_committed < commitWidth)
< {
< DPRINTF(Commit, "Commit: Trying to commit head instruction.\n");
---
> while (num_committed < commitWidth) {
> int commit_thread = getCommittingThread();
296,298c838,851
< // If the head instruction is squashed, it is ready to retire at any
< // time. However, we need to avoid updating any other state
< // incorrectly if it's already been squashed.
---
> if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
> break;
>
> head_inst = rob->readHeadInst(commit_thread);
>
> int tid = head_inst->threadNumber;
>
> assert(tid == commit_thread);
>
> DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
> head_inst->seqNum, tid);
>
> // If the head instruction is squashed, it is ready to retire
> // (be removed from the ROB) at any time.
301c854
< DPRINTF(Commit, "Commit: Retiring squashed instruction from "
---
> DPRINTF(Commit, "Retiring squashed instruction from "
304,306c857
< // Tell ROB to retire head instruction. This retires the head
< // inst in the ROB without affecting any other stages.
< rob->retireHead();
---
> rob->retireHead(commit_thread);
309a861,862
> // Record that the number of ROB entries has changed.
> changedROBNumEntries[tid] = true;
310a864,866
> PC[tid] = head_inst->readPC();
> nextPC[tid] = head_inst->readNextPC();
>
316c872
< cpu->funcExeInst++;
---
> thread[tid]->funcExeInst++;
321d876
< // Update what instruction we are looking at if the commit worked.
325,329c880
< // Send back which instruction has been committed.
< // @todo: Update this later when a wider pipeline is used.
< // Hmm, can't really give a pointer here...perhaps the
< // sequence number instead (copy).
< toIEW->commitInfo.doneSeqNum = head_inst->seqNum;
---
> changedROBNumEntries[tid] = true;
330a882,884
> // Set the doneSeqNum to the youngest committed instruction.
> toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
>
333,334c887,890
< if (!head_inst->isNop()) {
< cpu->instDone();
---
> // To match the old model, don't count nops and instruction
> // prefetches towards the total commit count.
> if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
> cpu->instDone(tid);
335a892,913
>
> PC[tid] = nextPC[tid];
> nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
> #if FULL_SYSTEM
> int count = 0;
> Addr oldpc;
> do {
> // Debug statement. Checks to make sure we're not
> // currently updating state while handling PC events.
> if (count == 0)
> assert(!thread[tid]->inSyscall &&
> !thread[tid]->trapPending);
> oldpc = PC[tid];
> cpu->system->pcEventQueue.service(
> thread[tid]->getXCProxy());
> count++;
> } while (oldpc != PC[tid]);
> if (count > 1) {
> DPRINTF(Commit, "PC skip function event, stopping commit\n");
> break;
> }
> #endif
336a915,917
> DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
> "[tid:%i] [sn:%i].\n",
> head_inst->readPC(), tid ,head_inst->seqNum);
340,342d920
<
< // Update the pointer to read the next instruction in the ROB.
< head_inst = rob->readHeadInst();
346c924,928
< n_committed_dist.sample(num_committed);
---
> numCommittedDist.sample(num_committed);
>
> if (num_committed == commitWidth) {
> commitEligible[0]++;
> }
351c933
< SimpleCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
---
> DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
353d934
< // Make sure instruction is valid
356,357c937,940
< // If the instruction is not executed yet, then it is a non-speculative
< // or store inst. Signal backwards that it should be executed.
---
> int tid = head_inst->threadNumber;
>
> // If the instruction is not executed yet, then it will need extra
> // handling. Signal backwards that it should be executed.
361c944
< cpu->funcExeInst--;
---
> thread[tid]->funcExeInst--;
363,366c946
< if (head_inst->isNonSpeculative()) {
< DPRINTF(Commit, "Commit: Encountered a store or non-speculative "
< "instruction at the head of the ROB, PC %#x.\n",
< head_inst->readPC());
---
> head_inst->reachedCommit = true;
368c948,950
< toIEW->commitInfo.nonSpecSeqNum = head_inst->seqNum;
---
> if (head_inst->isNonSpeculative() ||
> head_inst->isMemBarrier() ||
> head_inst->isWriteBarrier()) {
369a952,973
> DPRINTF(Commit, "Encountered a barrier or non-speculative "
> "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
> head_inst->seqNum, head_inst->readPC());
>
> #if !FULL_SYSTEM
> // Hack to make sure syscalls/memory barriers/quiesces
> // aren't executed until all stores write back their data.
> // This direct communication shouldn't be used for
> // anything other than this.
> if (inst_num > 0 || iewStage->hasStoresToWB())
> #else
> if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
> head_inst->isQuiesce()) &&
> iewStage->hasStoresToWB())
> #endif
> {
> DPRINTF(Commit, "Waiting for all stores to writeback.\n");
> return false;
> }
>
> toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
>
376a981,993
> } else if (head_inst->isLoad()) {
> DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
> head_inst->seqNum, head_inst->readPC());
>
> // Send back the non-speculative instruction's sequence
> // number. Tell the lsq to re-execute the load.
> toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
> toIEW->commitInfo[tid].uncached = true;
> toIEW->commitInfo[tid].uncachedLoad = head_inst;
>
> head_inst->clearCanCommit();
>
> return false;
378c995
< panic("Commit: Trying to commit un-executed instruction "
---
> panic("Trying to commit un-executed instruction "
383,394c1000,1002
< // Now check if it's one of the special trap or barrier or
< // serializing instructions.
< if (head_inst->isThreadSync() ||
< head_inst->isSerializing() ||
< head_inst->isMemBarrier() ||
< head_inst->isWriteBarrier() )
< {
< // Not handled for now. Mem barriers and write barriers are safe
< // to simply let commit as memory accesses only happen once they
< // reach the head of commit. Not sure about the other two.
< panic("Serializing or barrier instructions"
< " are not handled yet.\n");
---
> if (head_inst->isThreadSync()) {
> // Not handled for now.
> panic("Thread sync instructions are not handled yet.\n");
396a1005,1015
> // Stores mark themselves as completed.
> if (!head_inst->isStore()) {
> head_inst->setCompleted();
> }
>
> // Use checker prior to updating anything due to traps or PC
> // based events.
> if (cpu->checker) {
> cpu->checker->tick(head_inst);
> }
>
401c1020
< if (!head_inst->isNop()) {
---
> head_inst->setCompleted();
403,407c1022,1027
< cpu->trap(inst_fault);
< #else // !FULL_SYSTEM
< panic("fault (%d) detected @ PC %08p", inst_fault,
< head_inst->PC);
< #endif // FULL_SYSTEM
---
> DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
> head_inst->seqNum, head_inst->readPC());
>
> if (iewStage->hasStoresToWB() || inst_num > 0) {
> DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
> return false;
409d1028
< }
411,417c1030,1032
< // Check if we're really ready to commit. If not then return false.
< // I'm pretty sure all instructions should be able to commit if they've
< // reached this far. For now leave this in as a check.
< if (!rob->isHeadReady()) {
< panic("Commit: Unable to commit head instruction!\n");
< return false;
< }
---
> if (cpu->checker && head_inst->isStore()) {
> cpu->checker->tick(head_inst);
> }
419,421c1034
< // If it's a branch, then send back branch prediction update info
< // to the fetch stage.
< // This should be handled in the iew stage if a mispredict happens...
---
> assert(!thread[tid]->inSyscall);
423c1036,1038
< if (head_inst->isControl()) {
---
> // Mark that we're in state update mode so that the trap's
> // execution doesn't generate extra squashes.
> thread[tid]->inSyscall = true;
425,432c1040,1044
< #if 0
< toIEW->nextPC = head_inst->readPC();
< //Maybe switch over to BTB incorrect.
< toIEW->btbMissed = head_inst->btbMiss();
< toIEW->target = head_inst->nextPC;
< //Maybe also include global history information.
< //This simple version will have no branch prediction however.
< #endif
---
> // DTB will sometimes need the machine instruction for when
> // faults happen. So we will set it here, prior to the DTB
> // possibly needing it for its fault.
> thread[tid]->setInst(
> static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
434c1046,1066
< ++commitCommittedBranches;
---
> // Execute the trap. Although it's slightly unrealistic in
> // terms of timing (as it doesn't wait for the full timing of
> // the trap event to complete before updating state), it's
> // needed to update the state as soon as possible. This
> // prevents external agents from changing any specific state
> // that the trap need.
> cpu->trap(inst_fault, tid);
>
> // Exit state update mode to avoid accidental updating.
> thread[tid]->inSyscall = false;
>
> commitStatus[tid] = TrapPending;
>
> // Generate trap squash event.
> generateTrapEvent(tid);
>
> return false;
> #else // !FULL_SYSTEM
> panic("fault (%d) detected @ PC %08p", inst_fault,
> head_inst->PC);
> #endif // FULL_SYSTEM
437,438c1069,1070
< // Now that the instruction is going to be committed, finalize its
< // trace data.
---
> updateComInstStats(head_inst);
>
439a1072,1073
> head_inst->traceData->setFetchSeq(head_inst->seqNum);
> head_inst->traceData->setCPSeq(thread[tid]->numInst);
440a1075
> head_inst->traceData = NULL;
443,444c1078,1082
< //Finally clear the head ROB entry.
< rob->retireHead();
---
> // Update the commit rename map
> for (int i = 0; i < head_inst->numDestRegs(); i++) {
> renameMap[tid]->setEntry(head_inst->destRegIdx(i),
> head_inst->renamedDestRegIdx(i));
> }
445a1084,1086
> // Finally clear the head ROB entry.
> rob->retireHead(tid);
>
452c1093
< SimpleCommit<Impl>::getInsts()
---
> DefaultCommit<Impl>::getInsts()
454,460c1095
< //////////////////////////////////////
< // Handle ROB functions
< //////////////////////////////////////
<
< // Read any issued instructions and place them into the ROB. Do this
< // prior to squashing to avoid having instructions in the ROB that
< // don't get squashed properly.
---
> // Read any renamed instructions and place them into the ROB.
463,465c1098
< for (int inst_num = 0;
< inst_num < insts_to_process;
< ++inst_num)
---
> for (int inst_num = 0; inst_num < insts_to_process; ++inst_num)
467,470c1100,1114
< if (!fromRename->insts[inst_num]->isSquashed()) {
< DPRINTF(Commit, "Commit: Inserting PC %#x into ROB.\n",
< fromRename->insts[inst_num]->readPC());
< rob->insertInst(fromRename->insts[inst_num]);
---
> DynInstPtr inst = fromRename->insts[inst_num];
> int tid = inst->threadNumber;
>
> if (!inst->isSquashed() &&
> commitStatus[tid] != ROBSquashing) {
> changedROBNumEntries[tid] = true;
>
> DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
> inst->readPC(), inst->seqNum, tid);
>
> rob->insertInst(inst);
>
> assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
>
> youngestSeqNum[tid] = inst->seqNum;
472c1116
< DPRINTF(Commit, "Commit: Instruction %i PC %#x was "
---
> DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
474,475c1118
< fromRename->insts[inst_num]->seqNum,
< fromRename->insts[inst_num]->readPC());
---
> inst->readPC(), inst->seqNum, tid);
482c1125
< SimpleCommit<Impl>::markCompletedInsts()
---
> DefaultCommit<Impl>::markCompletedInsts()
490,492c1133,1138
< DPRINTF(Commit, "Commit: Marking PC %#x, SN %i ready within ROB.\n",
< fromIEW->insts[inst_num]->readPC(),
< fromIEW->insts[inst_num]->seqNum);
---
> if (!fromIEW->insts[inst_num]->isSquashed()) {
> DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
> "within ROB.\n",
> fromIEW->insts[inst_num]->threadNumber,
> fromIEW->insts[inst_num]->readPC(),
> fromIEW->insts[inst_num]->seqNum);
494,495c1140,1142
< // Mark the instruction as ready to commit.
< fromIEW->insts[inst_num]->setCanCommit();
---
> // Mark the instruction as ready to commit.
> fromIEW->insts[inst_num]->setCanCommit();
> }
500,501c1147,1148
< uint64_t
< SimpleCommit<Impl>::readCommitPC()
---
> bool
> DefaultCommit<Impl>::robDoneSquashing()
503c1150,1159
< return rob->readHeadPC();
---
> list<unsigned>::iterator threads = (*activeThreads).begin();
>
> while (threads != (*activeThreads).end()) {
> unsigned tid = *threads++;
>
> if (!rob->isDoneSquashing(tid))
> return false;
> }
>
> return true;
504a1161,1306
>
> template <class Impl>
> void
> DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
> {
> unsigned thread = inst->threadNumber;
>
> //
> // Pick off the software prefetches
> //
> #ifdef TARGET_ALPHA
> if (inst->isDataPrefetch()) {
> statComSwp[thread]++;
> } else {
> statComInst[thread]++;
> }
> #else
> statComInst[thread]++;
> #endif
>
> //
> // Control Instructions
> //
> if (inst->isControl())
> statComBranches[thread]++;
>
> //
> // Memory references
> //
> if (inst->isMemRef()) {
> statComRefs[thread]++;
>
> if (inst->isLoad()) {
> statComLoads[thread]++;
> }
> }
>
> if (inst->isMemBarrier()) {
> statComMembars[thread]++;
> }
> }
>
> ////////////////////////////////////////
> // //
> // SMT COMMIT POLICY MAINTAINED HERE //
> // //
> ////////////////////////////////////////
> template <class Impl>
> int
> DefaultCommit<Impl>::getCommittingThread()
> {
> if (numThreads > 1) {
> switch (commitPolicy) {
>
> case Aggressive:
> //If Policy is Aggressive, commit will call
> //this function multiple times per
> //cycle
> return oldestReady();
>
> case RoundRobin:
> return roundRobin();
>
> case OldestReady:
> return oldestReady();
>
> default:
> return -1;
> }
> } else {
> int tid = (*activeThreads).front();
>
> if (commitStatus[tid] == Running ||
> commitStatus[tid] == Idle ||
> commitStatus[tid] == FetchTrapPending) {
> return tid;
> } else {
> return -1;
> }
> }
> }
>
> template<class Impl>
> int
> DefaultCommit<Impl>::roundRobin()
> {
> list<unsigned>::iterator pri_iter = priority_list.begin();
> list<unsigned>::iterator end = priority_list.end();
>
> while (pri_iter != end) {
> unsigned tid = *pri_iter;
>
> if (commitStatus[tid] == Running ||
> commitStatus[tid] == Idle) {
>
> if (rob->isHeadReady(tid)) {
> priority_list.erase(pri_iter);
> priority_list.push_back(tid);
>
> return tid;
> }
> }
>
> pri_iter++;
> }
>
> return -1;
> }
>
> template<class Impl>
> int
> DefaultCommit<Impl>::oldestReady()
> {
> unsigned oldest = 0;
> bool first = true;
>
> list<unsigned>::iterator threads = (*activeThreads).begin();
>
> while (threads != (*activeThreads).end()) {
> unsigned tid = *threads++;
>
> if (!rob->isEmpty(tid) &&
> (commitStatus[tid] == Running ||
> commitStatus[tid] == Idle ||
> commitStatus[tid] == FetchTrapPending)) {
>
> if (rob->isHeadReady(tid)) {
>
> DynInstPtr head_inst = rob->readHeadInst(tid);
>
> if (first) {
> oldest = tid;
> first = false;
> } else if (head_inst->seqNum < oldest) {
> oldest = tid;
> }
> }
> }
> }
>
> if (!first) {
> return oldest;
> } else {
> return -1;
> }
> }
< * Copyright (c) 2004-2005 The Regents of The University of Michigan
---
> * Copyright (c) 2004-2006 The Regents of The University of Michigan
27,28d26
< *
< * Authors: Kevin Lim
30a29,32
> #include <algorithm>
> #include <string>
>
> #include "base/loader/symtab.hh"
32c34
< #include "cpu/o3/commit.hh"
---
> #include "cpu/checker/cpu.hh"
33a36,37
> #include "cpu/o3/commit.hh"
> #include "cpu/o3/thread_state.hh"
34a39,40
> using namespace std;
>
36,42c42,44
< SimpleCommit<Impl>::SimpleCommit(Params ¶ms)
< : dcacheInterface(params.dcacheInterface),
< iewToCommitDelay(params.iewToCommitDelay),
< renameToROBDelay(params.renameToROBDelay),
< renameWidth(params.renameWidth),
< iewWidth(params.executeWidth),
< commitWidth(params.commitWidth)
---
> DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
> unsigned _tid)
> : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
44c46
< _status = Idle;
---
> this->setFlags(Event::AutoDelete);
49c51
< SimpleCommit<Impl>::regStats()
---
> DefaultCommit<Impl>::TrapEvent::process()
50a53,133
> // This will get reset by commit if it was switched out at the
> // time of this event processing.
> commit->trapSquash[tid] = true;
> }
>
> template <class Impl>
> const char *
> DefaultCommit<Impl>::TrapEvent::description()
> {
> return "Trap event";
> }
>
> template <class Impl>
> DefaultCommit<Impl>::DefaultCommit(Params *params)
> : squashCounter(0),
> iewToCommitDelay(params->iewToCommitDelay),
> commitToIEWDelay(params->commitToIEWDelay),
> renameToROBDelay(params->renameToROBDelay),
> fetchToCommitDelay(params->commitToFetchDelay),
> renameWidth(params->renameWidth),
> iewWidth(params->executeWidth),
> commitWidth(params->commitWidth),
> numThreads(params->numberOfThreads),
> switchedOut(false),
> trapLatency(params->trapLatency),
> fetchTrapLatency(params->fetchTrapLatency)
> {
> _status = Active;
> _nextStatus = Inactive;
> string policy = params->smtCommitPolicy;
>
> //Convert string to lowercase
> std::transform(policy.begin(), policy.end(), policy.begin(),
> (int(*)(int)) tolower);
>
> //Assign commit policy
> if (policy == "aggressive"){
> commitPolicy = Aggressive;
>
> DPRINTF(Commit,"Commit Policy set to Aggressive.");
> } else if (policy == "roundrobin"){
> commitPolicy = RoundRobin;
>
> //Set-Up Priority List
> for (int tid=0; tid < numThreads; tid++) {
> priority_list.push_back(tid);
> }
>
> DPRINTF(Commit,"Commit Policy set to Round Robin.");
> } else if (policy == "oldestready"){
> commitPolicy = OldestReady;
>
> DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
> } else {
> assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
> "RoundRobin,OldestReady}");
> }
>
> for (int i=0; i < numThreads; i++) {
> commitStatus[i] = Idle;
> changedROBNumEntries[i] = false;
> trapSquash[i] = false;
> xcSquash[i] = false;
> }
>
> fetchFaultTick = 0;
> fetchTrapWait = 0;
> }
>
> template <class Impl>
> std::string
> DefaultCommit<Impl>::name() const
> {
> return cpu->name() + ".commit";
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::regStats()
> {
> using namespace Stats;
68,79d150
< commitCommittedBranches
< .name(name() + ".commitCommittedBranches")
< .desc("The number of committed branches")
< .prereq(commitCommittedBranches);
< commitCommittedLoads
< .name(name() + ".commitCommittedLoads")
< .desc("The number of committed loads")
< .prereq(commitCommittedLoads);
< commitCommittedMemRefs
< .name(name() + ".commitCommittedMemRefs")
< .desc("The number of committed memory references")
< .prereq(commitCommittedMemRefs);
84c155
< n_committed_dist
---
> numCommittedDist
89a161,227
>
> statComInst
> .init(cpu->number_of_threads)
> .name(name() + ".COM:count")
> .desc("Number of instructions committed")
> .flags(total)
> ;
>
> statComSwp
> .init(cpu->number_of_threads)
> .name(name() + ".COM:swp_count")
> .desc("Number of s/w prefetches committed")
> .flags(total)
> ;
>
> statComRefs
> .init(cpu->number_of_threads)
> .name(name() + ".COM:refs")
> .desc("Number of memory references committed")
> .flags(total)
> ;
>
> statComLoads
> .init(cpu->number_of_threads)
> .name(name() + ".COM:loads")
> .desc("Number of loads committed")
> .flags(total)
> ;
>
> statComMembars
> .init(cpu->number_of_threads)
> .name(name() + ".COM:membars")
> .desc("Number of memory barriers committed")
> .flags(total)
> ;
>
> statComBranches
> .init(cpu->number_of_threads)
> .name(name() + ".COM:branches")
> .desc("Number of branches committed")
> .flags(total)
> ;
>
> //
> // Commit-Eligible instructions...
> //
> // -> The number of instructions eligible to commit in those
> // cycles where we reached our commit BW limit (less the number
> // actually committed)
> //
> // -> The average value is computed over ALL CYCLES... not just
> // the BW limited cycles
> //
> // -> The standard deviation is computed only over cycles where
> // we reached the BW limit
> //
> commitEligible
> .init(cpu->number_of_threads)
> .name(name() + ".COM:bw_limited")
> .desc("number of insts not committed due to BW limits")
> .flags(total)
> ;
>
> commitEligibleSamples
> .name(name() + ".COM:bw_lim_events")
> .desc("number cycles where commit BW limit reached")
> ;
94c232
< SimpleCommit<Impl>::setCPU(FullCPU *cpu_ptr)
---
> DefaultCommit<Impl>::setCPU(FullCPU *cpu_ptr)
97a236,242
>
> // Commit must broadcast the number of free entries it has at the start of
> // the simulation, so it starts as active.
> cpu->activateStage(FullCPU::CommitIdx);
>
> trapLatency = cpu->cycles(trapLatency);
> fetchTrapLatency = cpu->cycles(fetchTrapLatency);
102c247
< SimpleCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
---
> DefaultCommit<Impl>::setThreads(vector<Thread *> &threads)
103a249,255
> thread = threads;
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
> {
116c268
< SimpleCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
---
> DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
117a270,280
> DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n");
> fetchQueue = fq_ptr;
>
> // Setup wire to get instructions from rename (for the ROB).
> fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
> {
127c290
< SimpleCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
---
> DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
138c301
< SimpleCommit<Impl>::setROB(ROB *rob_ptr)
---
> DefaultCommit<Impl>::setFetchStage(Fetch *fetch_stage)
139a303,335
> fetchStage = fetch_stage;
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
> {
> iewStage = iew_stage;
> }
>
> template<class Impl>
> void
> DefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr)
> {
> DPRINTF(Commit, "Commit: Setting active threads list pointer.\n");
> activeThreads = at_ptr;
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
> {
> DPRINTF(Commit, "Setting rename map pointers.\n");
>
> for (int i=0; i < numThreads; i++) {
> renameMap[i] = &rm_ptr[i];
> }
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::setROB(ROB *rob_ptr)
> {
146c342
< SimpleCommit<Impl>::tick()
---
> DefaultCommit<Impl>::initStage()
148,155c344,345
< // If the ROB is currently in its squash sequence, then continue
< // to squash. In this case, commit does not do anything. Otherwise
< // run commit.
< if (_status == ROBSquashing) {
< if (rob->isDoneSquashing()) {
< _status = Running;
< } else {
< rob->doSquash();
---
> rob->setActiveThreads(activeThreads);
> rob->resetEntries();
157,163c347,402
< // Send back sequence number of tail of ROB, so other stages
< // can squash younger instructions. Note that really the only
< // stage that this is important for is the IEW stage; other
< // stages can just clear all their state as long as selective
< // replay isn't used.
< toIEW->commitInfo.doneSeqNum = rob->readTailSeqNum();
< toIEW->commitInfo.robSquashing = true;
---
> // Broadcast the number of free entries.
> for (int i=0; i < numThreads; i++) {
> toIEW->commitInfo[i].usedROB = true;
> toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
> }
>
> cpu->activityThisCycle();
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::switchOut()
> {
> switchPending = true;
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::doSwitchOut()
> {
> switchedOut = true;
> switchPending = false;
> rob->switchOut();
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::takeOverFrom()
> {
> switchedOut = false;
> _status = Active;
> _nextStatus = Inactive;
> for (int i=0; i < numThreads; i++) {
> commitStatus[i] = Idle;
> changedROBNumEntries[i] = false;
> trapSquash[i] = false;
> xcSquash[i] = false;
> }
> squashCounter = 0;
> rob->takeOverFrom();
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::updateStatus()
> {
> // reset ROB changed variable
> list<unsigned>::iterator threads = (*activeThreads).begin();
> while (threads != (*activeThreads).end()) {
> unsigned tid = *threads++;
> changedROBNumEntries[tid] = false;
>
> // Also check if any of the threads has a trap pending
> if (commitStatus[tid] == TrapPending ||
> commitStatus[tid] == FetchTrapPending) {
> _nextStatus = Active;
165,166d403
< } else {
< commit();
168a406,593
> if (_nextStatus == Inactive && _status == Active) {
> DPRINTF(Activity, "Deactivating stage.\n");
> cpu->deactivateStage(FullCPU::CommitIdx);
> } else if (_nextStatus == Active && _status == Inactive) {
> DPRINTF(Activity, "Activating stage.\n");
> cpu->activateStage(FullCPU::CommitIdx);
> }
>
> _status = _nextStatus;
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::setNextStatus()
> {
> int squashes = 0;
>
> list<unsigned>::iterator threads = (*activeThreads).begin();
>
> while (threads != (*activeThreads).end()) {
> unsigned tid = *threads++;
>
> if (commitStatus[tid] == ROBSquashing) {
> squashes++;
> }
> }
>
> assert(squashes == squashCounter);
>
> // If commit is currently squashing, then it will have activity for the
> // next cycle. Set its next status as active.
> if (squashCounter) {
> _nextStatus = Active;
> }
> }
>
> template <class Impl>
> bool
> DefaultCommit<Impl>::changedROBEntries()
> {
> list<unsigned>::iterator threads = (*activeThreads).begin();
>
> while (threads != (*activeThreads).end()) {
> unsigned tid = *threads++;
>
> if (changedROBNumEntries[tid]) {
> return true;
> }
> }
>
> return false;
> }
>
> template <class Impl>
> unsigned
> DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
> {
> return rob->numFreeEntries(tid);
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
> {
> DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
>
> TrapEvent *trap = new TrapEvent(this, tid);
>
> trap->schedule(curTick + trapLatency);
>
> thread[tid]->trapPending = true;
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::generateXCEvent(unsigned tid)
> {
> DPRINTF(Commit, "Generating XC squash event for [tid:%i]\n", tid);
>
> xcSquash[tid] = true;
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::squashAll(unsigned tid)
> {
> // If we want to include the squashing instruction in the squash,
> // then use one older sequence number.
> // Hopefully this doesn't mess things up. Basically I want to squash
> // all instructions of this thread.
> InstSeqNum squashed_inst = rob->isEmpty() ?
> 0 : rob->readHeadInst(tid)->seqNum - 1;;
>
> // All younger instructions will be squashed. Set the sequence
> // number as the youngest instruction in the ROB (0 in this case.
> // Hopefully nothing breaks.)
> youngestSeqNum[tid] = 0;
>
> rob->squash(squashed_inst, tid);
> changedROBNumEntries[tid] = true;
>
> // Send back the sequence number of the squashed instruction.
> toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
>
> // Send back the squash signal to tell stages that they should
> // squash.
> toIEW->commitInfo[tid].squash = true;
>
> // Send back the rob squashing signal so other stages know that
> // the ROB is in the process of squashing.
> toIEW->commitInfo[tid].robSquashing = true;
>
> toIEW->commitInfo[tid].branchMispredict = false;
>
> toIEW->commitInfo[tid].nextPC = PC[tid];
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::squashFromTrap(unsigned tid)
> {
> squashAll(tid);
>
> DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
>
> thread[tid]->trapPending = false;
> thread[tid]->inSyscall = false;
>
> trapSquash[tid] = false;
>
> commitStatus[tid] = ROBSquashing;
> cpu->activityThisCycle();
>
> ++squashCounter;
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::squashFromXC(unsigned tid)
> {
> squashAll(tid);
>
> DPRINTF(Commit, "Squashing from XC, restarting at PC %#x\n", PC[tid]);
>
> thread[tid]->inSyscall = false;
> assert(!thread[tid]->trapPending);
>
> commitStatus[tid] = ROBSquashing;
> cpu->activityThisCycle();
>
> xcSquash[tid] = false;
>
> ++squashCounter;
> }
>
> template <class Impl>
> void
> DefaultCommit<Impl>::tick()
> {
> wroteToTimeBuffer = false;
> _nextStatus = Inactive;
>
> if (switchPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
> cpu->signalSwitched();
> return;
> }
>
> list<unsigned>::iterator threads = (*activeThreads).begin();
>
> // Check if any of the threads are done squashing. Change the
> // status if they are done.
> while (threads != (*activeThreads).end()) {
> unsigned tid = *threads++;
>
> if (commitStatus[tid] == ROBSquashing) {
>
> if (rob->isDoneSquashing(tid)) {
> commitStatus[tid] = Running;
> --squashCounter;
> } else {
> DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
> "insts this cycle.\n", tid);
> }
> }
> }
>
> commit();
>
171,174c596,630
< // Writeback number of free ROB entries here.
< DPRINTF(Commit, "Commit: ROB has %d free entries.\n",
< rob->numFreeEntries());
< toIEW->commitInfo.freeROBEntries = rob->numFreeEntries();
---
> threads = (*activeThreads).begin();
>
> while (threads != (*activeThreads).end()) {
> unsigned tid = *threads++;
>
> if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
> // The ROB has more instructions it can commit. Its next status
> // will be active.
> _nextStatus = Active;
>
> DynInstPtr inst = rob->readHeadInst(tid);
>
> DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
> " ROB and ready to commit\n",
> tid, inst->seqNum, inst->readPC());
>
> } else if (!rob->isEmpty(tid)) {
> DynInstPtr inst = rob->readHeadInst(tid);
>
> DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
> "%#x is head of ROB and not ready\n",
> tid, inst->seqNum, inst->readPC());
> }
>
> DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
> tid, rob->countInsts(tid), rob->numFreeEntries(tid));
> }
>
>
> if (wroteToTimeBuffer) {
> DPRINTF(Activity, "Activity This Cycle.\n");
> cpu->activityThisCycle();
> }
>
> updateStatus();
179c635
< SimpleCommit<Impl>::commit()
---
> DefaultCommit<Impl>::commit()
180a637
>
185,190d641
< // Process interrupts if interrupts are enabled and not in PAL mode.
< // Take the PC from commit and write it to the IPR, then squash. The
< // interrupt completing will take care of restoring the PC from that value
< // in the IPR. Look at IPR[EXC_ADDR];
< // hwrei() is what resets the PC to the place where instruction execution
< // beings again.
192c643,646
< if (//checkInterrupts &&
---
> // Process interrupts if interrupts are enabled, not in PAL mode,
> // and no other traps or external squashes are currently pending.
> // @todo: Allow other threads to handle interrupts.
> if (cpu->checkInterrupts &&
194,199c648,654
< !cpu->inPalMode(readCommitPC())) {
< // Will need to squash all instructions currently in flight and have
< // the interrupt handler restart at the last non-committed inst.
< // Most of that can be handled through the trap() function. The
< // processInterrupts() function really just checks for interrupts
< // and then calls trap() if there is an interrupt present.
---
> !cpu->inPalMode(readPC()) &&
> !trapSquash[0] &&
> !xcSquash[0]) {
> // Tell fetch that there is an interrupt pending. This will
> // make fetch wait until it sees a non PAL-mode PC, at which
> // point it stops fetching instructions.
> toIEW->commitInfo[0].interruptPending = true;
201,202c656,681
< // CPU will handle implementation of the interrupt.
< cpu->processInterrupts();
---
> // Wait until the ROB is empty and all stores have drained in
> // order to enter the interrupt.
> if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
> // Not sure which thread should be the one to interrupt. For now
> // always do thread 0.
> assert(!thread[0]->inSyscall);
> thread[0]->inSyscall = true;
>
> // CPU will handle implementation of the interrupt.
> cpu->processInterrupts();
>
> // Now squash or record that I need to squash this cycle.
> commitStatus[0] = TrapPending;
>
> // Exit state update mode to avoid accidental updating.
> thread[0]->inSyscall = false;
>
> // Generate trap squash event.
> generateTrapEvent(0);
>
> toIEW->commitInfo[0].clearInterrupt = true;
>
> DPRINTF(Commit, "Interrupt detected.\n");
> } else {
> DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
> }
207c686
< // Check for squash signal, handle that first
---
> // Check for any possible squashes, handle them first
210,215c689
< // Want to mainly check if the IEW stage is telling the ROB to squash.
< // Should I also check if the commit stage is telling the ROB to squah?
< // This might be necessary to keep the same timing between the IQ and
< // the ROB...
< if (fromIEW->squash) {
< DPRINTF(Commit, "Commit: Squashing instructions in the ROB.\n");
---
> list<unsigned>::iterator threads = (*activeThreads).begin();
217c691,692
< _status = ROBSquashing;
---
> while (threads != (*activeThreads).end()) {
> unsigned tid = *threads++;
219c694,704
< InstSeqNum squashed_inst = fromIEW->squashedSeqNum;
---
> if (fromFetch->fetchFault && commitStatus[0] != TrapPending) {
> // Record the fault. Wait until it's empty in the ROB.
> // Then handle the trap. Ignore it if there's already a
> // trap pending as fetch will be redirected.
> fetchFault = fromFetch->fetchFault;
> fetchFaultTick = curTick + fetchTrapLatency;
> commitStatus[0] = FetchTrapPending;
> DPRINTF(Commit, "Fault from fetch recorded. Will trap if the "
> "ROB empties without squashing the fault.\n");
> fetchTrapWait = 0;
> }
221c706,714
< rob->squash(squashed_inst);
---
> // Fetch may tell commit to clear the trap if it's been squashed.
> if (fromFetch->clearFetchFault) {
> DPRINTF(Commit, "Received clear fetch fault signal\n");
> fetchTrapWait = 0;
> if (commitStatus[0] == FetchTrapPending) {
> DPRINTF(Commit, "Clearing fault from fetch\n");
> commitStatus[0] = Running;
> }
> }
223,224c716,723
< // Send back the sequence number of the squashed instruction.
< toIEW->commitInfo.doneSeqNum = squashed_inst;
---
> // Not sure which one takes priority. I think if we have
> // both, that's a bad sign.
> if (trapSquash[tid] == true) {
> assert(!xcSquash[tid]);
> squashFromTrap(tid);
> } else if (xcSquash[tid] == true) {
> squashFromXC(tid);
> }
226,227c725,730
< // Send back the squash signal to tell stages that they should squash.
< toIEW->commitInfo.squash = true;
---
> // Squashed sequence number must be older than youngest valid
> // instruction in the ROB. This prevents squashes from younger
> // instructions overriding squashes from older instructions.
> if (fromIEW->squash[tid] &&
> commitStatus[tid] != TrapPending &&
> fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
229,231c732,735
< // Send back the rob squashing signal so other stages know that the
< // ROB is in the process of squashing.
< toIEW->commitInfo.robSquashing = true;
---
> DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
> tid,
> fromIEW->mispredPC[tid],
> fromIEW->squashedSeqNum[tid]);
233c737,739
< toIEW->commitInfo.branchMispredict = fromIEW->branchMispredict;
---
> DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
> tid,
> fromIEW->nextPC[tid]);
235c741
< toIEW->commitInfo.branchTaken = fromIEW->branchTaken;
---
> commitStatus[tid] = ROBSquashing;
237c743
< toIEW->commitInfo.nextPC = fromIEW->nextPC;
---
> ++squashCounter;
239c745,747
< toIEW->commitInfo.mispredPC = fromIEW->mispredPC;
---
> // If we want to include the squashing instruction in the squash,
> // then use one older sequence number.
> InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
241,242c749,779
< if (toIEW->commitInfo.branchMispredict) {
< ++branchMispredicts;
---
> if (fromIEW->includeSquashInst[tid] == true)
> squashed_inst--;
>
> // All younger instructions will be squashed. Set the sequence
> // number as the youngest instruction in the ROB.
> youngestSeqNum[tid] = squashed_inst;
>
> rob->squash(squashed_inst, tid);
> changedROBNumEntries[tid] = true;
>
> toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
>
> toIEW->commitInfo[tid].squash = true;
>
> // Send back the rob squashing signal so other stages know that
> // the ROB is in the process of squashing.
> toIEW->commitInfo[tid].robSquashing = true;
>
> toIEW->commitInfo[tid].branchMispredict =
> fromIEW->branchMispredict[tid];
>
> toIEW->commitInfo[tid].branchTaken =
> fromIEW->branchTaken[tid];
>
> toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
>
> toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
>
> if (toIEW->commitInfo[tid].branchMispredict) {
> ++branchMispredicts;
> }
243a781
>
246c784,786
< if (_status != ROBSquashing) {
---
> setNextStatus();
>
> if (squashCounter != numThreads) {
254,261c794,810
< // If the ROB is empty, we can set this stage to idle. Use this
< // in the future when the Idle status will actually be utilized.
< #if 0
< if (rob->isEmpty()) {
< DPRINTF(Commit, "Commit: ROB is empty. Status changed to idle.\n");
< _status = Idle;
< // Schedule an event so that commit will actually wake up
< // once something gets put in the ROB.
---
> //Check for any activity
> threads = (*activeThreads).begin();
>
> while (threads != (*activeThreads).end()) {
> unsigned tid = *threads++;
>
> if (changedROBNumEntries[tid]) {
> toIEW->commitInfo[tid].usedROB = true;
> toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
>
> if (rob->isEmpty(tid)) {
> toIEW->commitInfo[tid].emptyROB = true;
> }
>
> wroteToTimeBuffer = true;
> changedROBNumEntries[tid] = false;
> }
263d811
< #endif
266,268d813
< // Loop that goes through as many instructions in the ROB as possible and
< // tries to commit them. The actual work for committing is done by the
< // commitHead() function.
271c816
< SimpleCommit<Impl>::commitInsts()
---
> DefaultCommit<Impl>::commitInsts()
275,278c820,824
< // Note that commit will be handled prior to the ROB so that the ROB
< // only tries to commit instructions it has in this current cycle, and
< // not instructions it is writing in during this cycle.
< // Can't commit and squash things at the same time...
---
> // Note that commit will be handled prior to putting new
> // instructions in the ROB so that the ROB only tries to commit
> // instructions it has in this current cycle, and not instructions
> // it is writing in during this cycle. Can't commit and squash
> // things at the same time...
281,282c827
< if (rob->isEmpty())
< return;
---
> DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
284,285d828
< DynInstPtr head_inst = rob->readHeadInst();
<
287a831,832
> DynInstPtr head_inst;
>
290,294c835,836
< while (!rob->isEmpty() &&
< head_inst->readyToCommit() &&
< num_committed < commitWidth)
< {
< DPRINTF(Commit, "Commit: Trying to commit head instruction.\n");
---
> while (num_committed < commitWidth) {
> int commit_thread = getCommittingThread();
296,298c838,851
< // If the head instruction is squashed, it is ready to retire at any
< // time. However, we need to avoid updating any other state
< // incorrectly if it's already been squashed.
---
> if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
> break;
>
> head_inst = rob->readHeadInst(commit_thread);
>
> int tid = head_inst->threadNumber;
>
> assert(tid == commit_thread);
>
> DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
> head_inst->seqNum, tid);
>
> // If the head instruction is squashed, it is ready to retire
> // (be removed from the ROB) at any time.
301c854
< DPRINTF(Commit, "Commit: Retiring squashed instruction from "
---
> DPRINTF(Commit, "Retiring squashed instruction from "
304,306c857
< // Tell ROB to retire head instruction. This retires the head
< // inst in the ROB without affecting any other stages.
< rob->retireHead();
---
> rob->retireHead(commit_thread);
309a861,862
> // Record that the number of ROB entries has changed.
> changedROBNumEntries[tid] = true;
310a864,866
> PC[tid] = head_inst->readPC();
> nextPC[tid] = head_inst->readNextPC();
>
316c872
< cpu->funcExeInst++;
---
> thread[tid]->funcExeInst++;
321d876
< // Update what instruction we are looking at if the commit worked.
325,329c880
< // Send back which instruction has been committed.
< // @todo: Update this later when a wider pipeline is used.
< // Hmm, can't really give a pointer here...perhaps the
< // sequence number instead (copy).
< toIEW->commitInfo.doneSeqNum = head_inst->seqNum;
---
> changedROBNumEntries[tid] = true;
330a882,884
> // Set the doneSeqNum to the youngest committed instruction.
> toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
>
333,334c887,890
< if (!head_inst->isNop()) {
< cpu->instDone();
---
> // To match the old model, don't count nops and instruction
> // prefetches towards the total commit count.
> if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
> cpu->instDone(tid);
335a892,913
>
> PC[tid] = nextPC[tid];
> nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
> #if FULL_SYSTEM
> int count = 0;
> Addr oldpc;
> do {
> // Debug statement. Checks to make sure we're not
> // currently updating state while handling PC events.
> if (count == 0)
> assert(!thread[tid]->inSyscall &&
> !thread[tid]->trapPending);
> oldpc = PC[tid];
> cpu->system->pcEventQueue.service(
> thread[tid]->getXCProxy());
> count++;
> } while (oldpc != PC[tid]);
> if (count > 1) {
> DPRINTF(Commit, "PC skip function event, stopping commit\n");
> break;
> }
> #endif
336a915,917
> DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
> "[tid:%i] [sn:%i].\n",
> head_inst->readPC(), tid ,head_inst->seqNum);
340,342d920
<
< // Update the pointer to read the next instruction in the ROB.
< head_inst = rob->readHeadInst();
346c924,928
< n_committed_dist.sample(num_committed);
---
> numCommittedDist.sample(num_committed);
>
> if (num_committed == commitWidth) {
> commitEligible[0]++;
> }
351c933
< SimpleCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
---
> DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
353d934
< // Make sure instruction is valid
356,357c937,940
< // If the instruction is not executed yet, then it is a non-speculative
< // or store inst. Signal backwards that it should be executed.
---
> int tid = head_inst->threadNumber;
>
> // If the instruction is not executed yet, then it will need extra
> // handling. Signal backwards that it should be executed.
361c944
< cpu->funcExeInst--;
---
> thread[tid]->funcExeInst--;
363,366c946
< if (head_inst->isNonSpeculative()) {
< DPRINTF(Commit, "Commit: Encountered a store or non-speculative "
< "instruction at the head of the ROB, PC %#x.\n",
< head_inst->readPC());
---
> head_inst->reachedCommit = true;
368c948,950
< toIEW->commitInfo.nonSpecSeqNum = head_inst->seqNum;
---
> if (head_inst->isNonSpeculative() ||
> head_inst->isMemBarrier() ||
> head_inst->isWriteBarrier()) {
369a952,973
> DPRINTF(Commit, "Encountered a barrier or non-speculative "
> "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
> head_inst->seqNum, head_inst->readPC());
>
> #if !FULL_SYSTEM
> // Hack to make sure syscalls/memory barriers/quiesces
> // aren't executed until all stores write back their data.
> // This direct communication shouldn't be used for
> // anything other than this.
> if (inst_num > 0 || iewStage->hasStoresToWB())
> #else
> if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
> head_inst->isQuiesce()) &&
> iewStage->hasStoresToWB())
> #endif
> {
> DPRINTF(Commit, "Waiting for all stores to writeback.\n");
> return false;
> }
>
> toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
>
376a981,993
> } else if (head_inst->isLoad()) {
> DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
> head_inst->seqNum, head_inst->readPC());
>
> // Send back the non-speculative instruction's sequence
> // number. Tell the lsq to re-execute the load.
> toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
> toIEW->commitInfo[tid].uncached = true;
> toIEW->commitInfo[tid].uncachedLoad = head_inst;
>
> head_inst->clearCanCommit();
>
> return false;
378c995
< panic("Commit: Trying to commit un-executed instruction "
---
> panic("Trying to commit un-executed instruction "
383,394c1000,1002
< // Now check if it's one of the special trap or barrier or
< // serializing instructions.
< if (head_inst->isThreadSync() ||
< head_inst->isSerializing() ||
< head_inst->isMemBarrier() ||
< head_inst->isWriteBarrier() )
< {
< // Not handled for now. Mem barriers and write barriers are safe
< // to simply let commit as memory accesses only happen once they
< // reach the head of commit. Not sure about the other two.
< panic("Serializing or barrier instructions"
< " are not handled yet.\n");
---
> if (head_inst->isThreadSync()) {
> // Not handled for now.
> panic("Thread sync instructions are not handled yet.\n");
396a1005,1015
> // Stores mark themselves as completed.
> if (!head_inst->isStore()) {
> head_inst->setCompleted();
> }
>
> // Use checker prior to updating anything due to traps or PC
> // based events.
> if (cpu->checker) {
> cpu->checker->tick(head_inst);
> }
>
401c1020
< if (!head_inst->isNop()) {
---
> head_inst->setCompleted();
403,407c1022,1027
< cpu->trap(inst_fault);
< #else // !FULL_SYSTEM
< panic("fault (%d) detected @ PC %08p", inst_fault,
< head_inst->PC);
< #endif // FULL_SYSTEM
---
> DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
> head_inst->seqNum, head_inst->readPC());
>
> if (iewStage->hasStoresToWB() || inst_num > 0) {
> DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
> return false;
409d1028
< }
411,417c1030,1032
< // Check if we're really ready to commit. If not then return false.
< // I'm pretty sure all instructions should be able to commit if they've
< // reached this far. For now leave this in as a check.
< if (!rob->isHeadReady()) {
< panic("Commit: Unable to commit head instruction!\n");
< return false;
< }
---
> if (cpu->checker && head_inst->isStore()) {
> cpu->checker->tick(head_inst);
> }
419,421c1034
< // If it's a branch, then send back branch prediction update info
< // to the fetch stage.
< // This should be handled in the iew stage if a mispredict happens...
---
> assert(!thread[tid]->inSyscall);
423c1036,1038
< if (head_inst->isControl()) {
---
> // Mark that we're in state update mode so that the trap's
> // execution doesn't generate extra squashes.
> thread[tid]->inSyscall = true;
425,432c1040,1044
< #if 0
< toIEW->nextPC = head_inst->readPC();
< //Maybe switch over to BTB incorrect.
< toIEW->btbMissed = head_inst->btbMiss();
< toIEW->target = head_inst->nextPC;
< //Maybe also include global history information.
< //This simple version will have no branch prediction however.
< #endif
---
> // DTB will sometimes need the machine instruction for when
> // faults happen. So we will set it here, prior to the DTB
> // possibly needing it for its fault.
> thread[tid]->setInst(
> static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
434c1046,1066
< ++commitCommittedBranches;
---
> // Execute the trap. Although it's slightly unrealistic in
> // terms of timing (as it doesn't wait for the full timing of
> // the trap event to complete before updating state), it's
> // needed to update the state as soon as possible. This
> // prevents external agents from changing any specific state
> // that the trap need.
> cpu->trap(inst_fault, tid);
>
> // Exit state update mode to avoid accidental updating.
> thread[tid]->inSyscall = false;
>
> commitStatus[tid] = TrapPending;
>
> // Generate trap squash event.
> generateTrapEvent(tid);
>
> return false;
> #else // !FULL_SYSTEM
> panic("fault (%d) detected @ PC %08p", inst_fault,
> head_inst->PC);
> #endif // FULL_SYSTEM
437,438c1069,1070
< // Now that the instruction is going to be committed, finalize its
< // trace data.
---
> updateComInstStats(head_inst);
>
439a1072,1073
> head_inst->traceData->setFetchSeq(head_inst->seqNum);
> head_inst->traceData->setCPSeq(thread[tid]->numInst);
440a1075
> head_inst->traceData = NULL;
443,444c1078,1082
< //Finally clear the head ROB entry.
< rob->retireHead();
---
> // Update the commit rename map
> for (int i = 0; i < head_inst->numDestRegs(); i++) {
> renameMap[tid]->setEntry(head_inst->destRegIdx(i),
> head_inst->renamedDestRegIdx(i));
> }
445a1084,1086
> // Finally clear the head ROB entry.
> rob->retireHead(tid);
>
452c1093
< SimpleCommit<Impl>::getInsts()
---
> DefaultCommit<Impl>::getInsts()
454,460c1095
< //////////////////////////////////////
< // Handle ROB functions
< //////////////////////////////////////
<
< // Read any issued instructions and place them into the ROB. Do this
< // prior to squashing to avoid having instructions in the ROB that
< // don't get squashed properly.
---
> // Read any renamed instructions and place them into the ROB.
463,465c1098
< for (int inst_num = 0;
< inst_num < insts_to_process;
< ++inst_num)
---
> for (int inst_num = 0; inst_num < insts_to_process; ++inst_num)
467,470c1100,1114
< if (!fromRename->insts[inst_num]->isSquashed()) {
< DPRINTF(Commit, "Commit: Inserting PC %#x into ROB.\n",
< fromRename->insts[inst_num]->readPC());
< rob->insertInst(fromRename->insts[inst_num]);
---
> DynInstPtr inst = fromRename->insts[inst_num];
> int tid = inst->threadNumber;
>
> if (!inst->isSquashed() &&
> commitStatus[tid] != ROBSquashing) {
> changedROBNumEntries[tid] = true;
>
> DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
> inst->readPC(), inst->seqNum, tid);
>
> rob->insertInst(inst);
>
> assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
>
> youngestSeqNum[tid] = inst->seqNum;
472c1116
< DPRINTF(Commit, "Commit: Instruction %i PC %#x was "
---
> DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
474,475c1118
< fromRename->insts[inst_num]->seqNum,
< fromRename->insts[inst_num]->readPC());
---
> inst->readPC(), inst->seqNum, tid);
482c1125
< SimpleCommit<Impl>::markCompletedInsts()
---
> DefaultCommit<Impl>::markCompletedInsts()
490,492c1133,1138
< DPRINTF(Commit, "Commit: Marking PC %#x, SN %i ready within ROB.\n",
< fromIEW->insts[inst_num]->readPC(),
< fromIEW->insts[inst_num]->seqNum);
---
> if (!fromIEW->insts[inst_num]->isSquashed()) {
> DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
> "within ROB.\n",
> fromIEW->insts[inst_num]->threadNumber,
> fromIEW->insts[inst_num]->readPC(),
> fromIEW->insts[inst_num]->seqNum);
494,495c1140,1142
< // Mark the instruction as ready to commit.
< fromIEW->insts[inst_num]->setCanCommit();
---
> // Mark the instruction as ready to commit.
> fromIEW->insts[inst_num]->setCanCommit();
> }
500,501c1147,1148
< uint64_t
< SimpleCommit<Impl>::readCommitPC()
---
> bool
> DefaultCommit<Impl>::robDoneSquashing()
503c1150,1159
< return rob->readHeadPC();
---
> list<unsigned>::iterator threads = (*activeThreads).begin();
>
> while (threads != (*activeThreads).end()) {
> unsigned tid = *threads++;
>
> if (!rob->isDoneSquashing(tid))
> return false;
> }
>
> return true;
504a1161,1306
>
> template <class Impl>
> void
> DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
> {
> unsigned thread = inst->threadNumber;
>
> //
> // Pick off the software prefetches
> //
> #ifdef TARGET_ALPHA
> if (inst->isDataPrefetch()) {
> statComSwp[thread]++;
> } else {
> statComInst[thread]++;
> }
> #else
> statComInst[thread]++;
> #endif
>
> //
> // Control Instructions
> //
> if (inst->isControl())
> statComBranches[thread]++;
>
> //
> // Memory references
> //
> if (inst->isMemRef()) {
> statComRefs[thread]++;
>
> if (inst->isLoad()) {
> statComLoads[thread]++;
> }
> }
>
> if (inst->isMemBarrier()) {
> statComMembars[thread]++;
> }
> }
>
> ////////////////////////////////////////
> // //
> // SMT COMMIT POLICY MAINTAINED HERE //
> // //
> ////////////////////////////////////////
> template <class Impl>
> int
> DefaultCommit<Impl>::getCommittingThread()
> {
> if (numThreads > 1) {
> switch (commitPolicy) {
>
> case Aggressive:
> //If Policy is Aggressive, commit will call
> //this function multiple times per
> //cycle
> return oldestReady();
>
> case RoundRobin:
> return roundRobin();
>
> case OldestReady:
> return oldestReady();
>
> default:
> return -1;
> }
> } else {
> int tid = (*activeThreads).front();
>
> if (commitStatus[tid] == Running ||
> commitStatus[tid] == Idle ||
> commitStatus[tid] == FetchTrapPending) {
> return tid;
> } else {
> return -1;
> }
> }
> }
>
> template<class Impl>
> int
> DefaultCommit<Impl>::roundRobin()
> {
> list<unsigned>::iterator pri_iter = priority_list.begin();
> list<unsigned>::iterator end = priority_list.end();
>
> while (pri_iter != end) {
> unsigned tid = *pri_iter;
>
> if (commitStatus[tid] == Running ||
> commitStatus[tid] == Idle) {
>
> if (rob->isHeadReady(tid)) {
> priority_list.erase(pri_iter);
> priority_list.push_back(tid);
>
> return tid;
> }
> }
>
> pri_iter++;
> }
>
> return -1;
> }
>
> template<class Impl>
> int
> DefaultCommit<Impl>::oldestReady()
> {
> unsigned oldest = 0;
> bool first = true;
>
> list<unsigned>::iterator threads = (*activeThreads).begin();
>
> while (threads != (*activeThreads).end()) {
> unsigned tid = *threads++;
>
> if (!rob->isEmpty(tid) &&
> (commitStatus[tid] == Running ||
> commitStatus[tid] == Idle ||
> commitStatus[tid] == FetchTrapPending)) {
>
> if (rob->isHeadReady(tid)) {
>
> DynInstPtr head_inst = rob->readHeadInst(tid);
>
> if (first) {
> oldest = tid;
> first = false;
> } else if (head_inst->seqNum < oldest) {
> oldest = tid;
> }
> }
> }
> }
>
> if (!first) {
> return oldest;
> } else {
> return -1;
> }
> }