1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#include <algorithm>
45#include <string>
46
47#include "arch/utility.hh"
48#include "base/loader/symtab.hh"
49#include "base/cp_annotate.hh"
50#include "config/the_isa.hh"
| 1/*
2 * Copyright (c) 2010-2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#include <algorithm>
45#include <string>
46
47#include "arch/utility.hh"
48#include "base/loader/symtab.hh"
49#include "base/cp_annotate.hh"
50#include "config/the_isa.hh"
|
51#include "config/use_checker.hh"
| 51#include "cpu/checker/cpu.hh"
|
52#include "cpu/o3/commit.hh"
53#include "cpu/o3/thread_state.hh"
54#include "cpu/base.hh"
55#include "cpu/exetrace.hh"
56#include "cpu/timebuf.hh"
57#include "debug/Activity.hh"
58#include "debug/Commit.hh"
59#include "debug/CommitRate.hh"
60#include "debug/ExecFaulting.hh"
61#include "debug/O3PipeView.hh"
62#include "params/DerivO3CPU.hh"
63#include "sim/faults.hh"
64#include "sim/full_system.hh"
65
| 52#include "cpu/o3/commit.hh"
53#include "cpu/o3/thread_state.hh"
54#include "cpu/base.hh"
55#include "cpu/exetrace.hh"
56#include "cpu/timebuf.hh"
57#include "debug/Activity.hh"
58#include "debug/Commit.hh"
59#include "debug/CommitRate.hh"
60#include "debug/ExecFaulting.hh"
61#include "debug/O3PipeView.hh"
62#include "params/DerivO3CPU.hh"
63#include "sim/faults.hh"
64#include "sim/full_system.hh"
65
|
66#if USE_CHECKER
67#include "cpu/checker/cpu.hh"
68#endif
69
| |
70using namespace std;
71
72template <class Impl>
73DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
74 ThreadID _tid)
75 : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid)
76{
77}
78
79template <class Impl>
80void
81DefaultCommit<Impl>::TrapEvent::process()
82{
83 // This will get reset by commit if it was switched out at the
84 // time of this event processing.
85 commit->trapSquash[tid] = true;
86}
87
88template <class Impl>
89const char *
90DefaultCommit<Impl>::TrapEvent::description() const
91{
92 return "Trap";
93}
94
95template <class Impl>
96DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
97 : cpu(_cpu),
98 squashCounter(0),
99 iewToCommitDelay(params->iewToCommitDelay),
100 commitToIEWDelay(params->commitToIEWDelay),
101 renameToROBDelay(params->renameToROBDelay),
102 fetchToCommitDelay(params->commitToFetchDelay),
103 renameWidth(params->renameWidth),
104 commitWidth(params->commitWidth),
105 numThreads(params->numThreads),
106 drainPending(false),
107 switchedOut(false),
108 trapLatency(params->trapLatency),
109 canHandleInterrupts(true)
110{
111 _status = Active;
112 _nextStatus = Inactive;
113 std::string policy = params->smtCommitPolicy;
114
115 //Convert string to lowercase
116 std::transform(policy.begin(), policy.end(), policy.begin(),
117 (int(*)(int)) tolower);
118
119 //Assign commit policy
120 if (policy == "aggressive"){
121 commitPolicy = Aggressive;
122
123 DPRINTF(Commit,"Commit Policy set to Aggressive.\n");
124 } else if (policy == "roundrobin"){
125 commitPolicy = RoundRobin;
126
127 //Set-Up Priority List
128 for (ThreadID tid = 0; tid < numThreads; tid++) {
129 priority_list.push_back(tid);
130 }
131
132 DPRINTF(Commit,"Commit Policy set to Round Robin.\n");
133 } else if (policy == "oldestready"){
134 commitPolicy = OldestReady;
135
136 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
137 } else {
138 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
139 "RoundRobin,OldestReady}");
140 }
141
142 for (ThreadID tid = 0; tid < numThreads; tid++) {
143 commitStatus[tid] = Idle;
144 changedROBNumEntries[tid] = false;
145 checkEmptyROB[tid] = false;
146 trapInFlight[tid] = false;
147 committedStores[tid] = false;
148 trapSquash[tid] = false;
149 tcSquash[tid] = false;
150 pc[tid].set(0);
151 lastCommitedSeqNum[tid] = 0;
152 }
153 interrupt = NoFault;
154}
155
156template <class Impl>
157std::string
158DefaultCommit<Impl>::name() const
159{
160 return cpu->name() + ".commit";
161}
162
163template <class Impl>
164void
165DefaultCommit<Impl>::regStats()
166{
167 using namespace Stats;
168 commitCommittedInsts
169 .name(name() + ".commitCommittedInsts")
170 .desc("The number of committed instructions")
171 .prereq(commitCommittedInsts);
172 commitCommittedOps
173 .name(name() + ".commitCommittedOps")
174 .desc("The number of committed instructions")
175 .prereq(commitCommittedInsts);
176 commitSquashedInsts
177 .name(name() + ".commitSquashedInsts")
178 .desc("The number of squashed insts skipped by commit")
179 .prereq(commitSquashedInsts);
180 commitSquashEvents
181 .name(name() + ".commitSquashEvents")
182 .desc("The number of times commit is told to squash")
183 .prereq(commitSquashEvents);
184 commitNonSpecStalls
185 .name(name() + ".commitNonSpecStalls")
186 .desc("The number of times commit has been forced to stall to "
187 "communicate backwards")
188 .prereq(commitNonSpecStalls);
189 branchMispredicts
190 .name(name() + ".branchMispredicts")
191 .desc("The number of times a branch was mispredicted")
192 .prereq(branchMispredicts);
193 numCommittedDist
194 .init(0,commitWidth,1)
195 .name(name() + ".committed_per_cycle")
196 .desc("Number of insts commited each cycle")
197 .flags(Stats::pdf)
198 ;
199
200 instsCommitted
201 .init(cpu->numThreads)
202 .name(name() + ".committedInsts")
203 .desc("Number of instructions committed")
204 .flags(total)
205 ;
206
207 opsCommitted
208 .init(cpu->numThreads)
209 .name(name() + ".committedOps")
210 .desc("Number of ops (including micro ops) committed")
211 .flags(total)
212 ;
213
214 statComSwp
215 .init(cpu->numThreads)
216 .name(name() + ".swp_count")
217 .desc("Number of s/w prefetches committed")
218 .flags(total)
219 ;
220
221 statComRefs
222 .init(cpu->numThreads)
223 .name(name() + ".refs")
224 .desc("Number of memory references committed")
225 .flags(total)
226 ;
227
228 statComLoads
229 .init(cpu->numThreads)
230 .name(name() + ".loads")
231 .desc("Number of loads committed")
232 .flags(total)
233 ;
234
235 statComMembars
236 .init(cpu->numThreads)
237 .name(name() + ".membars")
238 .desc("Number of memory barriers committed")
239 .flags(total)
240 ;
241
242 statComBranches
243 .init(cpu->numThreads)
244 .name(name() + ".branches")
245 .desc("Number of branches committed")
246 .flags(total)
247 ;
248
249 statComFloating
250 .init(cpu->numThreads)
251 .name(name() + ".fp_insts")
252 .desc("Number of committed floating point instructions.")
253 .flags(total)
254 ;
255
256 statComInteger
257 .init(cpu->numThreads)
258 .name(name()+".int_insts")
259 .desc("Number of committed integer instructions.")
260 .flags(total)
261 ;
262
263 statComFunctionCalls
264 .init(cpu->numThreads)
265 .name(name()+".function_calls")
266 .desc("Number of function calls committed.")
267 .flags(total)
268 ;
269
270 commitEligible
271 .init(cpu->numThreads)
272 .name(name() + ".bw_limited")
273 .desc("number of insts not committed due to BW limits")
274 .flags(total)
275 ;
276
277 commitEligibleSamples
278 .name(name() + ".bw_lim_events")
279 .desc("number cycles where commit BW limit reached")
280 ;
281}
282
283template <class Impl>
284void
285DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
286{
287 thread = threads;
288}
289
290template <class Impl>
291void
292DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
293{
294 timeBuffer = tb_ptr;
295
296 // Setup wire to send information back to IEW.
297 toIEW = timeBuffer->getWire(0);
298
299 // Setup wire to read data from IEW (for the ROB).
300 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
301}
302
303template <class Impl>
304void
305DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
306{
307 fetchQueue = fq_ptr;
308
309 // Setup wire to get instructions from rename (for the ROB).
310 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
311}
312
313template <class Impl>
314void
315DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
316{
317 renameQueue = rq_ptr;
318
319 // Setup wire to get instructions from rename (for the ROB).
320 fromRename = renameQueue->getWire(-renameToROBDelay);
321}
322
323template <class Impl>
324void
325DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
326{
327 iewQueue = iq_ptr;
328
329 // Setup wire to get instructions from IEW.
330 fromIEW = iewQueue->getWire(-iewToCommitDelay);
331}
332
333template <class Impl>
334void
335DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
336{
337 iewStage = iew_stage;
338}
339
340template<class Impl>
341void
342DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
343{
344 activeThreads = at_ptr;
345}
346
347template <class Impl>
348void
349DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
350{
351 for (ThreadID tid = 0; tid < numThreads; tid++)
352 renameMap[tid] = &rm_ptr[tid];
353}
354
355template <class Impl>
356void
357DefaultCommit<Impl>::setROB(ROB *rob_ptr)
358{
359 rob = rob_ptr;
360}
361
362template <class Impl>
363void
364DefaultCommit<Impl>::initStage()
365{
366 rob->setActiveThreads(activeThreads);
367 rob->resetEntries();
368
369 // Broadcast the number of free entries.
370 for (ThreadID tid = 0; tid < numThreads; tid++) {
371 toIEW->commitInfo[tid].usedROB = true;
372 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
373 toIEW->commitInfo[tid].emptyROB = true;
374 }
375
376 // Commit must broadcast the number of free entries it has at the
377 // start of the simulation, so it starts as active.
378 cpu->activateStage(O3CPU::CommitIdx);
379
380 cpu->activityThisCycle();
381 trapLatency = cpu->ticks(trapLatency);
382}
383
384template <class Impl>
385bool
386DefaultCommit<Impl>::drain()
387{
388 drainPending = true;
389
390 return false;
391}
392
393template <class Impl>
394void
395DefaultCommit<Impl>::switchOut()
396{
397 switchedOut = true;
398 drainPending = false;
399 rob->switchOut();
400}
401
402template <class Impl>
403void
404DefaultCommit<Impl>::resume()
405{
406 drainPending = false;
407}
408
409template <class Impl>
410void
411DefaultCommit<Impl>::takeOverFrom()
412{
413 switchedOut = false;
414 _status = Active;
415 _nextStatus = Inactive;
416 for (ThreadID tid = 0; tid < numThreads; tid++) {
417 commitStatus[tid] = Idle;
418 changedROBNumEntries[tid] = false;
419 trapSquash[tid] = false;
420 tcSquash[tid] = false;
421 }
422 squashCounter = 0;
423 rob->takeOverFrom();
424}
425
426template <class Impl>
427void
428DefaultCommit<Impl>::updateStatus()
429{
430 // reset ROB changed variable
431 list<ThreadID>::iterator threads = activeThreads->begin();
432 list<ThreadID>::iterator end = activeThreads->end();
433
434 while (threads != end) {
435 ThreadID tid = *threads++;
436
437 changedROBNumEntries[tid] = false;
438
439 // Also check if any of the threads has a trap pending
440 if (commitStatus[tid] == TrapPending ||
441 commitStatus[tid] == FetchTrapPending) {
442 _nextStatus = Active;
443 }
444 }
445
446 if (_nextStatus == Inactive && _status == Active) {
447 DPRINTF(Activity, "Deactivating stage.\n");
448 cpu->deactivateStage(O3CPU::CommitIdx);
449 } else if (_nextStatus == Active && _status == Inactive) {
450 DPRINTF(Activity, "Activating stage.\n");
451 cpu->activateStage(O3CPU::CommitIdx);
452 }
453
454 _status = _nextStatus;
455}
456
457template <class Impl>
458void
459DefaultCommit<Impl>::setNextStatus()
460{
461 int squashes = 0;
462
463 list<ThreadID>::iterator threads = activeThreads->begin();
464 list<ThreadID>::iterator end = activeThreads->end();
465
466 while (threads != end) {
467 ThreadID tid = *threads++;
468
469 if (commitStatus[tid] == ROBSquashing) {
470 squashes++;
471 }
472 }
473
474 squashCounter = squashes;
475
476 // If commit is currently squashing, then it will have activity for the
477 // next cycle. Set its next status as active.
478 if (squashCounter) {
479 _nextStatus = Active;
480 }
481}
482
483template <class Impl>
484bool
485DefaultCommit<Impl>::changedROBEntries()
486{
487 list<ThreadID>::iterator threads = activeThreads->begin();
488 list<ThreadID>::iterator end = activeThreads->end();
489
490 while (threads != end) {
491 ThreadID tid = *threads++;
492
493 if (changedROBNumEntries[tid]) {
494 return true;
495 }
496 }
497
498 return false;
499}
500
501template <class Impl>
502size_t
503DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
504{
505 return rob->numFreeEntries(tid);
506}
507
508template <class Impl>
509void
510DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
511{
512 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
513
514 TrapEvent *trap = new TrapEvent(this, tid);
515
516 cpu->schedule(trap, curTick() + trapLatency);
517 trapInFlight[tid] = true;
518 thread[tid]->trapPending = true;
519}
520
521template <class Impl>
522void
523DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
524{
525 assert(!trapInFlight[tid]);
526 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
527
528 tcSquash[tid] = true;
529}
530
531template <class Impl>
532void
533DefaultCommit<Impl>::squashAll(ThreadID tid)
534{
535 // If we want to include the squashing instruction in the squash,
536 // then use one older sequence number.
537 // Hopefully this doesn't mess things up. Basically I want to squash
538 // all instructions of this thread.
539 InstSeqNum squashed_inst = rob->isEmpty() ?
540 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
541
542 // All younger instructions will be squashed. Set the sequence
543 // number as the youngest instruction in the ROB (0 in this case.
544 // Hopefully nothing breaks.)
545 youngestSeqNum[tid] = lastCommitedSeqNum[tid];
546
547 rob->squash(squashed_inst, tid);
548 changedROBNumEntries[tid] = true;
549
550 // Send back the sequence number of the squashed instruction.
551 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
552
553 // Send back the squash signal to tell stages that they should
554 // squash.
555 toIEW->commitInfo[tid].squash = true;
556
557 // Send back the rob squashing signal so other stages know that
558 // the ROB is in the process of squashing.
559 toIEW->commitInfo[tid].robSquashing = true;
560
561 toIEW->commitInfo[tid].mispredictInst = NULL;
562 toIEW->commitInfo[tid].squashInst = NULL;
563
564 toIEW->commitInfo[tid].pc = pc[tid];
565}
566
567template <class Impl>
568void
569DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
570{
571 squashAll(tid);
572
573 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
574
575 thread[tid]->trapPending = false;
576 thread[tid]->inSyscall = false;
577 trapInFlight[tid] = false;
578
579 trapSquash[tid] = false;
580
581 commitStatus[tid] = ROBSquashing;
582 cpu->activityThisCycle();
583}
584
585template <class Impl>
586void
587DefaultCommit<Impl>::squashFromTC(ThreadID tid)
588{
589 squashAll(tid);
590
591 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
592
593 thread[tid]->inSyscall = false;
594 assert(!thread[tid]->trapPending);
595
596 commitStatus[tid] = ROBSquashing;
597 cpu->activityThisCycle();
598
599 tcSquash[tid] = false;
600}
601
602template <class Impl>
603void
604DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst,
605 uint64_t squash_after_seq_num)
606{
607 youngestSeqNum[tid] = squash_after_seq_num;
608
609 rob->squash(squash_after_seq_num, tid);
610 changedROBNumEntries[tid] = true;
611
612 // Send back the sequence number of the squashed instruction.
613 toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num;
614
615 toIEW->commitInfo[tid].squashInst = head_inst;
616 // Send back the squash signal to tell stages that they should squash.
617 toIEW->commitInfo[tid].squash = true;
618
619 // Send back the rob squashing signal so other stages know that
620 // the ROB is in the process of squashing.
621 toIEW->commitInfo[tid].robSquashing = true;
622
623 toIEW->commitInfo[tid].mispredictInst = NULL;
624
625 toIEW->commitInfo[tid].pc = pc[tid];
626 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
627 tid, squash_after_seq_num);
628 commitStatus[tid] = ROBSquashing;
629}
630
631template <class Impl>
632void
633DefaultCommit<Impl>::tick()
634{
635 wroteToTimeBuffer = false;
636 _nextStatus = Inactive;
637
638 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
639 cpu->signalDrained();
640 drainPending = false;
641 return;
642 }
643
644 if (activeThreads->empty())
645 return;
646
647 list<ThreadID>::iterator threads = activeThreads->begin();
648 list<ThreadID>::iterator end = activeThreads->end();
649
650 // Check if any of the threads are done squashing. Change the
651 // status if they are done.
652 while (threads != end) {
653 ThreadID tid = *threads++;
654
655 // Clear the bit saying if the thread has committed stores
656 // this cycle.
657 committedStores[tid] = false;
658
659 if (commitStatus[tid] == ROBSquashing) {
660
661 if (rob->isDoneSquashing(tid)) {
662 commitStatus[tid] = Running;
663 } else {
664 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
665 " insts this cycle.\n", tid);
666 rob->doSquash(tid);
667 toIEW->commitInfo[tid].robSquashing = true;
668 wroteToTimeBuffer = true;
669 }
670 }
671 }
672
673 commit();
674
675 markCompletedInsts();
676
677 threads = activeThreads->begin();
678
679 while (threads != end) {
680 ThreadID tid = *threads++;
681
682 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
683 // The ROB has more instructions it can commit. Its next status
684 // will be active.
685 _nextStatus = Active;
686
687 DynInstPtr inst = rob->readHeadInst(tid);
688
689 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
690 " ROB and ready to commit\n",
691 tid, inst->seqNum, inst->pcState());
692
693 } else if (!rob->isEmpty(tid)) {
694 DynInstPtr inst = rob->readHeadInst(tid);
695
696 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
697 "%s is head of ROB and not ready\n",
698 tid, inst->seqNum, inst->pcState());
699 }
700
701 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
702 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
703 }
704
705
706 if (wroteToTimeBuffer) {
707 DPRINTF(Activity, "Activity This Cycle.\n");
708 cpu->activityThisCycle();
709 }
710
711 updateStatus();
712}
713
714template <class Impl>
715void
716DefaultCommit<Impl>::handleInterrupt()
717{
718 // Verify that we still have an interrupt to handle
719 if (!cpu->checkInterrupts(cpu->tcBase(0))) {
720 DPRINTF(Commit, "Pending interrupt is cleared by master before "
721 "it got handled. Restart fetching from the orig path.\n");
722 toIEW->commitInfo[0].clearInterrupt = true;
723 interrupt = NoFault;
724 return;
725 }
726
727 // Wait until all in flight instructions are finished before enterring
728 // the interrupt.
729 if (canHandleInterrupts && cpu->instList.empty()) {
730 // Squash or record that I need to squash this cycle if
731 // an interrupt needed to be handled.
732 DPRINTF(Commit, "Interrupt detected.\n");
733
734 // Clear the interrupt now that it's going to be handled
735 toIEW->commitInfo[0].clearInterrupt = true;
736
737 assert(!thread[0]->inSyscall);
738 thread[0]->inSyscall = true;
739
| 66using namespace std;
67
68template <class Impl>
69DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
70 ThreadID _tid)
71 : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid)
72{
73}
74
75template <class Impl>
76void
77DefaultCommit<Impl>::TrapEvent::process()
78{
79 // This will get reset by commit if it was switched out at the
80 // time of this event processing.
81 commit->trapSquash[tid] = true;
82}
83
84template <class Impl>
85const char *
86DefaultCommit<Impl>::TrapEvent::description() const
87{
88 return "Trap";
89}
90
91template <class Impl>
92DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
93 : cpu(_cpu),
94 squashCounter(0),
95 iewToCommitDelay(params->iewToCommitDelay),
96 commitToIEWDelay(params->commitToIEWDelay),
97 renameToROBDelay(params->renameToROBDelay),
98 fetchToCommitDelay(params->commitToFetchDelay),
99 renameWidth(params->renameWidth),
100 commitWidth(params->commitWidth),
101 numThreads(params->numThreads),
102 drainPending(false),
103 switchedOut(false),
104 trapLatency(params->trapLatency),
105 canHandleInterrupts(true)
106{
107 _status = Active;
108 _nextStatus = Inactive;
109 std::string policy = params->smtCommitPolicy;
110
111 //Convert string to lowercase
112 std::transform(policy.begin(), policy.end(), policy.begin(),
113 (int(*)(int)) tolower);
114
115 //Assign commit policy
116 if (policy == "aggressive"){
117 commitPolicy = Aggressive;
118
119 DPRINTF(Commit,"Commit Policy set to Aggressive.\n");
120 } else if (policy == "roundrobin"){
121 commitPolicy = RoundRobin;
122
123 //Set-Up Priority List
124 for (ThreadID tid = 0; tid < numThreads; tid++) {
125 priority_list.push_back(tid);
126 }
127
128 DPRINTF(Commit,"Commit Policy set to Round Robin.\n");
129 } else if (policy == "oldestready"){
130 commitPolicy = OldestReady;
131
132 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
133 } else {
134 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
135 "RoundRobin,OldestReady}");
136 }
137
138 for (ThreadID tid = 0; tid < numThreads; tid++) {
139 commitStatus[tid] = Idle;
140 changedROBNumEntries[tid] = false;
141 checkEmptyROB[tid] = false;
142 trapInFlight[tid] = false;
143 committedStores[tid] = false;
144 trapSquash[tid] = false;
145 tcSquash[tid] = false;
146 pc[tid].set(0);
147 lastCommitedSeqNum[tid] = 0;
148 }
149 interrupt = NoFault;
150}
151
152template <class Impl>
153std::string
154DefaultCommit<Impl>::name() const
155{
156 return cpu->name() + ".commit";
157}
158
159template <class Impl>
160void
161DefaultCommit<Impl>::regStats()
162{
163 using namespace Stats;
164 commitCommittedInsts
165 .name(name() + ".commitCommittedInsts")
166 .desc("The number of committed instructions")
167 .prereq(commitCommittedInsts);
168 commitCommittedOps
169 .name(name() + ".commitCommittedOps")
170 .desc("The number of committed instructions")
171 .prereq(commitCommittedInsts);
172 commitSquashedInsts
173 .name(name() + ".commitSquashedInsts")
174 .desc("The number of squashed insts skipped by commit")
175 .prereq(commitSquashedInsts);
176 commitSquashEvents
177 .name(name() + ".commitSquashEvents")
178 .desc("The number of times commit is told to squash")
179 .prereq(commitSquashEvents);
180 commitNonSpecStalls
181 .name(name() + ".commitNonSpecStalls")
182 .desc("The number of times commit has been forced to stall to "
183 "communicate backwards")
184 .prereq(commitNonSpecStalls);
185 branchMispredicts
186 .name(name() + ".branchMispredicts")
187 .desc("The number of times a branch was mispredicted")
188 .prereq(branchMispredicts);
189 numCommittedDist
190 .init(0,commitWidth,1)
191 .name(name() + ".committed_per_cycle")
192 .desc("Number of insts commited each cycle")
193 .flags(Stats::pdf)
194 ;
195
196 instsCommitted
197 .init(cpu->numThreads)
198 .name(name() + ".committedInsts")
199 .desc("Number of instructions committed")
200 .flags(total)
201 ;
202
203 opsCommitted
204 .init(cpu->numThreads)
205 .name(name() + ".committedOps")
206 .desc("Number of ops (including micro ops) committed")
207 .flags(total)
208 ;
209
210 statComSwp
211 .init(cpu->numThreads)
212 .name(name() + ".swp_count")
213 .desc("Number of s/w prefetches committed")
214 .flags(total)
215 ;
216
217 statComRefs
218 .init(cpu->numThreads)
219 .name(name() + ".refs")
220 .desc("Number of memory references committed")
221 .flags(total)
222 ;
223
224 statComLoads
225 .init(cpu->numThreads)
226 .name(name() + ".loads")
227 .desc("Number of loads committed")
228 .flags(total)
229 ;
230
231 statComMembars
232 .init(cpu->numThreads)
233 .name(name() + ".membars")
234 .desc("Number of memory barriers committed")
235 .flags(total)
236 ;
237
238 statComBranches
239 .init(cpu->numThreads)
240 .name(name() + ".branches")
241 .desc("Number of branches committed")
242 .flags(total)
243 ;
244
245 statComFloating
246 .init(cpu->numThreads)
247 .name(name() + ".fp_insts")
248 .desc("Number of committed floating point instructions.")
249 .flags(total)
250 ;
251
252 statComInteger
253 .init(cpu->numThreads)
254 .name(name()+".int_insts")
255 .desc("Number of committed integer instructions.")
256 .flags(total)
257 ;
258
259 statComFunctionCalls
260 .init(cpu->numThreads)
261 .name(name()+".function_calls")
262 .desc("Number of function calls committed.")
263 .flags(total)
264 ;
265
266 commitEligible
267 .init(cpu->numThreads)
268 .name(name() + ".bw_limited")
269 .desc("number of insts not committed due to BW limits")
270 .flags(total)
271 ;
272
273 commitEligibleSamples
274 .name(name() + ".bw_lim_events")
275 .desc("number cycles where commit BW limit reached")
276 ;
277}
278
279template <class Impl>
280void
281DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
282{
283 thread = threads;
284}
285
286template <class Impl>
287void
288DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
289{
290 timeBuffer = tb_ptr;
291
292 // Setup wire to send information back to IEW.
293 toIEW = timeBuffer->getWire(0);
294
295 // Setup wire to read data from IEW (for the ROB).
296 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
297}
298
299template <class Impl>
300void
301DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
302{
303 fetchQueue = fq_ptr;
304
305 // Setup wire to get instructions from rename (for the ROB).
306 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
307}
308
309template <class Impl>
310void
311DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
312{
313 renameQueue = rq_ptr;
314
315 // Setup wire to get instructions from rename (for the ROB).
316 fromRename = renameQueue->getWire(-renameToROBDelay);
317}
318
319template <class Impl>
320void
321DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
322{
323 iewQueue = iq_ptr;
324
325 // Setup wire to get instructions from IEW.
326 fromIEW = iewQueue->getWire(-iewToCommitDelay);
327}
328
329template <class Impl>
330void
331DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
332{
333 iewStage = iew_stage;
334}
335
336template<class Impl>
337void
338DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
339{
340 activeThreads = at_ptr;
341}
342
343template <class Impl>
344void
345DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
346{
347 for (ThreadID tid = 0; tid < numThreads; tid++)
348 renameMap[tid] = &rm_ptr[tid];
349}
350
351template <class Impl>
352void
353DefaultCommit<Impl>::setROB(ROB *rob_ptr)
354{
355 rob = rob_ptr;
356}
357
358template <class Impl>
359void
360DefaultCommit<Impl>::initStage()
361{
362 rob->setActiveThreads(activeThreads);
363 rob->resetEntries();
364
365 // Broadcast the number of free entries.
366 for (ThreadID tid = 0; tid < numThreads; tid++) {
367 toIEW->commitInfo[tid].usedROB = true;
368 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
369 toIEW->commitInfo[tid].emptyROB = true;
370 }
371
372 // Commit must broadcast the number of free entries it has at the
373 // start of the simulation, so it starts as active.
374 cpu->activateStage(O3CPU::CommitIdx);
375
376 cpu->activityThisCycle();
377 trapLatency = cpu->ticks(trapLatency);
378}
379
380template <class Impl>
381bool
382DefaultCommit<Impl>::drain()
383{
384 drainPending = true;
385
386 return false;
387}
388
389template <class Impl>
390void
391DefaultCommit<Impl>::switchOut()
392{
393 switchedOut = true;
394 drainPending = false;
395 rob->switchOut();
396}
397
398template <class Impl>
399void
400DefaultCommit<Impl>::resume()
401{
402 drainPending = false;
403}
404
405template <class Impl>
406void
407DefaultCommit<Impl>::takeOverFrom()
408{
409 switchedOut = false;
410 _status = Active;
411 _nextStatus = Inactive;
412 for (ThreadID tid = 0; tid < numThreads; tid++) {
413 commitStatus[tid] = Idle;
414 changedROBNumEntries[tid] = false;
415 trapSquash[tid] = false;
416 tcSquash[tid] = false;
417 }
418 squashCounter = 0;
419 rob->takeOverFrom();
420}
421
422template <class Impl>
423void
424DefaultCommit<Impl>::updateStatus()
425{
426 // reset ROB changed variable
427 list<ThreadID>::iterator threads = activeThreads->begin();
428 list<ThreadID>::iterator end = activeThreads->end();
429
430 while (threads != end) {
431 ThreadID tid = *threads++;
432
433 changedROBNumEntries[tid] = false;
434
435 // Also check if any of the threads has a trap pending
436 if (commitStatus[tid] == TrapPending ||
437 commitStatus[tid] == FetchTrapPending) {
438 _nextStatus = Active;
439 }
440 }
441
442 if (_nextStatus == Inactive && _status == Active) {
443 DPRINTF(Activity, "Deactivating stage.\n");
444 cpu->deactivateStage(O3CPU::CommitIdx);
445 } else if (_nextStatus == Active && _status == Inactive) {
446 DPRINTF(Activity, "Activating stage.\n");
447 cpu->activateStage(O3CPU::CommitIdx);
448 }
449
450 _status = _nextStatus;
451}
452
453template <class Impl>
454void
455DefaultCommit<Impl>::setNextStatus()
456{
457 int squashes = 0;
458
459 list<ThreadID>::iterator threads = activeThreads->begin();
460 list<ThreadID>::iterator end = activeThreads->end();
461
462 while (threads != end) {
463 ThreadID tid = *threads++;
464
465 if (commitStatus[tid] == ROBSquashing) {
466 squashes++;
467 }
468 }
469
470 squashCounter = squashes;
471
472 // If commit is currently squashing, then it will have activity for the
473 // next cycle. Set its next status as active.
474 if (squashCounter) {
475 _nextStatus = Active;
476 }
477}
478
479template <class Impl>
480bool
481DefaultCommit<Impl>::changedROBEntries()
482{
483 list<ThreadID>::iterator threads = activeThreads->begin();
484 list<ThreadID>::iterator end = activeThreads->end();
485
486 while (threads != end) {
487 ThreadID tid = *threads++;
488
489 if (changedROBNumEntries[tid]) {
490 return true;
491 }
492 }
493
494 return false;
495}
496
497template <class Impl>
498size_t
499DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
500{
501 return rob->numFreeEntries(tid);
502}
503
504template <class Impl>
505void
506DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
507{
508 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
509
510 TrapEvent *trap = new TrapEvent(this, tid);
511
512 cpu->schedule(trap, curTick() + trapLatency);
513 trapInFlight[tid] = true;
514 thread[tid]->trapPending = true;
515}
516
517template <class Impl>
518void
519DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
520{
521 assert(!trapInFlight[tid]);
522 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
523
524 tcSquash[tid] = true;
525}
526
527template <class Impl>
528void
529DefaultCommit<Impl>::squashAll(ThreadID tid)
530{
531 // If we want to include the squashing instruction in the squash,
532 // then use one older sequence number.
533 // Hopefully this doesn't mess things up. Basically I want to squash
534 // all instructions of this thread.
535 InstSeqNum squashed_inst = rob->isEmpty() ?
536 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
537
538 // All younger instructions will be squashed. Set the sequence
539 // number as the youngest instruction in the ROB (0 in this case.
540 // Hopefully nothing breaks.)
541 youngestSeqNum[tid] = lastCommitedSeqNum[tid];
542
543 rob->squash(squashed_inst, tid);
544 changedROBNumEntries[tid] = true;
545
546 // Send back the sequence number of the squashed instruction.
547 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
548
549 // Send back the squash signal to tell stages that they should
550 // squash.
551 toIEW->commitInfo[tid].squash = true;
552
553 // Send back the rob squashing signal so other stages know that
554 // the ROB is in the process of squashing.
555 toIEW->commitInfo[tid].robSquashing = true;
556
557 toIEW->commitInfo[tid].mispredictInst = NULL;
558 toIEW->commitInfo[tid].squashInst = NULL;
559
560 toIEW->commitInfo[tid].pc = pc[tid];
561}
562
563template <class Impl>
564void
565DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
566{
567 squashAll(tid);
568
569 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
570
571 thread[tid]->trapPending = false;
572 thread[tid]->inSyscall = false;
573 trapInFlight[tid] = false;
574
575 trapSquash[tid] = false;
576
577 commitStatus[tid] = ROBSquashing;
578 cpu->activityThisCycle();
579}
580
581template <class Impl>
582void
583DefaultCommit<Impl>::squashFromTC(ThreadID tid)
584{
585 squashAll(tid);
586
587 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
588
589 thread[tid]->inSyscall = false;
590 assert(!thread[tid]->trapPending);
591
592 commitStatus[tid] = ROBSquashing;
593 cpu->activityThisCycle();
594
595 tcSquash[tid] = false;
596}
597
598template <class Impl>
599void
600DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst,
601 uint64_t squash_after_seq_num)
602{
603 youngestSeqNum[tid] = squash_after_seq_num;
604
605 rob->squash(squash_after_seq_num, tid);
606 changedROBNumEntries[tid] = true;
607
608 // Send back the sequence number of the squashed instruction.
609 toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num;
610
611 toIEW->commitInfo[tid].squashInst = head_inst;
612 // Send back the squash signal to tell stages that they should squash.
613 toIEW->commitInfo[tid].squash = true;
614
615 // Send back the rob squashing signal so other stages know that
616 // the ROB is in the process of squashing.
617 toIEW->commitInfo[tid].robSquashing = true;
618
619 toIEW->commitInfo[tid].mispredictInst = NULL;
620
621 toIEW->commitInfo[tid].pc = pc[tid];
622 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
623 tid, squash_after_seq_num);
624 commitStatus[tid] = ROBSquashing;
625}
626
627template <class Impl>
628void
629DefaultCommit<Impl>::tick()
630{
631 wroteToTimeBuffer = false;
632 _nextStatus = Inactive;
633
634 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
635 cpu->signalDrained();
636 drainPending = false;
637 return;
638 }
639
640 if (activeThreads->empty())
641 return;
642
643 list<ThreadID>::iterator threads = activeThreads->begin();
644 list<ThreadID>::iterator end = activeThreads->end();
645
646 // Check if any of the threads are done squashing. Change the
647 // status if they are done.
648 while (threads != end) {
649 ThreadID tid = *threads++;
650
651 // Clear the bit saying if the thread has committed stores
652 // this cycle.
653 committedStores[tid] = false;
654
655 if (commitStatus[tid] == ROBSquashing) {
656
657 if (rob->isDoneSquashing(tid)) {
658 commitStatus[tid] = Running;
659 } else {
660 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
661 " insts this cycle.\n", tid);
662 rob->doSquash(tid);
663 toIEW->commitInfo[tid].robSquashing = true;
664 wroteToTimeBuffer = true;
665 }
666 }
667 }
668
669 commit();
670
671 markCompletedInsts();
672
673 threads = activeThreads->begin();
674
675 while (threads != end) {
676 ThreadID tid = *threads++;
677
678 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
679 // The ROB has more instructions it can commit. Its next status
680 // will be active.
681 _nextStatus = Active;
682
683 DynInstPtr inst = rob->readHeadInst(tid);
684
685 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
686 " ROB and ready to commit\n",
687 tid, inst->seqNum, inst->pcState());
688
689 } else if (!rob->isEmpty(tid)) {
690 DynInstPtr inst = rob->readHeadInst(tid);
691
692 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
693 "%s is head of ROB and not ready\n",
694 tid, inst->seqNum, inst->pcState());
695 }
696
697 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
698 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
699 }
700
701
702 if (wroteToTimeBuffer) {
703 DPRINTF(Activity, "Activity This Cycle.\n");
704 cpu->activityThisCycle();
705 }
706
707 updateStatus();
708}
709
710template <class Impl>
711void
712DefaultCommit<Impl>::handleInterrupt()
713{
714 // Verify that we still have an interrupt to handle
715 if (!cpu->checkInterrupts(cpu->tcBase(0))) {
716 DPRINTF(Commit, "Pending interrupt is cleared by master before "
717 "it got handled. Restart fetching from the orig path.\n");
718 toIEW->commitInfo[0].clearInterrupt = true;
719 interrupt = NoFault;
720 return;
721 }
722
723 // Wait until all in flight instructions are finished before enterring
724 // the interrupt.
725 if (canHandleInterrupts && cpu->instList.empty()) {
726 // Squash or record that I need to squash this cycle if
727 // an interrupt needed to be handled.
728 DPRINTF(Commit, "Interrupt detected.\n");
729
730 // Clear the interrupt now that it's going to be handled
731 toIEW->commitInfo[0].clearInterrupt = true;
732
733 assert(!thread[0]->inSyscall);
734 thread[0]->inSyscall = true;
735
|
740#if USE_CHECKER
| |
741 if (cpu->checker) {
742 cpu->checker->handlePendingInt();
743 }
| 736 if (cpu->checker) {
737 cpu->checker->handlePendingInt();
738 }
|
744#endif
| |
745
746 // CPU will handle interrupt.
747 cpu->processInterrupts(interrupt);
748
749 thread[0]->inSyscall = false;
750
751 commitStatus[0] = TrapPending;
752
753 // Generate trap squash event.
754 generateTrapEvent(0);
755
756 interrupt = NoFault;
757 } else {
758 DPRINTF(Commit, "Interrupt pending: instruction is %sin "
759 "flight, ROB is %sempty\n",
760 canHandleInterrupts ? "not " : "",
761 cpu->instList.empty() ? "" : "not " );
762 }
763}
764
765template <class Impl>
766void
767DefaultCommit<Impl>::propagateInterrupt()
768{
769 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
770 tcSquash[0])
771 return;
772
773 // Process interrupts if interrupts are enabled, not in PAL
774 // mode, and no other traps or external squashes are currently
775 // pending.
776 // @todo: Allow other threads to handle interrupts.
777
778 // Get any interrupt that happened
779 interrupt = cpu->getInterrupts();
780
781 // Tell fetch that there is an interrupt pending. This
782 // will make fetch wait until it sees a non PAL-mode PC,
783 // at which point it stops fetching instructions.
784 if (interrupt != NoFault)
785 toIEW->commitInfo[0].interruptPending = true;
786}
787
788template <class Impl>
789void
790DefaultCommit<Impl>::commit()
791{
792 if (FullSystem) {
793 // Check if we have a interrupt and get read to handle it
794 if (cpu->checkInterrupts(cpu->tcBase(0)))
795 propagateInterrupt();
796 }
797
798 ////////////////////////////////////
799 // Check for any possible squashes, handle them first
800 ////////////////////////////////////
801 list<ThreadID>::iterator threads = activeThreads->begin();
802 list<ThreadID>::iterator end = activeThreads->end();
803
804 while (threads != end) {
805 ThreadID tid = *threads++;
806
807 // Not sure which one takes priority. I think if we have
808 // both, that's a bad sign.
809 if (trapSquash[tid] == true) {
810 assert(!tcSquash[tid]);
811 squashFromTrap(tid);
812 } else if (tcSquash[tid] == true) {
813 assert(commitStatus[tid] != TrapPending);
814 squashFromTC(tid);
815 }
816
817 // Squashed sequence number must be older than youngest valid
818 // instruction in the ROB. This prevents squashes from younger
819 // instructions overriding squashes from older instructions.
820 if (fromIEW->squash[tid] &&
821 commitStatus[tid] != TrapPending &&
822 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
823
824 if (fromIEW->mispredictInst[tid]) {
825 DPRINTF(Commit,
826 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
827 tid,
828 fromIEW->mispredictInst[tid]->instAddr(),
829 fromIEW->squashedSeqNum[tid]);
830 } else {
831 DPRINTF(Commit,
832 "[tid:%i]: Squashing due to order violation [sn:%i]\n",
833 tid, fromIEW->squashedSeqNum[tid]);
834 }
835
836 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
837 tid,
838 fromIEW->pc[tid].nextInstAddr());
839
840 commitStatus[tid] = ROBSquashing;
841
842 // If we want to include the squashing instruction in the squash,
843 // then use one older sequence number.
844 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
845
846 if (fromIEW->includeSquashInst[tid] == true) {
847 squashed_inst--;
848 }
849
850 // All younger instructions will be squashed. Set the sequence
851 // number as the youngest instruction in the ROB.
852 youngestSeqNum[tid] = squashed_inst;
853
854 rob->squash(squashed_inst, tid);
855 changedROBNumEntries[tid] = true;
856
857 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
858
859 toIEW->commitInfo[tid].squash = true;
860
861 // Send back the rob squashing signal so other stages know that
862 // the ROB is in the process of squashing.
863 toIEW->commitInfo[tid].robSquashing = true;
864
865 toIEW->commitInfo[tid].mispredictInst =
866 fromIEW->mispredictInst[tid];
867 toIEW->commitInfo[tid].branchTaken =
868 fromIEW->branchTaken[tid];
869 toIEW->commitInfo[tid].squashInst =
870 rob->findInst(tid, squashed_inst);
871 if (toIEW->commitInfo[tid].mispredictInst) {
872 if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) {
873 toIEW->commitInfo[tid].branchTaken = true;
874 }
875 }
876
877 toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
878
879 if (toIEW->commitInfo[tid].mispredictInst) {
880 ++branchMispredicts;
881 }
882 }
883
884 }
885
886 setNextStatus();
887
888 if (squashCounter != numThreads) {
889 // If we're not currently squashing, then get instructions.
890 getInsts();
891
892 // Try to commit any instructions.
893 commitInsts();
894 }
895
896 //Check for any activity
897 threads = activeThreads->begin();
898
899 while (threads != end) {
900 ThreadID tid = *threads++;
901
902 if (changedROBNumEntries[tid]) {
903 toIEW->commitInfo[tid].usedROB = true;
904 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
905
906 wroteToTimeBuffer = true;
907 changedROBNumEntries[tid] = false;
908 if (rob->isEmpty(tid))
909 checkEmptyROB[tid] = true;
910 }
911
912 // ROB is only considered "empty" for previous stages if: a)
913 // ROB is empty, b) there are no outstanding stores, c) IEW
914 // stage has received any information regarding stores that
915 // committed.
916 // c) is checked by making sure to not consider the ROB empty
917 // on the same cycle as when stores have been committed.
918 // @todo: Make this handle multi-cycle communication between
919 // commit and IEW.
920 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
921 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
922 checkEmptyROB[tid] = false;
923 toIEW->commitInfo[tid].usedROB = true;
924 toIEW->commitInfo[tid].emptyROB = true;
925 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
926 wroteToTimeBuffer = true;
927 }
928
929 }
930}
931
932template <class Impl>
933void
934DefaultCommit<Impl>::commitInsts()
935{
936 ////////////////////////////////////
937 // Handle commit
938 // Note that commit will be handled prior to putting new
939 // instructions in the ROB so that the ROB only tries to commit
940 // instructions it has in this current cycle, and not instructions
941 // it is writing in during this cycle. Can't commit and squash
942 // things at the same time...
943 ////////////////////////////////////
944
945 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
946
947 unsigned num_committed = 0;
948
949 DynInstPtr head_inst;
950
951 // Commit as many instructions as possible until the commit bandwidth
952 // limit is reached, or it becomes impossible to commit any more.
953 while (num_committed < commitWidth) {
954 // Check for any interrupt that we've already squashed for
955 // and start processing it.
956 if (interrupt != NoFault)
957 handleInterrupt();
958
959 int commit_thread = getCommittingThread();
960
961 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
962 break;
963
964 head_inst = rob->readHeadInst(commit_thread);
965
966 ThreadID tid = head_inst->threadNumber;
967
968 assert(tid == commit_thread);
969
970 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
971 head_inst->seqNum, tid);
972
973 // If the head instruction is squashed, it is ready to retire
974 // (be removed from the ROB) at any time.
975 if (head_inst->isSquashed()) {
976
977 DPRINTF(Commit, "Retiring squashed instruction from "
978 "ROB.\n");
979
980 rob->retireHead(commit_thread);
981
982 ++commitSquashedInsts;
983
984 // Record that the number of ROB entries has changed.
985 changedROBNumEntries[tid] = true;
986 } else {
987 pc[tid] = head_inst->pcState();
988
989 // Increment the total number of non-speculative instructions
990 // executed.
991 // Hack for now: it really shouldn't happen until after the
992 // commit is deemed to be successful, but this count is needed
993 // for syscalls.
994 thread[tid]->funcExeInst++;
995
996 // Try to commit the head instruction.
997 bool commit_success = commitHead(head_inst, num_committed);
998
999 if (commit_success) {
1000 ++num_committed;
1001
1002 changedROBNumEntries[tid] = true;
1003
1004 // Set the doneSeqNum to the youngest committed instruction.
1005 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
1006
1007 if (!head_inst->isMicroop() || head_inst->isLastMicroop())
1008 ++commitCommittedInsts;
1009 ++commitCommittedOps;
1010
1011 // To match the old model, don't count nops and instruction
1012 // prefetches towards the total commit count.
1013 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
1014 cpu->instDone(tid, head_inst);
1015 }
1016
1017 if (tid == 0) {
1018 canHandleInterrupts = (!head_inst->isDelayedCommit()) &&
1019 ((THE_ISA != ALPHA_ISA) ||
1020 (!(pc[0].instAddr() & 0x3)));
1021 }
1022
1023 // Updates misc. registers.
1024 head_inst->updateMiscRegs();
1025
1026 cpu->traceFunctions(pc[tid].instAddr());
1027
1028 TheISA::advancePC(pc[tid], head_inst->staticInst);
1029
1030 // Keep track of the last sequence number commited
1031 lastCommitedSeqNum[tid] = head_inst->seqNum;
1032
1033 // If this is an instruction that doesn't play nicely with
1034 // others squash everything and restart fetch
1035 if (head_inst->isSquashAfter())
1036 squashAfter(tid, head_inst, head_inst->seqNum);
1037
1038 int count = 0;
1039 Addr oldpc;
1040 // Debug statement. Checks to make sure we're not
1041 // currently updating state while handling PC events.
1042 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
1043 do {
1044 oldpc = pc[tid].instAddr();
1045 cpu->system->pcEventQueue.service(thread[tid]->getTC());
1046 count++;
1047 } while (oldpc != pc[tid].instAddr());
1048 if (count > 1) {
1049 DPRINTF(Commit,
1050 "PC skip function event, stopping commit\n");
1051 break;
1052 }
1053 } else {
1054 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1055 "[tid:%i] [sn:%i].\n",
1056 head_inst->pcState(), tid ,head_inst->seqNum);
1057 break;
1058 }
1059 }
1060 }
1061
1062 DPRINTF(CommitRate, "%i\n", num_committed);
1063 numCommittedDist.sample(num_committed);
1064
1065 if (num_committed == commitWidth) {
1066 commitEligibleSamples++;
1067 }
1068}
1069
1070template <class Impl>
1071bool
1072DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1073{
1074 assert(head_inst);
1075
1076 ThreadID tid = head_inst->threadNumber;
1077
1078 // If the instruction is not executed yet, then it will need extra
1079 // handling. Signal backwards that it should be executed.
1080 if (!head_inst->isExecuted()) {
1081 // Keep this number correct. We have not yet actually executed
1082 // and committed this instruction.
1083 thread[tid]->funcExeInst--;
1084
1085 if (head_inst->isNonSpeculative() ||
1086 head_inst->isStoreConditional() ||
1087 head_inst->isMemBarrier() ||
1088 head_inst->isWriteBarrier()) {
1089
1090 DPRINTF(Commit, "Encountered a barrier or non-speculative "
1091 "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1092 head_inst->seqNum, head_inst->pcState());
1093
1094 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1095 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1096 return false;
1097 }
1098
1099 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1100
1101 // Change the instruction so it won't try to commit again until
1102 // it is executed.
1103 head_inst->clearCanCommit();
1104
1105 ++commitNonSpecStalls;
1106
1107 return false;
1108 } else if (head_inst->isLoad()) {
1109 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1110 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1111 return false;
1112 }
1113
1114 assert(head_inst->uncacheable());
1115 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
1116 head_inst->seqNum, head_inst->pcState());
1117
1118 // Send back the non-speculative instruction's sequence
1119 // number. Tell the lsq to re-execute the load.
1120 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1121 toIEW->commitInfo[tid].uncached = true;
1122 toIEW->commitInfo[tid].uncachedLoad = head_inst;
1123
1124 head_inst->clearCanCommit();
1125
1126 return false;
1127 } else {
1128 panic("Trying to commit un-executed instruction "
1129 "of unknown type!\n");
1130 }
1131 }
1132
1133 if (head_inst->isThreadSync()) {
1134 // Not handled for now.
1135 panic("Thread sync instructions are not handled yet.\n");
1136 }
1137
1138 // Check if the instruction caused a fault. If so, trap.
1139 Fault inst_fault = head_inst->getFault();
1140
1141 // Stores mark themselves as completed.
1142 if (!head_inst->isStore() && inst_fault == NoFault) {
1143 head_inst->setCompleted();
1144 }
1145
| 739
740 // CPU will handle interrupt.
741 cpu->processInterrupts(interrupt);
742
743 thread[0]->inSyscall = false;
744
745 commitStatus[0] = TrapPending;
746
747 // Generate trap squash event.
748 generateTrapEvent(0);
749
750 interrupt = NoFault;
751 } else {
752 DPRINTF(Commit, "Interrupt pending: instruction is %sin "
753 "flight, ROB is %sempty\n",
754 canHandleInterrupts ? "not " : "",
755 cpu->instList.empty() ? "" : "not " );
756 }
757}
758
759template <class Impl>
760void
761DefaultCommit<Impl>::propagateInterrupt()
762{
763 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
764 tcSquash[0])
765 return;
766
767 // Process interrupts if interrupts are enabled, not in PAL
768 // mode, and no other traps or external squashes are currently
769 // pending.
770 // @todo: Allow other threads to handle interrupts.
771
772 // Get any interrupt that happened
773 interrupt = cpu->getInterrupts();
774
775 // Tell fetch that there is an interrupt pending. This
776 // will make fetch wait until it sees a non PAL-mode PC,
777 // at which point it stops fetching instructions.
778 if (interrupt != NoFault)
779 toIEW->commitInfo[0].interruptPending = true;
780}
781
782template <class Impl>
783void
784DefaultCommit<Impl>::commit()
785{
786 if (FullSystem) {
787 // Check if we have a interrupt and get read to handle it
788 if (cpu->checkInterrupts(cpu->tcBase(0)))
789 propagateInterrupt();
790 }
791
792 ////////////////////////////////////
793 // Check for any possible squashes, handle them first
794 ////////////////////////////////////
795 list<ThreadID>::iterator threads = activeThreads->begin();
796 list<ThreadID>::iterator end = activeThreads->end();
797
798 while (threads != end) {
799 ThreadID tid = *threads++;
800
801 // Not sure which one takes priority. I think if we have
802 // both, that's a bad sign.
803 if (trapSquash[tid] == true) {
804 assert(!tcSquash[tid]);
805 squashFromTrap(tid);
806 } else if (tcSquash[tid] == true) {
807 assert(commitStatus[tid] != TrapPending);
808 squashFromTC(tid);
809 }
810
811 // Squashed sequence number must be older than youngest valid
812 // instruction in the ROB. This prevents squashes from younger
813 // instructions overriding squashes from older instructions.
814 if (fromIEW->squash[tid] &&
815 commitStatus[tid] != TrapPending &&
816 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
817
818 if (fromIEW->mispredictInst[tid]) {
819 DPRINTF(Commit,
820 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
821 tid,
822 fromIEW->mispredictInst[tid]->instAddr(),
823 fromIEW->squashedSeqNum[tid]);
824 } else {
825 DPRINTF(Commit,
826 "[tid:%i]: Squashing due to order violation [sn:%i]\n",
827 tid, fromIEW->squashedSeqNum[tid]);
828 }
829
830 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
831 tid,
832 fromIEW->pc[tid].nextInstAddr());
833
834 commitStatus[tid] = ROBSquashing;
835
836 // If we want to include the squashing instruction in the squash,
837 // then use one older sequence number.
838 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
839
840 if (fromIEW->includeSquashInst[tid] == true) {
841 squashed_inst--;
842 }
843
844 // All younger instructions will be squashed. Set the sequence
845 // number as the youngest instruction in the ROB.
846 youngestSeqNum[tid] = squashed_inst;
847
848 rob->squash(squashed_inst, tid);
849 changedROBNumEntries[tid] = true;
850
851 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
852
853 toIEW->commitInfo[tid].squash = true;
854
855 // Send back the rob squashing signal so other stages know that
856 // the ROB is in the process of squashing.
857 toIEW->commitInfo[tid].robSquashing = true;
858
859 toIEW->commitInfo[tid].mispredictInst =
860 fromIEW->mispredictInst[tid];
861 toIEW->commitInfo[tid].branchTaken =
862 fromIEW->branchTaken[tid];
863 toIEW->commitInfo[tid].squashInst =
864 rob->findInst(tid, squashed_inst);
865 if (toIEW->commitInfo[tid].mispredictInst) {
866 if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) {
867 toIEW->commitInfo[tid].branchTaken = true;
868 }
869 }
870
871 toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
872
873 if (toIEW->commitInfo[tid].mispredictInst) {
874 ++branchMispredicts;
875 }
876 }
877
878 }
879
880 setNextStatus();
881
882 if (squashCounter != numThreads) {
883 // If we're not currently squashing, then get instructions.
884 getInsts();
885
886 // Try to commit any instructions.
887 commitInsts();
888 }
889
890 //Check for any activity
891 threads = activeThreads->begin();
892
893 while (threads != end) {
894 ThreadID tid = *threads++;
895
896 if (changedROBNumEntries[tid]) {
897 toIEW->commitInfo[tid].usedROB = true;
898 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
899
900 wroteToTimeBuffer = true;
901 changedROBNumEntries[tid] = false;
902 if (rob->isEmpty(tid))
903 checkEmptyROB[tid] = true;
904 }
905
906 // ROB is only considered "empty" for previous stages if: a)
907 // ROB is empty, b) there are no outstanding stores, c) IEW
908 // stage has received any information regarding stores that
909 // committed.
910 // c) is checked by making sure to not consider the ROB empty
911 // on the same cycle as when stores have been committed.
912 // @todo: Make this handle multi-cycle communication between
913 // commit and IEW.
914 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
915 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
916 checkEmptyROB[tid] = false;
917 toIEW->commitInfo[tid].usedROB = true;
918 toIEW->commitInfo[tid].emptyROB = true;
919 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
920 wroteToTimeBuffer = true;
921 }
922
923 }
924}
925
926template <class Impl>
927void
928DefaultCommit<Impl>::commitInsts()
929{
930 ////////////////////////////////////
931 // Handle commit
932 // Note that commit will be handled prior to putting new
933 // instructions in the ROB so that the ROB only tries to commit
934 // instructions it has in this current cycle, and not instructions
935 // it is writing in during this cycle. Can't commit and squash
936 // things at the same time...
937 ////////////////////////////////////
938
939 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
940
941 unsigned num_committed = 0;
942
943 DynInstPtr head_inst;
944
945 // Commit as many instructions as possible until the commit bandwidth
946 // limit is reached, or it becomes impossible to commit any more.
947 while (num_committed < commitWidth) {
948 // Check for any interrupt that we've already squashed for
949 // and start processing it.
950 if (interrupt != NoFault)
951 handleInterrupt();
952
953 int commit_thread = getCommittingThread();
954
955 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
956 break;
957
958 head_inst = rob->readHeadInst(commit_thread);
959
960 ThreadID tid = head_inst->threadNumber;
961
962 assert(tid == commit_thread);
963
964 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
965 head_inst->seqNum, tid);
966
967 // If the head instruction is squashed, it is ready to retire
968 // (be removed from the ROB) at any time.
969 if (head_inst->isSquashed()) {
970
971 DPRINTF(Commit, "Retiring squashed instruction from "
972 "ROB.\n");
973
974 rob->retireHead(commit_thread);
975
976 ++commitSquashedInsts;
977
978 // Record that the number of ROB entries has changed.
979 changedROBNumEntries[tid] = true;
980 } else {
981 pc[tid] = head_inst->pcState();
982
983 // Increment the total number of non-speculative instructions
984 // executed.
985 // Hack for now: it really shouldn't happen until after the
986 // commit is deemed to be successful, but this count is needed
987 // for syscalls.
988 thread[tid]->funcExeInst++;
989
990 // Try to commit the head instruction.
991 bool commit_success = commitHead(head_inst, num_committed);
992
993 if (commit_success) {
994 ++num_committed;
995
996 changedROBNumEntries[tid] = true;
997
998 // Set the doneSeqNum to the youngest committed instruction.
999 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
1000
1001 if (!head_inst->isMicroop() || head_inst->isLastMicroop())
1002 ++commitCommittedInsts;
1003 ++commitCommittedOps;
1004
1005 // To match the old model, don't count nops and instruction
1006 // prefetches towards the total commit count.
1007 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
1008 cpu->instDone(tid, head_inst);
1009 }
1010
1011 if (tid == 0) {
1012 canHandleInterrupts = (!head_inst->isDelayedCommit()) &&
1013 ((THE_ISA != ALPHA_ISA) ||
1014 (!(pc[0].instAddr() & 0x3)));
1015 }
1016
1017 // Updates misc. registers.
1018 head_inst->updateMiscRegs();
1019
1020 cpu->traceFunctions(pc[tid].instAddr());
1021
1022 TheISA::advancePC(pc[tid], head_inst->staticInst);
1023
1024 // Keep track of the last sequence number commited
1025 lastCommitedSeqNum[tid] = head_inst->seqNum;
1026
1027 // If this is an instruction that doesn't play nicely with
1028 // others squash everything and restart fetch
1029 if (head_inst->isSquashAfter())
1030 squashAfter(tid, head_inst, head_inst->seqNum);
1031
1032 int count = 0;
1033 Addr oldpc;
1034 // Debug statement. Checks to make sure we're not
1035 // currently updating state while handling PC events.
1036 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
1037 do {
1038 oldpc = pc[tid].instAddr();
1039 cpu->system->pcEventQueue.service(thread[tid]->getTC());
1040 count++;
1041 } while (oldpc != pc[tid].instAddr());
1042 if (count > 1) {
1043 DPRINTF(Commit,
1044 "PC skip function event, stopping commit\n");
1045 break;
1046 }
1047 } else {
1048 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1049 "[tid:%i] [sn:%i].\n",
1050 head_inst->pcState(), tid ,head_inst->seqNum);
1051 break;
1052 }
1053 }
1054 }
1055
1056 DPRINTF(CommitRate, "%i\n", num_committed);
1057 numCommittedDist.sample(num_committed);
1058
1059 if (num_committed == commitWidth) {
1060 commitEligibleSamples++;
1061 }
1062}
1063
1064template <class Impl>
1065bool
1066DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1067{
1068 assert(head_inst);
1069
1070 ThreadID tid = head_inst->threadNumber;
1071
1072 // If the instruction is not executed yet, then it will need extra
1073 // handling. Signal backwards that it should be executed.
1074 if (!head_inst->isExecuted()) {
1075 // Keep this number correct. We have not yet actually executed
1076 // and committed this instruction.
1077 thread[tid]->funcExeInst--;
1078
1079 if (head_inst->isNonSpeculative() ||
1080 head_inst->isStoreConditional() ||
1081 head_inst->isMemBarrier() ||
1082 head_inst->isWriteBarrier()) {
1083
1084 DPRINTF(Commit, "Encountered a barrier or non-speculative "
1085 "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1086 head_inst->seqNum, head_inst->pcState());
1087
1088 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1089 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1090 return false;
1091 }
1092
1093 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1094
1095 // Change the instruction so it won't try to commit again until
1096 // it is executed.
1097 head_inst->clearCanCommit();
1098
1099 ++commitNonSpecStalls;
1100
1101 return false;
1102 } else if (head_inst->isLoad()) {
1103 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1104 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1105 return false;
1106 }
1107
1108 assert(head_inst->uncacheable());
1109 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
1110 head_inst->seqNum, head_inst->pcState());
1111
1112 // Send back the non-speculative instruction's sequence
1113 // number. Tell the lsq to re-execute the load.
1114 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1115 toIEW->commitInfo[tid].uncached = true;
1116 toIEW->commitInfo[tid].uncachedLoad = head_inst;
1117
1118 head_inst->clearCanCommit();
1119
1120 return false;
1121 } else {
1122 panic("Trying to commit un-executed instruction "
1123 "of unknown type!\n");
1124 }
1125 }
1126
1127 if (head_inst->isThreadSync()) {
1128 // Not handled for now.
1129 panic("Thread sync instructions are not handled yet.\n");
1130 }
1131
1132 // Check if the instruction caused a fault. If so, trap.
1133 Fault inst_fault = head_inst->getFault();
1134
1135 // Stores mark themselves as completed.
1136 if (!head_inst->isStore() && inst_fault == NoFault) {
1137 head_inst->setCompleted();
1138 }
1139
|
1146#if USE_CHECKER
| |
1147 // Use checker prior to updating anything due to traps or PC
1148 // based events.
1149 if (cpu->checker) {
1150 cpu->checker->verify(head_inst);
1151 }
| 1140 // Use checker prior to updating anything due to traps or PC
1141 // based events.
1142 if (cpu->checker) {
1143 cpu->checker->verify(head_inst);
1144 }
|
1152#endif
| |
1153
1154 if (inst_fault != NoFault) {
1155 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1156 head_inst->seqNum, head_inst->pcState());
1157
1158 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1159 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1160 return false;
1161 }
1162
1163 head_inst->setCompleted();
1164
| 1145
1146 if (inst_fault != NoFault) {
1147 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1148 head_inst->seqNum, head_inst->pcState());
1149
1150 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1151 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1152 return false;
1153 }
1154
1155 head_inst->setCompleted();
1156
|
1165#if USE_CHECKER
| |
1166 if (cpu->checker) {
1167 // Need to check the instruction before its fault is processed
1168 cpu->checker->verify(head_inst);
1169 }
| 1157 if (cpu->checker) {
1158 // Need to check the instruction before its fault is processed
1159 cpu->checker->verify(head_inst);
1160 }
|
1170#endif
| |
1171
1172 assert(!thread[tid]->inSyscall);
1173
1174 // Mark that we're in state update mode so that the trap's
1175 // execution doesn't generate extra squashes.
1176 thread[tid]->inSyscall = true;
1177
1178 // Execute the trap. Although it's slightly unrealistic in
1179 // terms of timing (as it doesn't wait for the full timing of
1180 // the trap event to complete before updating state), it's
1181 // needed to update the state as soon as possible. This
1182 // prevents external agents from changing any specific state
1183 // that the trap need.
1184 cpu->trap(inst_fault, tid, head_inst->staticInst);
1185
1186 // Exit state update mode to avoid accidental updating.
1187 thread[tid]->inSyscall = false;
1188
1189 commitStatus[tid] = TrapPending;
1190
1191 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1192 head_inst->seqNum);
1193 if (head_inst->traceData) {
1194 if (DTRACE(ExecFaulting)) {
1195 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1196 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1197 head_inst->traceData->dump();
1198 }
1199 delete head_inst->traceData;
1200 head_inst->traceData = NULL;
1201 }
1202
1203 // Generate trap squash event.
1204 generateTrapEvent(tid);
1205 return false;
1206 }
1207
1208 updateComInstStats(head_inst);
1209
1210 if (FullSystem) {
1211 if (thread[tid]->profile) {
1212 thread[tid]->profilePC = head_inst->instAddr();
1213 ProfileNode *node = thread[tid]->profile->consume(
1214 thread[tid]->getTC(), head_inst->staticInst);
1215
1216 if (node)
1217 thread[tid]->profileNode = node;
1218 }
1219 if (CPA::available()) {
1220 if (head_inst->isControl()) {
1221 ThreadContext *tc = thread[tid]->getTC();
1222 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1223 }
1224 }
1225 }
1226 DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
1227 head_inst->seqNum, head_inst->pcState());
1228 if (head_inst->traceData) {
1229 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1230 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1231 head_inst->traceData->dump();
1232 delete head_inst->traceData;
1233 head_inst->traceData = NULL;
1234 }
1235 if (head_inst->isReturn()) {
1236 DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n",
1237 head_inst->seqNum, head_inst->pcState());
1238 }
1239
1240 // Update the commit rename map
1241 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1242 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1243 head_inst->renamedDestRegIdx(i));
1244 }
1245
1246 // Finally clear the head ROB entry.
1247 rob->retireHead(tid);
1248
1249#if TRACING_ON
1250 // Print info needed by the pipeline activity viewer.
1251 DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
1252 head_inst->fetchTick,
1253 head_inst->instAddr(),
1254 head_inst->microPC(),
1255 head_inst->seqNum,
1256 head_inst->staticInst->disassemble(head_inst->instAddr()));
1257 DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", head_inst->decodeTick);
1258 DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", head_inst->renameTick);
1259 DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", head_inst->dispatchTick);
1260 DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", head_inst->issueTick);
1261 DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", head_inst->completeTick);
1262 DPRINTFR(O3PipeView, "O3PipeView:retire:%llu\n", curTick());
1263#endif
1264
1265 // If this was a store, record it for this cycle.
1266 if (head_inst->isStore())
1267 committedStores[tid] = true;
1268
1269 // Return true to indicate that we have committed an instruction.
1270 return true;
1271}
1272
1273template <class Impl>
1274void
1275DefaultCommit<Impl>::getInsts()
1276{
1277 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1278
1279 // Read any renamed instructions and place them into the ROB.
1280 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1281
1282 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1283 DynInstPtr inst;
1284
1285 inst = fromRename->insts[inst_num];
1286 ThreadID tid = inst->threadNumber;
1287
1288 if (!inst->isSquashed() &&
1289 commitStatus[tid] != ROBSquashing &&
1290 commitStatus[tid] != TrapPending) {
1291 changedROBNumEntries[tid] = true;
1292
1293 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1294 inst->pcState(), inst->seqNum, tid);
1295
1296 rob->insertInst(inst);
1297
1298 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1299
1300 youngestSeqNum[tid] = inst->seqNum;
1301 } else {
1302 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1303 "squashed, skipping.\n",
1304 inst->pcState(), inst->seqNum, tid);
1305 }
1306 }
1307}
1308
1309template <class Impl>
1310void
1311DefaultCommit<Impl>::skidInsert()
1312{
1313 DPRINTF(Commit, "Attempting to any instructions from rename into "
1314 "skidBuffer.\n");
1315
1316 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1317 DynInstPtr inst = fromRename->insts[inst_num];
1318
1319 if (!inst->isSquashed()) {
1320 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1321 "skidBuffer.\n", inst->pcState(), inst->seqNum,
1322 inst->threadNumber);
1323 skidBuffer.push(inst);
1324 } else {
1325 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1326 "squashed, skipping.\n",
1327 inst->pcState(), inst->seqNum, inst->threadNumber);
1328 }
1329 }
1330}
1331
1332template <class Impl>
1333void
1334DefaultCommit<Impl>::markCompletedInsts()
1335{
1336 // Grab completed insts out of the IEW instruction queue, and mark
1337 // instructions completed within the ROB.
1338 for (int inst_num = 0;
1339 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1340 ++inst_num)
1341 {
1342 if (!fromIEW->insts[inst_num]->isSquashed()) {
1343 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1344 "within ROB.\n",
1345 fromIEW->insts[inst_num]->threadNumber,
1346 fromIEW->insts[inst_num]->pcState(),
1347 fromIEW->insts[inst_num]->seqNum);
1348
1349 // Mark the instruction as ready to commit.
1350 fromIEW->insts[inst_num]->setCanCommit();
1351 }
1352 }
1353}
1354
1355template <class Impl>
1356bool
1357DefaultCommit<Impl>::robDoneSquashing()
1358{
1359 list<ThreadID>::iterator threads = activeThreads->begin();
1360 list<ThreadID>::iterator end = activeThreads->end();
1361
1362 while (threads != end) {
1363 ThreadID tid = *threads++;
1364
1365 if (!rob->isDoneSquashing(tid))
1366 return false;
1367 }
1368
1369 return true;
1370}
1371
1372template <class Impl>
1373void
1374DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1375{
1376 ThreadID tid = inst->threadNumber;
1377
1378 //
1379 // Pick off the software prefetches
1380 //
1381#ifdef TARGET_ALPHA
1382 if (inst->isDataPrefetch()) {
1383 statComSwp[tid]++;
1384 } else {
1385 if (!inst->isMicroop() || inst->isLastMicroop())
1386 instsCommitted[tid]++;
1387 opsCommitted[tid]++;
1388 }
1389#else
1390 if (!inst->isMicroop() || inst->isLastMicroop())
1391 instsCommitted[tid]++;
1392 opsCommitted[tid]++;
1393#endif
1394
1395 //
1396 // Control Instructions
1397 //
1398 if (inst->isControl())
1399 statComBranches[tid]++;
1400
1401 //
1402 // Memory references
1403 //
1404 if (inst->isMemRef()) {
1405 statComRefs[tid]++;
1406
1407 if (inst->isLoad()) {
1408 statComLoads[tid]++;
1409 }
1410 }
1411
1412 if (inst->isMemBarrier()) {
1413 statComMembars[tid]++;
1414 }
1415
1416 // Integer Instruction
1417 if (inst->isInteger())
1418 statComInteger[tid]++;
1419
1420 // Floating Point Instruction
1421 if (inst->isFloating())
1422 statComFloating[tid]++;
1423
1424 // Function Calls
1425 if (inst->isCall())
1426 statComFunctionCalls[tid]++;
1427
1428}
1429
1430////////////////////////////////////////
1431// //
1432// SMT COMMIT POLICY MAINTAINED HERE //
1433// //
1434////////////////////////////////////////
1435template <class Impl>
1436ThreadID
1437DefaultCommit<Impl>::getCommittingThread()
1438{
1439 if (numThreads > 1) {
1440 switch (commitPolicy) {
1441
1442 case Aggressive:
1443 //If Policy is Aggressive, commit will call
1444 //this function multiple times per
1445 //cycle
1446 return oldestReady();
1447
1448 case RoundRobin:
1449 return roundRobin();
1450
1451 case OldestReady:
1452 return oldestReady();
1453
1454 default:
1455 return InvalidThreadID;
1456 }
1457 } else {
1458 assert(!activeThreads->empty());
1459 ThreadID tid = activeThreads->front();
1460
1461 if (commitStatus[tid] == Running ||
1462 commitStatus[tid] == Idle ||
1463 commitStatus[tid] == FetchTrapPending) {
1464 return tid;
1465 } else {
1466 return InvalidThreadID;
1467 }
1468 }
1469}
1470
1471template<class Impl>
1472ThreadID
1473DefaultCommit<Impl>::roundRobin()
1474{
1475 list<ThreadID>::iterator pri_iter = priority_list.begin();
1476 list<ThreadID>::iterator end = priority_list.end();
1477
1478 while (pri_iter != end) {
1479 ThreadID tid = *pri_iter;
1480
1481 if (commitStatus[tid] == Running ||
1482 commitStatus[tid] == Idle ||
1483 commitStatus[tid] == FetchTrapPending) {
1484
1485 if (rob->isHeadReady(tid)) {
1486 priority_list.erase(pri_iter);
1487 priority_list.push_back(tid);
1488
1489 return tid;
1490 }
1491 }
1492
1493 pri_iter++;
1494 }
1495
1496 return InvalidThreadID;
1497}
1498
1499template<class Impl>
1500ThreadID
1501DefaultCommit<Impl>::oldestReady()
1502{
1503 unsigned oldest = 0;
1504 bool first = true;
1505
1506 list<ThreadID>::iterator threads = activeThreads->begin();
1507 list<ThreadID>::iterator end = activeThreads->end();
1508
1509 while (threads != end) {
1510 ThreadID tid = *threads++;
1511
1512 if (!rob->isEmpty(tid) &&
1513 (commitStatus[tid] == Running ||
1514 commitStatus[tid] == Idle ||
1515 commitStatus[tid] == FetchTrapPending)) {
1516
1517 if (rob->isHeadReady(tid)) {
1518
1519 DynInstPtr head_inst = rob->readHeadInst(tid);
1520
1521 if (first) {
1522 oldest = tid;
1523 first = false;
1524 } else if (head_inst->seqNum < oldest) {
1525 oldest = tid;
1526 }
1527 }
1528 }
1529 }
1530
1531 if (!first) {
1532 return oldest;
1533 } else {
1534 return InvalidThreadID;
1535 }
1536}
| 1161
1162 assert(!thread[tid]->inSyscall);
1163
1164 // Mark that we're in state update mode so that the trap's
1165 // execution doesn't generate extra squashes.
1166 thread[tid]->inSyscall = true;
1167
1168 // Execute the trap. Although it's slightly unrealistic in
1169 // terms of timing (as it doesn't wait for the full timing of
1170 // the trap event to complete before updating state), it's
1171 // needed to update the state as soon as possible. This
1172 // prevents external agents from changing any specific state
1173 // that the trap need.
1174 cpu->trap(inst_fault, tid, head_inst->staticInst);
1175
1176 // Exit state update mode to avoid accidental updating.
1177 thread[tid]->inSyscall = false;
1178
1179 commitStatus[tid] = TrapPending;
1180
1181 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1182 head_inst->seqNum);
1183 if (head_inst->traceData) {
1184 if (DTRACE(ExecFaulting)) {
1185 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1186 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1187 head_inst->traceData->dump();
1188 }
1189 delete head_inst->traceData;
1190 head_inst->traceData = NULL;
1191 }
1192
1193 // Generate trap squash event.
1194 generateTrapEvent(tid);
1195 return false;
1196 }
1197
1198 updateComInstStats(head_inst);
1199
1200 if (FullSystem) {
1201 if (thread[tid]->profile) {
1202 thread[tid]->profilePC = head_inst->instAddr();
1203 ProfileNode *node = thread[tid]->profile->consume(
1204 thread[tid]->getTC(), head_inst->staticInst);
1205
1206 if (node)
1207 thread[tid]->profileNode = node;
1208 }
1209 if (CPA::available()) {
1210 if (head_inst->isControl()) {
1211 ThreadContext *tc = thread[tid]->getTC();
1212 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1213 }
1214 }
1215 }
1216 DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
1217 head_inst->seqNum, head_inst->pcState());
1218 if (head_inst->traceData) {
1219 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1220 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1221 head_inst->traceData->dump();
1222 delete head_inst->traceData;
1223 head_inst->traceData = NULL;
1224 }
1225 if (head_inst->isReturn()) {
1226 DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n",
1227 head_inst->seqNum, head_inst->pcState());
1228 }
1229
1230 // Update the commit rename map
1231 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1232 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1233 head_inst->renamedDestRegIdx(i));
1234 }
1235
1236 // Finally clear the head ROB entry.
1237 rob->retireHead(tid);
1238
1239#if TRACING_ON
1240 // Print info needed by the pipeline activity viewer.
1241 DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
1242 head_inst->fetchTick,
1243 head_inst->instAddr(),
1244 head_inst->microPC(),
1245 head_inst->seqNum,
1246 head_inst->staticInst->disassemble(head_inst->instAddr()));
1247 DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", head_inst->decodeTick);
1248 DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", head_inst->renameTick);
1249 DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", head_inst->dispatchTick);
1250 DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", head_inst->issueTick);
1251 DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", head_inst->completeTick);
1252 DPRINTFR(O3PipeView, "O3PipeView:retire:%llu\n", curTick());
1253#endif
1254
1255 // If this was a store, record it for this cycle.
1256 if (head_inst->isStore())
1257 committedStores[tid] = true;
1258
1259 // Return true to indicate that we have committed an instruction.
1260 return true;
1261}
1262
1263template <class Impl>
1264void
1265DefaultCommit<Impl>::getInsts()
1266{
1267 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1268
1269 // Read any renamed instructions and place them into the ROB.
1270 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1271
1272 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1273 DynInstPtr inst;
1274
1275 inst = fromRename->insts[inst_num];
1276 ThreadID tid = inst->threadNumber;
1277
1278 if (!inst->isSquashed() &&
1279 commitStatus[tid] != ROBSquashing &&
1280 commitStatus[tid] != TrapPending) {
1281 changedROBNumEntries[tid] = true;
1282
1283 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1284 inst->pcState(), inst->seqNum, tid);
1285
1286 rob->insertInst(inst);
1287
1288 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1289
1290 youngestSeqNum[tid] = inst->seqNum;
1291 } else {
1292 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1293 "squashed, skipping.\n",
1294 inst->pcState(), inst->seqNum, tid);
1295 }
1296 }
1297}
1298
1299template <class Impl>
1300void
1301DefaultCommit<Impl>::skidInsert()
1302{
1303 DPRINTF(Commit, "Attempting to any instructions from rename into "
1304 "skidBuffer.\n");
1305
1306 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1307 DynInstPtr inst = fromRename->insts[inst_num];
1308
1309 if (!inst->isSquashed()) {
1310 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1311 "skidBuffer.\n", inst->pcState(), inst->seqNum,
1312 inst->threadNumber);
1313 skidBuffer.push(inst);
1314 } else {
1315 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1316 "squashed, skipping.\n",
1317 inst->pcState(), inst->seqNum, inst->threadNumber);
1318 }
1319 }
1320}
1321
1322template <class Impl>
1323void
1324DefaultCommit<Impl>::markCompletedInsts()
1325{
1326 // Grab completed insts out of the IEW instruction queue, and mark
1327 // instructions completed within the ROB.
1328 for (int inst_num = 0;
1329 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1330 ++inst_num)
1331 {
1332 if (!fromIEW->insts[inst_num]->isSquashed()) {
1333 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1334 "within ROB.\n",
1335 fromIEW->insts[inst_num]->threadNumber,
1336 fromIEW->insts[inst_num]->pcState(),
1337 fromIEW->insts[inst_num]->seqNum);
1338
1339 // Mark the instruction as ready to commit.
1340 fromIEW->insts[inst_num]->setCanCommit();
1341 }
1342 }
1343}
1344
1345template <class Impl>
1346bool
1347DefaultCommit<Impl>::robDoneSquashing()
1348{
1349 list<ThreadID>::iterator threads = activeThreads->begin();
1350 list<ThreadID>::iterator end = activeThreads->end();
1351
1352 while (threads != end) {
1353 ThreadID tid = *threads++;
1354
1355 if (!rob->isDoneSquashing(tid))
1356 return false;
1357 }
1358
1359 return true;
1360}
1361
1362template <class Impl>
1363void
1364DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1365{
1366 ThreadID tid = inst->threadNumber;
1367
1368 //
1369 // Pick off the software prefetches
1370 //
1371#ifdef TARGET_ALPHA
1372 if (inst->isDataPrefetch()) {
1373 statComSwp[tid]++;
1374 } else {
1375 if (!inst->isMicroop() || inst->isLastMicroop())
1376 instsCommitted[tid]++;
1377 opsCommitted[tid]++;
1378 }
1379#else
1380 if (!inst->isMicroop() || inst->isLastMicroop())
1381 instsCommitted[tid]++;
1382 opsCommitted[tid]++;
1383#endif
1384
1385 //
1386 // Control Instructions
1387 //
1388 if (inst->isControl())
1389 statComBranches[tid]++;
1390
1391 //
1392 // Memory references
1393 //
1394 if (inst->isMemRef()) {
1395 statComRefs[tid]++;
1396
1397 if (inst->isLoad()) {
1398 statComLoads[tid]++;
1399 }
1400 }
1401
1402 if (inst->isMemBarrier()) {
1403 statComMembars[tid]++;
1404 }
1405
1406 // Integer Instruction
1407 if (inst->isInteger())
1408 statComInteger[tid]++;
1409
1410 // Floating Point Instruction
1411 if (inst->isFloating())
1412 statComFloating[tid]++;
1413
1414 // Function Calls
1415 if (inst->isCall())
1416 statComFunctionCalls[tid]++;
1417
1418}
1419
1420////////////////////////////////////////
1421// //
1422// SMT COMMIT POLICY MAINTAINED HERE //
1423// //
1424////////////////////////////////////////
1425template <class Impl>
1426ThreadID
1427DefaultCommit<Impl>::getCommittingThread()
1428{
1429 if (numThreads > 1) {
1430 switch (commitPolicy) {
1431
1432 case Aggressive:
1433 //If Policy is Aggressive, commit will call
1434 //this function multiple times per
1435 //cycle
1436 return oldestReady();
1437
1438 case RoundRobin:
1439 return roundRobin();
1440
1441 case OldestReady:
1442 return oldestReady();
1443
1444 default:
1445 return InvalidThreadID;
1446 }
1447 } else {
1448 assert(!activeThreads->empty());
1449 ThreadID tid = activeThreads->front();
1450
1451 if (commitStatus[tid] == Running ||
1452 commitStatus[tid] == Idle ||
1453 commitStatus[tid] == FetchTrapPending) {
1454 return tid;
1455 } else {
1456 return InvalidThreadID;
1457 }
1458 }
1459}
1460
1461template<class Impl>
1462ThreadID
1463DefaultCommit<Impl>::roundRobin()
1464{
1465 list<ThreadID>::iterator pri_iter = priority_list.begin();
1466 list<ThreadID>::iterator end = priority_list.end();
1467
1468 while (pri_iter != end) {
1469 ThreadID tid = *pri_iter;
1470
1471 if (commitStatus[tid] == Running ||
1472 commitStatus[tid] == Idle ||
1473 commitStatus[tid] == FetchTrapPending) {
1474
1475 if (rob->isHeadReady(tid)) {
1476 priority_list.erase(pri_iter);
1477 priority_list.push_back(tid);
1478
1479 return tid;
1480 }
1481 }
1482
1483 pri_iter++;
1484 }
1485
1486 return InvalidThreadID;
1487}
1488
1489template<class Impl>
1490ThreadID
1491DefaultCommit<Impl>::oldestReady()
1492{
1493 unsigned oldest = 0;
1494 bool first = true;
1495
1496 list<ThreadID>::iterator threads = activeThreads->begin();
1497 list<ThreadID>::iterator end = activeThreads->end();
1498
1499 while (threads != end) {
1500 ThreadID tid = *threads++;
1501
1502 if (!rob->isEmpty(tid) &&
1503 (commitStatus[tid] == Running ||
1504 commitStatus[tid] == Idle ||
1505 commitStatus[tid] == FetchTrapPending)) {
1506
1507 if (rob->isHeadReady(tid)) {
1508
1509 DynInstPtr head_inst = rob->readHeadInst(tid);
1510
1511 if (first) {
1512 oldest = tid;
1513 first = false;
1514 } else if (head_inst->seqNum < oldest) {
1515 oldest = tid;
1516 }
1517 }
1518 }
1519 }
1520
1521 if (!first) {
1522 return oldest;
1523 } else {
1524 return InvalidThreadID;
1525 }
1526}
|