1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#include <algorithm>
45#include <string>
46
47#include "arch/utility.hh"
48#include "base/loader/symtab.hh"
49#include "base/cp_annotate.hh"
50#include "config/full_system.hh"
51#include "config/the_isa.hh"
52#include "config/use_checker.hh"
53#include "cpu/o3/commit.hh"
54#include "cpu/o3/thread_state.hh"
55#include "cpu/exetrace.hh"
56#include "cpu/timebuf.hh"
57#include "debug/Activity.hh"
58#include "debug/Commit.hh"
59#include "debug/CommitRate.hh"
60#include "debug/ExecFaulting.hh"
61#include "debug/O3PipeView.hh"
62#include "params/DerivO3CPU.hh"
63#include "sim/faults.hh"
64
65#if USE_CHECKER
66#include "cpu/checker/cpu.hh"
67#endif
68
69using namespace std;
70
71template <class Impl>
72DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
73 ThreadID _tid)
74 : Event(CPU_Tick_Pri), commit(_commit), tid(_tid)
75{
76 this->setFlags(AutoDelete);
77}
78
79template <class Impl>
80void
81DefaultCommit<Impl>::TrapEvent::process()
82{
83 // This will get reset by commit if it was switched out at the
84 // time of this event processing.
85 commit->trapSquash[tid] = true;
86}
87
88template <class Impl>
89const char *
90DefaultCommit<Impl>::TrapEvent::description() const
91{
92 return "Trap";
93}
94
95template <class Impl>
96DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
97 : cpu(_cpu),
98 squashCounter(0),
99 iewToCommitDelay(params->iewToCommitDelay),
100 commitToIEWDelay(params->commitToIEWDelay),
101 renameToROBDelay(params->renameToROBDelay),
102 fetchToCommitDelay(params->commitToFetchDelay),
103 renameWidth(params->renameWidth),
104 commitWidth(params->commitWidth),
105 numThreads(params->numThreads),
106 drainPending(false),
107 switchedOut(false),
108 trapLatency(params->trapLatency)
109{
110 _status = Active;
111 _nextStatus = Inactive;
112 std::string policy = params->smtCommitPolicy;
113
114 //Convert string to lowercase
115 std::transform(policy.begin(), policy.end(), policy.begin(),
116 (int(*)(int)) tolower);
117
118 //Assign commit policy
119 if (policy == "aggressive"){
120 commitPolicy = Aggressive;
121
122 DPRINTF(Commit,"Commit Policy set to Aggressive.\n");
123 } else if (policy == "roundrobin"){
124 commitPolicy = RoundRobin;
125
126 //Set-Up Priority List
127 for (ThreadID tid = 0; tid < numThreads; tid++) {
128 priority_list.push_back(tid);
129 }
130
131 DPRINTF(Commit,"Commit Policy set to Round Robin.\n");
132 } else if (policy == "oldestready"){
133 commitPolicy = OldestReady;
134
135 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
136 } else {
137 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
138 "RoundRobin,OldestReady}");
139 }
140
141 for (ThreadID tid = 0; tid < numThreads; tid++) {
142 commitStatus[tid] = Idle;
143 changedROBNumEntries[tid] = false;
144 checkEmptyROB[tid] = false;
145 trapInFlight[tid] = false;
146 committedStores[tid] = false;
147 trapSquash[tid] = false;
148 tcSquash[tid] = false;
149 pc[tid].set(0);
150 lastCommitedSeqNum[tid] = 0;
151 }
152#if FULL_SYSTEM
153 interrupt = NoFault;
154#endif
155}
156
157template <class Impl>
158std::string
159DefaultCommit<Impl>::name() const
160{
161 return cpu->name() + ".commit";
162}
163
164template <class Impl>
165void
166DefaultCommit<Impl>::regStats()
167{
168 using namespace Stats;
169 commitCommittedInsts
170 .name(name() + ".commitCommittedInsts")
171 .desc("The number of committed instructions")
172 .prereq(commitCommittedInsts);
173 commitSquashedInsts
174 .name(name() + ".commitSquashedInsts")
175 .desc("The number of squashed insts skipped by commit")
176 .prereq(commitSquashedInsts);
177 commitSquashEvents
178 .name(name() + ".commitSquashEvents")
179 .desc("The number of times commit is told to squash")
180 .prereq(commitSquashEvents);
181 commitNonSpecStalls
182 .name(name() + ".commitNonSpecStalls")
183 .desc("The number of times commit has been forced to stall to "
184 "communicate backwards")
185 .prereq(commitNonSpecStalls);
186 branchMispredicts
187 .name(name() + ".branchMispredicts")
188 .desc("The number of times a branch was mispredicted")
189 .prereq(branchMispredicts);
190 numCommittedDist
191 .init(0,commitWidth,1)
192 .name(name() + ".committed_per_cycle")
193 .desc("Number of insts commited each cycle")
194 .flags(Stats::pdf)
195 ;
196
197 statComInst
198 .init(cpu->numThreads)
199 .name(name() + ".count")
200 .desc("Number of instructions committed")
201 .flags(total)
202 ;
203
204 statComSwp
205 .init(cpu->numThreads)
206 .name(name() + ".swp_count")
207 .desc("Number of s/w prefetches committed")
208 .flags(total)
209 ;
210
211 statComRefs
212 .init(cpu->numThreads)
213 .name(name() + ".refs")
214 .desc("Number of memory references committed")
215 .flags(total)
216 ;
217
218 statComLoads
219 .init(cpu->numThreads)
220 .name(name() + ".loads")
221 .desc("Number of loads committed")
222 .flags(total)
223 ;
224
225 statComMembars
226 .init(cpu->numThreads)
227 .name(name() + ".membars")
228 .desc("Number of memory barriers committed")
229 .flags(total)
230 ;
231
232 statComBranches
233 .init(cpu->numThreads)
234 .name(name() + ".branches")
235 .desc("Number of branches committed")
236 .flags(total)
237 ;
238
239 statComFloating
240 .init(cpu->numThreads)
241 .name(name() + ".fp_insts")
242 .desc("Number of committed floating point instructions.")
243 .flags(total)
244 ;
245
246 statComInteger
247 .init(cpu->numThreads)
248 .name(name()+".int_insts")
249 .desc("Number of committed integer instructions.")
250 .flags(total)
251 ;
252
253 statComFunctionCalls
254 .init(cpu->numThreads)
255 .name(name()+".function_calls")
256 .desc("Number of function calls committed.")
257 .flags(total)
258 ;
259
260 commitEligible
261 .init(cpu->numThreads)
262 .name(name() + ".bw_limited")
263 .desc("number of insts not committed due to BW limits")
264 .flags(total)
265 ;
266
267 commitEligibleSamples
268 .name(name() + ".bw_lim_events")
269 .desc("number cycles where commit BW limit reached")
270 ;
271}
272
273template <class Impl>
274void
275DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
276{
277 thread = threads;
278}
279
280template <class Impl>
281void
282DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
283{
284 timeBuffer = tb_ptr;
285
286 // Setup wire to send information back to IEW.
287 toIEW = timeBuffer->getWire(0);
288
289 // Setup wire to read data from IEW (for the ROB).
290 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
291}
292
293template <class Impl>
294void
295DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
296{
297 fetchQueue = fq_ptr;
298
299 // Setup wire to get instructions from rename (for the ROB).
300 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
301}
302
303template <class Impl>
304void
305DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
306{
307 renameQueue = rq_ptr;
308
309 // Setup wire to get instructions from rename (for the ROB).
310 fromRename = renameQueue->getWire(-renameToROBDelay);
311}
312
313template <class Impl>
314void
315DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
316{
317 iewQueue = iq_ptr;
318
319 // Setup wire to get instructions from IEW.
320 fromIEW = iewQueue->getWire(-iewToCommitDelay);
321}
322
323template <class Impl>
324void
325DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
326{
327 iewStage = iew_stage;
328}
329
330template<class Impl>
331void
332DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
333{
334 activeThreads = at_ptr;
335}
336
337template <class Impl>
338void
339DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
340{
341 for (ThreadID tid = 0; tid < numThreads; tid++)
342 renameMap[tid] = &rm_ptr[tid];
343}
344
345template <class Impl>
346void
347DefaultCommit<Impl>::setROB(ROB *rob_ptr)
348{
349 rob = rob_ptr;
350}
351
352template <class Impl>
353void
354DefaultCommit<Impl>::initStage()
355{
356 rob->setActiveThreads(activeThreads);
357 rob->resetEntries();
358
359 // Broadcast the number of free entries.
360 for (ThreadID tid = 0; tid < numThreads; tid++) {
361 toIEW->commitInfo[tid].usedROB = true;
362 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
363 toIEW->commitInfo[tid].emptyROB = true;
364 }
365
366 // Commit must broadcast the number of free entries it has at the
367 // start of the simulation, so it starts as active.
368 cpu->activateStage(O3CPU::CommitIdx);
369
370 cpu->activityThisCycle();
371 trapLatency = cpu->ticks(trapLatency);
372}
373
374template <class Impl>
375bool
376DefaultCommit<Impl>::drain()
377{
378 drainPending = true;
379
380 return false;
381}
382
383template <class Impl>
384void
385DefaultCommit<Impl>::switchOut()
386{
387 switchedOut = true;
388 drainPending = false;
389 rob->switchOut();
390}
391
392template <class Impl>
393void
394DefaultCommit<Impl>::resume()
395{
396 drainPending = false;
397}
398
399template <class Impl>
400void
401DefaultCommit<Impl>::takeOverFrom()
402{
403 switchedOut = false;
404 _status = Active;
405 _nextStatus = Inactive;
406 for (ThreadID tid = 0; tid < numThreads; tid++) {
407 commitStatus[tid] = Idle;
408 changedROBNumEntries[tid] = false;
409 trapSquash[tid] = false;
410 tcSquash[tid] = false;
411 }
412 squashCounter = 0;
413 rob->takeOverFrom();
414}
415
416template <class Impl>
417void
418DefaultCommit<Impl>::updateStatus()
419{
420 // reset ROB changed variable
421 list<ThreadID>::iterator threads = activeThreads->begin();
422 list<ThreadID>::iterator end = activeThreads->end();
423
424 while (threads != end) {
425 ThreadID tid = *threads++;
426
427 changedROBNumEntries[tid] = false;
428
429 // Also check if any of the threads has a trap pending
430 if (commitStatus[tid] == TrapPending ||
431 commitStatus[tid] == FetchTrapPending) {
432 _nextStatus = Active;
433 }
434 }
435
436 if (_nextStatus == Inactive && _status == Active) {
437 DPRINTF(Activity, "Deactivating stage.\n");
438 cpu->deactivateStage(O3CPU::CommitIdx);
439 } else if (_nextStatus == Active && _status == Inactive) {
440 DPRINTF(Activity, "Activating stage.\n");
441 cpu->activateStage(O3CPU::CommitIdx);
442 }
443
444 _status = _nextStatus;
445}
446
447template <class Impl>
448void
449DefaultCommit<Impl>::setNextStatus()
450{
451 int squashes = 0;
452
453 list<ThreadID>::iterator threads = activeThreads->begin();
454 list<ThreadID>::iterator end = activeThreads->end();
455
456 while (threads != end) {
457 ThreadID tid = *threads++;
458
459 if (commitStatus[tid] == ROBSquashing) {
460 squashes++;
461 }
462 }
463
464 squashCounter = squashes;
465
466 // If commit is currently squashing, then it will have activity for the
467 // next cycle. Set its next status as active.
468 if (squashCounter) {
469 _nextStatus = Active;
470 }
471}
472
473template <class Impl>
474bool
475DefaultCommit<Impl>::changedROBEntries()
476{
477 list<ThreadID>::iterator threads = activeThreads->begin();
478 list<ThreadID>::iterator end = activeThreads->end();
479
480 while (threads != end) {
481 ThreadID tid = *threads++;
482
483 if (changedROBNumEntries[tid]) {
484 return true;
485 }
486 }
487
488 return false;
489}
490
491template <class Impl>
492size_t
493DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
494{
495 return rob->numFreeEntries(tid);
496}
497
498template <class Impl>
499void
500DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
501{
502 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
503
504 TrapEvent *trap = new TrapEvent(this, tid);
505
506 cpu->schedule(trap, curTick() + trapLatency);
507 trapInFlight[tid] = true;
508}
509
510template <class Impl>
511void
512DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
513{
514 assert(!trapInFlight[tid]);
515 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
516
517 tcSquash[tid] = true;
518}
519
520template <class Impl>
521void
522DefaultCommit<Impl>::squashAll(ThreadID tid)
523{
524 // If we want to include the squashing instruction in the squash,
525 // then use one older sequence number.
526 // Hopefully this doesn't mess things up. Basically I want to squash
527 // all instructions of this thread.
528 InstSeqNum squashed_inst = rob->isEmpty() ?
529 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
530
531 // All younger instructions will be squashed. Set the sequence
532 // number as the youngest instruction in the ROB (0 in this case.
533 // Hopefully nothing breaks.)
534 youngestSeqNum[tid] = lastCommitedSeqNum[tid];
535
536 rob->squash(squashed_inst, tid);
537 changedROBNumEntries[tid] = true;
538
539 // Send back the sequence number of the squashed instruction.
540 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
541
542 // Send back the squash signal to tell stages that they should
543 // squash.
544 toIEW->commitInfo[tid].squash = true;
545
546 // Send back the rob squashing signal so other stages know that
547 // the ROB is in the process of squashing.
548 toIEW->commitInfo[tid].robSquashing = true;
549
550 toIEW->commitInfo[tid].mispredictInst = NULL;
551 toIEW->commitInfo[tid].squashInst = NULL;
552
553 toIEW->commitInfo[tid].pc = pc[tid];
554}
555
556template <class Impl>
557void
558DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
559{
560 squashAll(tid);
561
562 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
563
564 thread[tid]->trapPending = false;
565 thread[tid]->inSyscall = false;
566 trapInFlight[tid] = false;
567
568 trapSquash[tid] = false;
569
570 commitStatus[tid] = ROBSquashing;
571 cpu->activityThisCycle();
572}
573
574template <class Impl>
575void
576DefaultCommit<Impl>::squashFromTC(ThreadID tid)
577{
578 squashAll(tid);
579
580 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
581
582 thread[tid]->inSyscall = false;
583 assert(!thread[tid]->trapPending);
584
585 commitStatus[tid] = ROBSquashing;
586 cpu->activityThisCycle();
587
588 tcSquash[tid] = false;
589}
590
591template <class Impl>
592void
593DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst,
594 uint64_t squash_after_seq_num)
595{
596 youngestSeqNum[tid] = squash_after_seq_num;
597
598 rob->squash(squash_after_seq_num, tid);
599 changedROBNumEntries[tid] = true;
600
601 // Send back the sequence number of the squashed instruction.
602 toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num;
603
604 toIEW->commitInfo[tid].squashInst = head_inst;
605 // Send back the squash signal to tell stages that they should squash.
606 toIEW->commitInfo[tid].squash = true;
607
608 // Send back the rob squashing signal so other stages know that
609 // the ROB is in the process of squashing.
610 toIEW->commitInfo[tid].robSquashing = true;
611
612 toIEW->commitInfo[tid].mispredictInst = NULL;
613
614 toIEW->commitInfo[tid].pc = pc[tid];
615 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
616 tid, squash_after_seq_num);
617 commitStatus[tid] = ROBSquashing;
618}
619
620template <class Impl>
621void
622DefaultCommit<Impl>::tick()
623{
624 wroteToTimeBuffer = false;
625 _nextStatus = Inactive;
626
627 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
628 cpu->signalDrained();
629 drainPending = false;
630 return;
631 }
632
633 if (activeThreads->empty())
634 return;
635
636 list<ThreadID>::iterator threads = activeThreads->begin();
637 list<ThreadID>::iterator end = activeThreads->end();
638
639 // Check if any of the threads are done squashing. Change the
640 // status if they are done.
641 while (threads != end) {
642 ThreadID tid = *threads++;
643
644 // Clear the bit saying if the thread has committed stores
645 // this cycle.
646 committedStores[tid] = false;
647
648 if (commitStatus[tid] == ROBSquashing) {
649
650 if (rob->isDoneSquashing(tid)) {
651 commitStatus[tid] = Running;
652 } else {
653 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
654 " insts this cycle.\n", tid);
655 rob->doSquash(tid);
656 toIEW->commitInfo[tid].robSquashing = true;
657 wroteToTimeBuffer = true;
658 }
659 }
660 }
661
662 commit();
663
664 markCompletedInsts();
665
666 threads = activeThreads->begin();
667
668 while (threads != end) {
669 ThreadID tid = *threads++;
670
671 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
672 // The ROB has more instructions it can commit. Its next status
673 // will be active.
674 _nextStatus = Active;
675
676 DynInstPtr inst = rob->readHeadInst(tid);
677
678 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
679 " ROB and ready to commit\n",
680 tid, inst->seqNum, inst->pcState());
681
682 } else if (!rob->isEmpty(tid)) {
683 DynInstPtr inst = rob->readHeadInst(tid);
684
685 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
686 "%s is head of ROB and not ready\n",
687 tid, inst->seqNum, inst->pcState());
688 }
689
690 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
691 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
692 }
693
694
695 if (wroteToTimeBuffer) {
696 DPRINTF(Activity, "Activity This Cycle.\n");
697 cpu->activityThisCycle();
698 }
699
700 updateStatus();
701}
702
703#if FULL_SYSTEM
704template <class Impl>
705void
706DefaultCommit<Impl>::handleInterrupt()
707{
708 // Verify that we still have an interrupt to handle
709 if (!cpu->checkInterrupts(cpu->tcBase(0))) {
710 DPRINTF(Commit, "Pending interrupt is cleared by master before "
711 "it got handled. Restart fetching from the orig path.\n");
712 toIEW->commitInfo[0].clearInterrupt = true;
713 interrupt = NoFault;
714 return;
715 }
716
717 // Wait until all in flight instructions are finished before enterring
718 // the interrupt.
719 if (cpu->instList.empty()) {
720 // Squash or record that I need to squash this cycle if
721 // an interrupt needed to be handled.
722 DPRINTF(Commit, "Interrupt detected.\n");
723
724 // Clear the interrupt now that it's going to be handled
725 toIEW->commitInfo[0].clearInterrupt = true;
726
727 assert(!thread[0]->inSyscall);
728 thread[0]->inSyscall = true;
729
730 // CPU will handle interrupt.
731 cpu->processInterrupts(interrupt);
732
733 thread[0]->inSyscall = false;
734
735 commitStatus[0] = TrapPending;
736
737 // Generate trap squash event.
738 generateTrapEvent(0);
739
740 interrupt = NoFault;
741 } else {
742 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
743 }
744}
745
746template <class Impl>
747void
748DefaultCommit<Impl>::propagateInterrupt()
749{
750 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
751 tcSquash[0])
752 return;
753
754 // Process interrupts if interrupts are enabled, not in PAL
755 // mode, and no other traps or external squashes are currently
756 // pending.
757 // @todo: Allow other threads to handle interrupts.
758
759 // Get any interrupt that happened
760 interrupt = cpu->getInterrupts();
761
762 // Tell fetch that there is an interrupt pending. This
763 // will make fetch wait until it sees a non PAL-mode PC,
764 // at which point it stops fetching instructions.
765 if (interrupt != NoFault)
766 toIEW->commitInfo[0].interruptPending = true;
767}
768
769#endif // FULL_SYSTEM
770
771template <class Impl>
772void
773DefaultCommit<Impl>::commit()
774{
775
776#if FULL_SYSTEM
777 // Check for any interrupt that we've already squashed for and start processing it.
778 if (interrupt != NoFault)
779 handleInterrupt();
780
781 // Check if we have a interrupt and get read to handle it
782 if (cpu->checkInterrupts(cpu->tcBase(0)))
783 propagateInterrupt();
784#endif // FULL_SYSTEM
785
786 ////////////////////////////////////
787 // Check for any possible squashes, handle them first
788 ////////////////////////////////////
789 list<ThreadID>::iterator threads = activeThreads->begin();
790 list<ThreadID>::iterator end = activeThreads->end();
791
792 while (threads != end) {
793 ThreadID tid = *threads++;
794
795 // Not sure which one takes priority. I think if we have
796 // both, that's a bad sign.
797 if (trapSquash[tid] == true) {
798 assert(!tcSquash[tid]);
799 squashFromTrap(tid);
800 } else if (tcSquash[tid] == true) {
801 assert(commitStatus[tid] != TrapPending);
802 squashFromTC(tid);
803 }
804
805 // Squashed sequence number must be older than youngest valid
806 // instruction in the ROB. This prevents squashes from younger
807 // instructions overriding squashes from older instructions.
808 if (fromIEW->squash[tid] &&
809 commitStatus[tid] != TrapPending &&
810 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
811
812 if (fromIEW->mispredictInst[tid]) {
813 DPRINTF(Commit,
814 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
815 tid,
816 fromIEW->mispredictInst[tid]->instAddr(),
817 fromIEW->squashedSeqNum[tid]);
818 } else {
819 DPRINTF(Commit,
820 "[tid:%i]: Squashing due to order violation [sn:%i]\n",
821 tid, fromIEW->squashedSeqNum[tid]);
822 }
823
824 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
825 tid,
826 fromIEW->pc[tid].nextInstAddr());
827
828 commitStatus[tid] = ROBSquashing;
829
830 // If we want to include the squashing instruction in the squash,
831 // then use one older sequence number.
832 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
833
834 if (fromIEW->includeSquashInst[tid] == true) {
835 squashed_inst--;
836 }
837
838 // All younger instructions will be squashed. Set the sequence
839 // number as the youngest instruction in the ROB.
840 youngestSeqNum[tid] = squashed_inst;
841
842 rob->squash(squashed_inst, tid);
843 changedROBNumEntries[tid] = true;
844
845 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
846
847 toIEW->commitInfo[tid].squash = true;
848
849 // Send back the rob squashing signal so other stages know that
850 // the ROB is in the process of squashing.
851 toIEW->commitInfo[tid].robSquashing = true;
852
853 toIEW->commitInfo[tid].mispredictInst =
854 fromIEW->mispredictInst[tid];
855 toIEW->commitInfo[tid].branchTaken =
856 fromIEW->branchTaken[tid];
857 toIEW->commitInfo[tid].squashInst = NULL;
858
859 toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
860
861 if (toIEW->commitInfo[tid].mispredictInst) {
862 ++branchMispredicts;
863 }
864 }
865
866 }
867
868 setNextStatus();
869
870 if (squashCounter != numThreads) {
871 // If we're not currently squashing, then get instructions.
872 getInsts();
873
874 // Try to commit any instructions.
875 commitInsts();
876 }
877
878 //Check for any activity
879 threads = activeThreads->begin();
880
881 while (threads != end) {
882 ThreadID tid = *threads++;
883
884 if (changedROBNumEntries[tid]) {
885 toIEW->commitInfo[tid].usedROB = true;
886 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
887
888 wroteToTimeBuffer = true;
889 changedROBNumEntries[tid] = false;
890 if (rob->isEmpty(tid))
891 checkEmptyROB[tid] = true;
892 }
893
894 // ROB is only considered "empty" for previous stages if: a)
895 // ROB is empty, b) there are no outstanding stores, c) IEW
896 // stage has received any information regarding stores that
897 // committed.
898 // c) is checked by making sure to not consider the ROB empty
899 // on the same cycle as when stores have been committed.
900 // @todo: Make this handle multi-cycle communication between
901 // commit and IEW.
902 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
903 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
904 checkEmptyROB[tid] = false;
905 toIEW->commitInfo[tid].usedROB = true;
906 toIEW->commitInfo[tid].emptyROB = true;
907 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
908 wroteToTimeBuffer = true;
909 }
910
911 }
912}
913
914template <class Impl>
915void
916DefaultCommit<Impl>::commitInsts()
917{
918 ////////////////////////////////////
919 // Handle commit
920 // Note that commit will be handled prior to putting new
921 // instructions in the ROB so that the ROB only tries to commit
922 // instructions it has in this current cycle, and not instructions
923 // it is writing in during this cycle. Can't commit and squash
924 // things at the same time...
925 ////////////////////////////////////
926
927 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
928
929 unsigned num_committed = 0;
930
931 DynInstPtr head_inst;
932
933 // Commit as many instructions as possible until the commit bandwidth
934 // limit is reached, or it becomes impossible to commit any more.
935 while (num_committed < commitWidth) {
936 int commit_thread = getCommittingThread();
937
938 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
939 break;
940
941 head_inst = rob->readHeadInst(commit_thread);
942
943 ThreadID tid = head_inst->threadNumber;
944
945 assert(tid == commit_thread);
946
947 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
948 head_inst->seqNum, tid);
949
950 // If the head instruction is squashed, it is ready to retire
951 // (be removed from the ROB) at any time.
952 if (head_inst->isSquashed()) {
953
954 DPRINTF(Commit, "Retiring squashed instruction from "
955 "ROB.\n");
956
957 rob->retireHead(commit_thread);
958
959 ++commitSquashedInsts;
960
961 // Record that the number of ROB entries has changed.
962 changedROBNumEntries[tid] = true;
963 } else {
964 pc[tid] = head_inst->pcState();
965
966 // Increment the total number of non-speculative instructions
967 // executed.
968 // Hack for now: it really shouldn't happen until after the
969 // commit is deemed to be successful, but this count is needed
970 // for syscalls.
971 thread[tid]->funcExeInst++;
972
973 // Try to commit the head instruction.
974 bool commit_success = commitHead(head_inst, num_committed);
975
976 if (commit_success) {
977 ++num_committed;
978
979 changedROBNumEntries[tid] = true;
980
981 // Set the doneSeqNum to the youngest committed instruction.
982 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
983
984 ++commitCommittedInsts;
985
986 // To match the old model, don't count nops and instruction
987 // prefetches towards the total commit count.
988 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
989 cpu->instDone(tid);
990 }
991
992 // Updates misc. registers.
993 head_inst->updateMiscRegs();
994
995 TheISA::advancePC(pc[tid], head_inst->staticInst);
996
997 // Keep track of the last sequence number commited
998 lastCommitedSeqNum[tid] = head_inst->seqNum;
999
1000 // If this is an instruction that doesn't play nicely with
1001 // others squash everything and restart fetch
1002 if (head_inst->isSquashAfter())
1003 squashAfter(tid, head_inst, head_inst->seqNum);
1004
1005 int count = 0;
1006 Addr oldpc;
1007 // Debug statement. Checks to make sure we're not
1008 // currently updating state while handling PC events.
1009 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
1010 do {
1011 oldpc = pc[tid].instAddr();
1012 cpu->system->pcEventQueue.service(thread[tid]->getTC());
1013 count++;
1014 } while (oldpc != pc[tid].instAddr());
1015 if (count > 1) {
1016 DPRINTF(Commit,
1017 "PC skip function event, stopping commit\n");
1018 break;
1019 }
1020 } else {
1021 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1022 "[tid:%i] [sn:%i].\n",
1023 head_inst->pcState(), tid ,head_inst->seqNum);
1024 break;
1025 }
1026 }
1027 }
1028
1029 DPRINTF(CommitRate, "%i\n", num_committed);
1030 numCommittedDist.sample(num_committed);
1031
1032 if (num_committed == commitWidth) {
1033 commitEligibleSamples++;
1034 }
1035}
1036
1037template <class Impl>
1038bool
1039DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1040{
1041 assert(head_inst);
1042
1043 ThreadID tid = head_inst->threadNumber;
1044
1045 // If the instruction is not executed yet, then it will need extra
1046 // handling. Signal backwards that it should be executed.
1047 if (!head_inst->isExecuted()) {
1048 // Keep this number correct. We have not yet actually executed
1049 // and committed this instruction.
1050 thread[tid]->funcExeInst--;
1051
1052 if (head_inst->isNonSpeculative() ||
1053 head_inst->isStoreConditional() ||
1054 head_inst->isMemBarrier() ||
1055 head_inst->isWriteBarrier()) {
1056
1057 DPRINTF(Commit, "Encountered a barrier or non-speculative "
1058 "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1059 head_inst->seqNum, head_inst->pcState());
1060
1061 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1062 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1063 return false;
1064 }
1065
1066 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1067
1068 // Change the instruction so it won't try to commit again until
1069 // it is executed.
1070 head_inst->clearCanCommit();
1071
1072 ++commitNonSpecStalls;
1073
1074 return false;
1075 } else if (head_inst->isLoad()) {
1076 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1077 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1078 return false;
1079 }
1080
1081 assert(head_inst->uncacheable());
1082 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
1083 head_inst->seqNum, head_inst->pcState());
1084
1085 // Send back the non-speculative instruction's sequence
1086 // number. Tell the lsq to re-execute the load.
1087 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1088 toIEW->commitInfo[tid].uncached = true;
1089 toIEW->commitInfo[tid].uncachedLoad = head_inst;
1090
1091 head_inst->clearCanCommit();
1092
1093 return false;
1094 } else {
1095 panic("Trying to commit un-executed instruction "
1096 "of unknown type!\n");
1097 }
1098 }
1099
1100 if (head_inst->isThreadSync()) {
1101 // Not handled for now.
1102 panic("Thread sync instructions are not handled yet.\n");
1103 }
1104
1105 // Check if the instruction caused a fault. If so, trap.
1106 Fault inst_fault = head_inst->getFault();
1107
1108 // Stores mark themselves as completed.
1109 if (!head_inst->isStore() && inst_fault == NoFault) {
1110 head_inst->setCompleted();
1111 }
1112
1113#if USE_CHECKER
1114 // Use checker prior to updating anything due to traps or PC
1115 // based events.
1116 if (cpu->checker) {
1117 cpu->checker->verify(head_inst);
1118 }
1119#endif
1120
1121 if (inst_fault != NoFault) {
1122 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1123 head_inst->seqNum, head_inst->pcState());
1124
1125 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1126 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1127 return false;
1128 }
1129
1130 head_inst->setCompleted();
1131
1132#if USE_CHECKER
1133 if (cpu->checker && head_inst->isStore()) {
1134 cpu->checker->verify(head_inst);
1135 }
1136#endif
1137
1138 assert(!thread[tid]->inSyscall);
1139
1140 // Mark that we're in state update mode so that the trap's
1141 // execution doesn't generate extra squashes.
1142 thread[tid]->inSyscall = true;
1143
1144 // Execute the trap. Although it's slightly unrealistic in
1145 // terms of timing (as it doesn't wait for the full timing of
1146 // the trap event to complete before updating state), it's
1147 // needed to update the state as soon as possible. This
1148 // prevents external agents from changing any specific state
1149 // that the trap need.
1150 cpu->trap(inst_fault, tid, head_inst->staticInst);
1151
1152 // Exit state update mode to avoid accidental updating.
1153 thread[tid]->inSyscall = false;
1154
1155 commitStatus[tid] = TrapPending;
1156
1157 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1158 head_inst->seqNum);
1159 if (head_inst->traceData) {
1160 if (DTRACE(ExecFaulting)) {
1161 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1162 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1163 head_inst->traceData->dump();
1164 }
1165 delete head_inst->traceData;
1166 head_inst->traceData = NULL;
1167 }
1168
1169 // Generate trap squash event.
1170 generateTrapEvent(tid);
1171 return false;
1172 }
1173
1174 updateComInstStats(head_inst);
1175
1176#if FULL_SYSTEM
1177 if (thread[tid]->profile) {
1178 thread[tid]->profilePC = head_inst->instAddr();
1179 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1180 head_inst->staticInst);
1181
1182 if (node)
1183 thread[tid]->profileNode = node;
1184 }
1185 if (CPA::available()) {
1186 if (head_inst->isControl()) {
1187 ThreadContext *tc = thread[tid]->getTC();
1188 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1189 }
1190 }
1191#endif
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#include <algorithm>
45#include <string>
46
47#include "arch/utility.hh"
48#include "base/loader/symtab.hh"
49#include "base/cp_annotate.hh"
50#include "config/full_system.hh"
51#include "config/the_isa.hh"
52#include "config/use_checker.hh"
53#include "cpu/o3/commit.hh"
54#include "cpu/o3/thread_state.hh"
55#include "cpu/exetrace.hh"
56#include "cpu/timebuf.hh"
57#include "debug/Activity.hh"
58#include "debug/Commit.hh"
59#include "debug/CommitRate.hh"
60#include "debug/ExecFaulting.hh"
61#include "debug/O3PipeView.hh"
62#include "params/DerivO3CPU.hh"
63#include "sim/faults.hh"
64
65#if USE_CHECKER
66#include "cpu/checker/cpu.hh"
67#endif
68
69using namespace std;
70
71template <class Impl>
72DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
73 ThreadID _tid)
74 : Event(CPU_Tick_Pri), commit(_commit), tid(_tid)
75{
76 this->setFlags(AutoDelete);
77}
78
79template <class Impl>
80void
81DefaultCommit<Impl>::TrapEvent::process()
82{
83 // This will get reset by commit if it was switched out at the
84 // time of this event processing.
85 commit->trapSquash[tid] = true;
86}
87
88template <class Impl>
89const char *
90DefaultCommit<Impl>::TrapEvent::description() const
91{
92 return "Trap";
93}
94
95template <class Impl>
96DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
97 : cpu(_cpu),
98 squashCounter(0),
99 iewToCommitDelay(params->iewToCommitDelay),
100 commitToIEWDelay(params->commitToIEWDelay),
101 renameToROBDelay(params->renameToROBDelay),
102 fetchToCommitDelay(params->commitToFetchDelay),
103 renameWidth(params->renameWidth),
104 commitWidth(params->commitWidth),
105 numThreads(params->numThreads),
106 drainPending(false),
107 switchedOut(false),
108 trapLatency(params->trapLatency)
109{
110 _status = Active;
111 _nextStatus = Inactive;
112 std::string policy = params->smtCommitPolicy;
113
114 //Convert string to lowercase
115 std::transform(policy.begin(), policy.end(), policy.begin(),
116 (int(*)(int)) tolower);
117
118 //Assign commit policy
119 if (policy == "aggressive"){
120 commitPolicy = Aggressive;
121
122 DPRINTF(Commit,"Commit Policy set to Aggressive.\n");
123 } else if (policy == "roundrobin"){
124 commitPolicy = RoundRobin;
125
126 //Set-Up Priority List
127 for (ThreadID tid = 0; tid < numThreads; tid++) {
128 priority_list.push_back(tid);
129 }
130
131 DPRINTF(Commit,"Commit Policy set to Round Robin.\n");
132 } else if (policy == "oldestready"){
133 commitPolicy = OldestReady;
134
135 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
136 } else {
137 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
138 "RoundRobin,OldestReady}");
139 }
140
141 for (ThreadID tid = 0; tid < numThreads; tid++) {
142 commitStatus[tid] = Idle;
143 changedROBNumEntries[tid] = false;
144 checkEmptyROB[tid] = false;
145 trapInFlight[tid] = false;
146 committedStores[tid] = false;
147 trapSquash[tid] = false;
148 tcSquash[tid] = false;
149 pc[tid].set(0);
150 lastCommitedSeqNum[tid] = 0;
151 }
152#if FULL_SYSTEM
153 interrupt = NoFault;
154#endif
155}
156
157template <class Impl>
158std::string
159DefaultCommit<Impl>::name() const
160{
161 return cpu->name() + ".commit";
162}
163
164template <class Impl>
165void
166DefaultCommit<Impl>::regStats()
167{
168 using namespace Stats;
169 commitCommittedInsts
170 .name(name() + ".commitCommittedInsts")
171 .desc("The number of committed instructions")
172 .prereq(commitCommittedInsts);
173 commitSquashedInsts
174 .name(name() + ".commitSquashedInsts")
175 .desc("The number of squashed insts skipped by commit")
176 .prereq(commitSquashedInsts);
177 commitSquashEvents
178 .name(name() + ".commitSquashEvents")
179 .desc("The number of times commit is told to squash")
180 .prereq(commitSquashEvents);
181 commitNonSpecStalls
182 .name(name() + ".commitNonSpecStalls")
183 .desc("The number of times commit has been forced to stall to "
184 "communicate backwards")
185 .prereq(commitNonSpecStalls);
186 branchMispredicts
187 .name(name() + ".branchMispredicts")
188 .desc("The number of times a branch was mispredicted")
189 .prereq(branchMispredicts);
190 numCommittedDist
191 .init(0,commitWidth,1)
192 .name(name() + ".committed_per_cycle")
193 .desc("Number of insts commited each cycle")
194 .flags(Stats::pdf)
195 ;
196
197 statComInst
198 .init(cpu->numThreads)
199 .name(name() + ".count")
200 .desc("Number of instructions committed")
201 .flags(total)
202 ;
203
204 statComSwp
205 .init(cpu->numThreads)
206 .name(name() + ".swp_count")
207 .desc("Number of s/w prefetches committed")
208 .flags(total)
209 ;
210
211 statComRefs
212 .init(cpu->numThreads)
213 .name(name() + ".refs")
214 .desc("Number of memory references committed")
215 .flags(total)
216 ;
217
218 statComLoads
219 .init(cpu->numThreads)
220 .name(name() + ".loads")
221 .desc("Number of loads committed")
222 .flags(total)
223 ;
224
225 statComMembars
226 .init(cpu->numThreads)
227 .name(name() + ".membars")
228 .desc("Number of memory barriers committed")
229 .flags(total)
230 ;
231
232 statComBranches
233 .init(cpu->numThreads)
234 .name(name() + ".branches")
235 .desc("Number of branches committed")
236 .flags(total)
237 ;
238
239 statComFloating
240 .init(cpu->numThreads)
241 .name(name() + ".fp_insts")
242 .desc("Number of committed floating point instructions.")
243 .flags(total)
244 ;
245
246 statComInteger
247 .init(cpu->numThreads)
248 .name(name()+".int_insts")
249 .desc("Number of committed integer instructions.")
250 .flags(total)
251 ;
252
253 statComFunctionCalls
254 .init(cpu->numThreads)
255 .name(name()+".function_calls")
256 .desc("Number of function calls committed.")
257 .flags(total)
258 ;
259
260 commitEligible
261 .init(cpu->numThreads)
262 .name(name() + ".bw_limited")
263 .desc("number of insts not committed due to BW limits")
264 .flags(total)
265 ;
266
267 commitEligibleSamples
268 .name(name() + ".bw_lim_events")
269 .desc("number cycles where commit BW limit reached")
270 ;
271}
272
273template <class Impl>
274void
275DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
276{
277 thread = threads;
278}
279
280template <class Impl>
281void
282DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
283{
284 timeBuffer = tb_ptr;
285
286 // Setup wire to send information back to IEW.
287 toIEW = timeBuffer->getWire(0);
288
289 // Setup wire to read data from IEW (for the ROB).
290 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
291}
292
293template <class Impl>
294void
295DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
296{
297 fetchQueue = fq_ptr;
298
299 // Setup wire to get instructions from rename (for the ROB).
300 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
301}
302
303template <class Impl>
304void
305DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
306{
307 renameQueue = rq_ptr;
308
309 // Setup wire to get instructions from rename (for the ROB).
310 fromRename = renameQueue->getWire(-renameToROBDelay);
311}
312
313template <class Impl>
314void
315DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
316{
317 iewQueue = iq_ptr;
318
319 // Setup wire to get instructions from IEW.
320 fromIEW = iewQueue->getWire(-iewToCommitDelay);
321}
322
323template <class Impl>
324void
325DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
326{
327 iewStage = iew_stage;
328}
329
330template<class Impl>
331void
332DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
333{
334 activeThreads = at_ptr;
335}
336
337template <class Impl>
338void
339DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
340{
341 for (ThreadID tid = 0; tid < numThreads; tid++)
342 renameMap[tid] = &rm_ptr[tid];
343}
344
345template <class Impl>
346void
347DefaultCommit<Impl>::setROB(ROB *rob_ptr)
348{
349 rob = rob_ptr;
350}
351
352template <class Impl>
353void
354DefaultCommit<Impl>::initStage()
355{
356 rob->setActiveThreads(activeThreads);
357 rob->resetEntries();
358
359 // Broadcast the number of free entries.
360 for (ThreadID tid = 0; tid < numThreads; tid++) {
361 toIEW->commitInfo[tid].usedROB = true;
362 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
363 toIEW->commitInfo[tid].emptyROB = true;
364 }
365
366 // Commit must broadcast the number of free entries it has at the
367 // start of the simulation, so it starts as active.
368 cpu->activateStage(O3CPU::CommitIdx);
369
370 cpu->activityThisCycle();
371 trapLatency = cpu->ticks(trapLatency);
372}
373
374template <class Impl>
375bool
376DefaultCommit<Impl>::drain()
377{
378 drainPending = true;
379
380 return false;
381}
382
383template <class Impl>
384void
385DefaultCommit<Impl>::switchOut()
386{
387 switchedOut = true;
388 drainPending = false;
389 rob->switchOut();
390}
391
392template <class Impl>
393void
394DefaultCommit<Impl>::resume()
395{
396 drainPending = false;
397}
398
399template <class Impl>
400void
401DefaultCommit<Impl>::takeOverFrom()
402{
403 switchedOut = false;
404 _status = Active;
405 _nextStatus = Inactive;
406 for (ThreadID tid = 0; tid < numThreads; tid++) {
407 commitStatus[tid] = Idle;
408 changedROBNumEntries[tid] = false;
409 trapSquash[tid] = false;
410 tcSquash[tid] = false;
411 }
412 squashCounter = 0;
413 rob->takeOverFrom();
414}
415
416template <class Impl>
417void
418DefaultCommit<Impl>::updateStatus()
419{
420 // reset ROB changed variable
421 list<ThreadID>::iterator threads = activeThreads->begin();
422 list<ThreadID>::iterator end = activeThreads->end();
423
424 while (threads != end) {
425 ThreadID tid = *threads++;
426
427 changedROBNumEntries[tid] = false;
428
429 // Also check if any of the threads has a trap pending
430 if (commitStatus[tid] == TrapPending ||
431 commitStatus[tid] == FetchTrapPending) {
432 _nextStatus = Active;
433 }
434 }
435
436 if (_nextStatus == Inactive && _status == Active) {
437 DPRINTF(Activity, "Deactivating stage.\n");
438 cpu->deactivateStage(O3CPU::CommitIdx);
439 } else if (_nextStatus == Active && _status == Inactive) {
440 DPRINTF(Activity, "Activating stage.\n");
441 cpu->activateStage(O3CPU::CommitIdx);
442 }
443
444 _status = _nextStatus;
445}
446
447template <class Impl>
448void
449DefaultCommit<Impl>::setNextStatus()
450{
451 int squashes = 0;
452
453 list<ThreadID>::iterator threads = activeThreads->begin();
454 list<ThreadID>::iterator end = activeThreads->end();
455
456 while (threads != end) {
457 ThreadID tid = *threads++;
458
459 if (commitStatus[tid] == ROBSquashing) {
460 squashes++;
461 }
462 }
463
464 squashCounter = squashes;
465
466 // If commit is currently squashing, then it will have activity for the
467 // next cycle. Set its next status as active.
468 if (squashCounter) {
469 _nextStatus = Active;
470 }
471}
472
473template <class Impl>
474bool
475DefaultCommit<Impl>::changedROBEntries()
476{
477 list<ThreadID>::iterator threads = activeThreads->begin();
478 list<ThreadID>::iterator end = activeThreads->end();
479
480 while (threads != end) {
481 ThreadID tid = *threads++;
482
483 if (changedROBNumEntries[tid]) {
484 return true;
485 }
486 }
487
488 return false;
489}
490
491template <class Impl>
492size_t
493DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
494{
495 return rob->numFreeEntries(tid);
496}
497
498template <class Impl>
499void
500DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
501{
502 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
503
504 TrapEvent *trap = new TrapEvent(this, tid);
505
506 cpu->schedule(trap, curTick() + trapLatency);
507 trapInFlight[tid] = true;
508}
509
510template <class Impl>
511void
512DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
513{
514 assert(!trapInFlight[tid]);
515 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
516
517 tcSquash[tid] = true;
518}
519
520template <class Impl>
521void
522DefaultCommit<Impl>::squashAll(ThreadID tid)
523{
524 // If we want to include the squashing instruction in the squash,
525 // then use one older sequence number.
526 // Hopefully this doesn't mess things up. Basically I want to squash
527 // all instructions of this thread.
528 InstSeqNum squashed_inst = rob->isEmpty() ?
529 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
530
531 // All younger instructions will be squashed. Set the sequence
532 // number as the youngest instruction in the ROB (0 in this case.
533 // Hopefully nothing breaks.)
534 youngestSeqNum[tid] = lastCommitedSeqNum[tid];
535
536 rob->squash(squashed_inst, tid);
537 changedROBNumEntries[tid] = true;
538
539 // Send back the sequence number of the squashed instruction.
540 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
541
542 // Send back the squash signal to tell stages that they should
543 // squash.
544 toIEW->commitInfo[tid].squash = true;
545
546 // Send back the rob squashing signal so other stages know that
547 // the ROB is in the process of squashing.
548 toIEW->commitInfo[tid].robSquashing = true;
549
550 toIEW->commitInfo[tid].mispredictInst = NULL;
551 toIEW->commitInfo[tid].squashInst = NULL;
552
553 toIEW->commitInfo[tid].pc = pc[tid];
554}
555
556template <class Impl>
557void
558DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
559{
560 squashAll(tid);
561
562 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
563
564 thread[tid]->trapPending = false;
565 thread[tid]->inSyscall = false;
566 trapInFlight[tid] = false;
567
568 trapSquash[tid] = false;
569
570 commitStatus[tid] = ROBSquashing;
571 cpu->activityThisCycle();
572}
573
574template <class Impl>
575void
576DefaultCommit<Impl>::squashFromTC(ThreadID tid)
577{
578 squashAll(tid);
579
580 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
581
582 thread[tid]->inSyscall = false;
583 assert(!thread[tid]->trapPending);
584
585 commitStatus[tid] = ROBSquashing;
586 cpu->activityThisCycle();
587
588 tcSquash[tid] = false;
589}
590
591template <class Impl>
592void
593DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst,
594 uint64_t squash_after_seq_num)
595{
596 youngestSeqNum[tid] = squash_after_seq_num;
597
598 rob->squash(squash_after_seq_num, tid);
599 changedROBNumEntries[tid] = true;
600
601 // Send back the sequence number of the squashed instruction.
602 toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num;
603
604 toIEW->commitInfo[tid].squashInst = head_inst;
605 // Send back the squash signal to tell stages that they should squash.
606 toIEW->commitInfo[tid].squash = true;
607
608 // Send back the rob squashing signal so other stages know that
609 // the ROB is in the process of squashing.
610 toIEW->commitInfo[tid].robSquashing = true;
611
612 toIEW->commitInfo[tid].mispredictInst = NULL;
613
614 toIEW->commitInfo[tid].pc = pc[tid];
615 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
616 tid, squash_after_seq_num);
617 commitStatus[tid] = ROBSquashing;
618}
619
620template <class Impl>
621void
622DefaultCommit<Impl>::tick()
623{
624 wroteToTimeBuffer = false;
625 _nextStatus = Inactive;
626
627 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
628 cpu->signalDrained();
629 drainPending = false;
630 return;
631 }
632
633 if (activeThreads->empty())
634 return;
635
636 list<ThreadID>::iterator threads = activeThreads->begin();
637 list<ThreadID>::iterator end = activeThreads->end();
638
639 // Check if any of the threads are done squashing. Change the
640 // status if they are done.
641 while (threads != end) {
642 ThreadID tid = *threads++;
643
644 // Clear the bit saying if the thread has committed stores
645 // this cycle.
646 committedStores[tid] = false;
647
648 if (commitStatus[tid] == ROBSquashing) {
649
650 if (rob->isDoneSquashing(tid)) {
651 commitStatus[tid] = Running;
652 } else {
653 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
654 " insts this cycle.\n", tid);
655 rob->doSquash(tid);
656 toIEW->commitInfo[tid].robSquashing = true;
657 wroteToTimeBuffer = true;
658 }
659 }
660 }
661
662 commit();
663
664 markCompletedInsts();
665
666 threads = activeThreads->begin();
667
668 while (threads != end) {
669 ThreadID tid = *threads++;
670
671 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
672 // The ROB has more instructions it can commit. Its next status
673 // will be active.
674 _nextStatus = Active;
675
676 DynInstPtr inst = rob->readHeadInst(tid);
677
678 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
679 " ROB and ready to commit\n",
680 tid, inst->seqNum, inst->pcState());
681
682 } else if (!rob->isEmpty(tid)) {
683 DynInstPtr inst = rob->readHeadInst(tid);
684
685 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
686 "%s is head of ROB and not ready\n",
687 tid, inst->seqNum, inst->pcState());
688 }
689
690 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
691 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
692 }
693
694
695 if (wroteToTimeBuffer) {
696 DPRINTF(Activity, "Activity This Cycle.\n");
697 cpu->activityThisCycle();
698 }
699
700 updateStatus();
701}
702
703#if FULL_SYSTEM
704template <class Impl>
705void
706DefaultCommit<Impl>::handleInterrupt()
707{
708 // Verify that we still have an interrupt to handle
709 if (!cpu->checkInterrupts(cpu->tcBase(0))) {
710 DPRINTF(Commit, "Pending interrupt is cleared by master before "
711 "it got handled. Restart fetching from the orig path.\n");
712 toIEW->commitInfo[0].clearInterrupt = true;
713 interrupt = NoFault;
714 return;
715 }
716
717 // Wait until all in flight instructions are finished before enterring
718 // the interrupt.
719 if (cpu->instList.empty()) {
720 // Squash or record that I need to squash this cycle if
721 // an interrupt needed to be handled.
722 DPRINTF(Commit, "Interrupt detected.\n");
723
724 // Clear the interrupt now that it's going to be handled
725 toIEW->commitInfo[0].clearInterrupt = true;
726
727 assert(!thread[0]->inSyscall);
728 thread[0]->inSyscall = true;
729
730 // CPU will handle interrupt.
731 cpu->processInterrupts(interrupt);
732
733 thread[0]->inSyscall = false;
734
735 commitStatus[0] = TrapPending;
736
737 // Generate trap squash event.
738 generateTrapEvent(0);
739
740 interrupt = NoFault;
741 } else {
742 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
743 }
744}
745
746template <class Impl>
747void
748DefaultCommit<Impl>::propagateInterrupt()
749{
750 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
751 tcSquash[0])
752 return;
753
754 // Process interrupts if interrupts are enabled, not in PAL
755 // mode, and no other traps or external squashes are currently
756 // pending.
757 // @todo: Allow other threads to handle interrupts.
758
759 // Get any interrupt that happened
760 interrupt = cpu->getInterrupts();
761
762 // Tell fetch that there is an interrupt pending. This
763 // will make fetch wait until it sees a non PAL-mode PC,
764 // at which point it stops fetching instructions.
765 if (interrupt != NoFault)
766 toIEW->commitInfo[0].interruptPending = true;
767}
768
769#endif // FULL_SYSTEM
770
771template <class Impl>
772void
773DefaultCommit<Impl>::commit()
774{
775
776#if FULL_SYSTEM
777 // Check for any interrupt that we've already squashed for and start processing it.
778 if (interrupt != NoFault)
779 handleInterrupt();
780
781 // Check if we have a interrupt and get read to handle it
782 if (cpu->checkInterrupts(cpu->tcBase(0)))
783 propagateInterrupt();
784#endif // FULL_SYSTEM
785
786 ////////////////////////////////////
787 // Check for any possible squashes, handle them first
788 ////////////////////////////////////
789 list<ThreadID>::iterator threads = activeThreads->begin();
790 list<ThreadID>::iterator end = activeThreads->end();
791
792 while (threads != end) {
793 ThreadID tid = *threads++;
794
795 // Not sure which one takes priority. I think if we have
796 // both, that's a bad sign.
797 if (trapSquash[tid] == true) {
798 assert(!tcSquash[tid]);
799 squashFromTrap(tid);
800 } else if (tcSquash[tid] == true) {
801 assert(commitStatus[tid] != TrapPending);
802 squashFromTC(tid);
803 }
804
805 // Squashed sequence number must be older than youngest valid
806 // instruction in the ROB. This prevents squashes from younger
807 // instructions overriding squashes from older instructions.
808 if (fromIEW->squash[tid] &&
809 commitStatus[tid] != TrapPending &&
810 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
811
812 if (fromIEW->mispredictInst[tid]) {
813 DPRINTF(Commit,
814 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
815 tid,
816 fromIEW->mispredictInst[tid]->instAddr(),
817 fromIEW->squashedSeqNum[tid]);
818 } else {
819 DPRINTF(Commit,
820 "[tid:%i]: Squashing due to order violation [sn:%i]\n",
821 tid, fromIEW->squashedSeqNum[tid]);
822 }
823
824 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
825 tid,
826 fromIEW->pc[tid].nextInstAddr());
827
828 commitStatus[tid] = ROBSquashing;
829
830 // If we want to include the squashing instruction in the squash,
831 // then use one older sequence number.
832 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
833
834 if (fromIEW->includeSquashInst[tid] == true) {
835 squashed_inst--;
836 }
837
838 // All younger instructions will be squashed. Set the sequence
839 // number as the youngest instruction in the ROB.
840 youngestSeqNum[tid] = squashed_inst;
841
842 rob->squash(squashed_inst, tid);
843 changedROBNumEntries[tid] = true;
844
845 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
846
847 toIEW->commitInfo[tid].squash = true;
848
849 // Send back the rob squashing signal so other stages know that
850 // the ROB is in the process of squashing.
851 toIEW->commitInfo[tid].robSquashing = true;
852
853 toIEW->commitInfo[tid].mispredictInst =
854 fromIEW->mispredictInst[tid];
855 toIEW->commitInfo[tid].branchTaken =
856 fromIEW->branchTaken[tid];
857 toIEW->commitInfo[tid].squashInst = NULL;
858
859 toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
860
861 if (toIEW->commitInfo[tid].mispredictInst) {
862 ++branchMispredicts;
863 }
864 }
865
866 }
867
868 setNextStatus();
869
870 if (squashCounter != numThreads) {
871 // If we're not currently squashing, then get instructions.
872 getInsts();
873
874 // Try to commit any instructions.
875 commitInsts();
876 }
877
878 //Check for any activity
879 threads = activeThreads->begin();
880
881 while (threads != end) {
882 ThreadID tid = *threads++;
883
884 if (changedROBNumEntries[tid]) {
885 toIEW->commitInfo[tid].usedROB = true;
886 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
887
888 wroteToTimeBuffer = true;
889 changedROBNumEntries[tid] = false;
890 if (rob->isEmpty(tid))
891 checkEmptyROB[tid] = true;
892 }
893
894 // ROB is only considered "empty" for previous stages if: a)
895 // ROB is empty, b) there are no outstanding stores, c) IEW
896 // stage has received any information regarding stores that
897 // committed.
898 // c) is checked by making sure to not consider the ROB empty
899 // on the same cycle as when stores have been committed.
900 // @todo: Make this handle multi-cycle communication between
901 // commit and IEW.
902 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
903 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
904 checkEmptyROB[tid] = false;
905 toIEW->commitInfo[tid].usedROB = true;
906 toIEW->commitInfo[tid].emptyROB = true;
907 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
908 wroteToTimeBuffer = true;
909 }
910
911 }
912}
913
914template <class Impl>
915void
916DefaultCommit<Impl>::commitInsts()
917{
918 ////////////////////////////////////
919 // Handle commit
920 // Note that commit will be handled prior to putting new
921 // instructions in the ROB so that the ROB only tries to commit
922 // instructions it has in this current cycle, and not instructions
923 // it is writing in during this cycle. Can't commit and squash
924 // things at the same time...
925 ////////////////////////////////////
926
927 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
928
929 unsigned num_committed = 0;
930
931 DynInstPtr head_inst;
932
933 // Commit as many instructions as possible until the commit bandwidth
934 // limit is reached, or it becomes impossible to commit any more.
935 while (num_committed < commitWidth) {
936 int commit_thread = getCommittingThread();
937
938 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
939 break;
940
941 head_inst = rob->readHeadInst(commit_thread);
942
943 ThreadID tid = head_inst->threadNumber;
944
945 assert(tid == commit_thread);
946
947 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
948 head_inst->seqNum, tid);
949
950 // If the head instruction is squashed, it is ready to retire
951 // (be removed from the ROB) at any time.
952 if (head_inst->isSquashed()) {
953
954 DPRINTF(Commit, "Retiring squashed instruction from "
955 "ROB.\n");
956
957 rob->retireHead(commit_thread);
958
959 ++commitSquashedInsts;
960
961 // Record that the number of ROB entries has changed.
962 changedROBNumEntries[tid] = true;
963 } else {
964 pc[tid] = head_inst->pcState();
965
966 // Increment the total number of non-speculative instructions
967 // executed.
968 // Hack for now: it really shouldn't happen until after the
969 // commit is deemed to be successful, but this count is needed
970 // for syscalls.
971 thread[tid]->funcExeInst++;
972
973 // Try to commit the head instruction.
974 bool commit_success = commitHead(head_inst, num_committed);
975
976 if (commit_success) {
977 ++num_committed;
978
979 changedROBNumEntries[tid] = true;
980
981 // Set the doneSeqNum to the youngest committed instruction.
982 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
983
984 ++commitCommittedInsts;
985
986 // To match the old model, don't count nops and instruction
987 // prefetches towards the total commit count.
988 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
989 cpu->instDone(tid);
990 }
991
992 // Updates misc. registers.
993 head_inst->updateMiscRegs();
994
995 TheISA::advancePC(pc[tid], head_inst->staticInst);
996
997 // Keep track of the last sequence number commited
998 lastCommitedSeqNum[tid] = head_inst->seqNum;
999
1000 // If this is an instruction that doesn't play nicely with
1001 // others squash everything and restart fetch
1002 if (head_inst->isSquashAfter())
1003 squashAfter(tid, head_inst, head_inst->seqNum);
1004
1005 int count = 0;
1006 Addr oldpc;
1007 // Debug statement. Checks to make sure we're not
1008 // currently updating state while handling PC events.
1009 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
1010 do {
1011 oldpc = pc[tid].instAddr();
1012 cpu->system->pcEventQueue.service(thread[tid]->getTC());
1013 count++;
1014 } while (oldpc != pc[tid].instAddr());
1015 if (count > 1) {
1016 DPRINTF(Commit,
1017 "PC skip function event, stopping commit\n");
1018 break;
1019 }
1020 } else {
1021 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1022 "[tid:%i] [sn:%i].\n",
1023 head_inst->pcState(), tid ,head_inst->seqNum);
1024 break;
1025 }
1026 }
1027 }
1028
1029 DPRINTF(CommitRate, "%i\n", num_committed);
1030 numCommittedDist.sample(num_committed);
1031
1032 if (num_committed == commitWidth) {
1033 commitEligibleSamples++;
1034 }
1035}
1036
1037template <class Impl>
1038bool
1039DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1040{
1041 assert(head_inst);
1042
1043 ThreadID tid = head_inst->threadNumber;
1044
1045 // If the instruction is not executed yet, then it will need extra
1046 // handling. Signal backwards that it should be executed.
1047 if (!head_inst->isExecuted()) {
1048 // Keep this number correct. We have not yet actually executed
1049 // and committed this instruction.
1050 thread[tid]->funcExeInst--;
1051
1052 if (head_inst->isNonSpeculative() ||
1053 head_inst->isStoreConditional() ||
1054 head_inst->isMemBarrier() ||
1055 head_inst->isWriteBarrier()) {
1056
1057 DPRINTF(Commit, "Encountered a barrier or non-speculative "
1058 "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1059 head_inst->seqNum, head_inst->pcState());
1060
1061 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1062 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1063 return false;
1064 }
1065
1066 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1067
1068 // Change the instruction so it won't try to commit again until
1069 // it is executed.
1070 head_inst->clearCanCommit();
1071
1072 ++commitNonSpecStalls;
1073
1074 return false;
1075 } else if (head_inst->isLoad()) {
1076 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1077 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1078 return false;
1079 }
1080
1081 assert(head_inst->uncacheable());
1082 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
1083 head_inst->seqNum, head_inst->pcState());
1084
1085 // Send back the non-speculative instruction's sequence
1086 // number. Tell the lsq to re-execute the load.
1087 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1088 toIEW->commitInfo[tid].uncached = true;
1089 toIEW->commitInfo[tid].uncachedLoad = head_inst;
1090
1091 head_inst->clearCanCommit();
1092
1093 return false;
1094 } else {
1095 panic("Trying to commit un-executed instruction "
1096 "of unknown type!\n");
1097 }
1098 }
1099
1100 if (head_inst->isThreadSync()) {
1101 // Not handled for now.
1102 panic("Thread sync instructions are not handled yet.\n");
1103 }
1104
1105 // Check if the instruction caused a fault. If so, trap.
1106 Fault inst_fault = head_inst->getFault();
1107
1108 // Stores mark themselves as completed.
1109 if (!head_inst->isStore() && inst_fault == NoFault) {
1110 head_inst->setCompleted();
1111 }
1112
1113#if USE_CHECKER
1114 // Use checker prior to updating anything due to traps or PC
1115 // based events.
1116 if (cpu->checker) {
1117 cpu->checker->verify(head_inst);
1118 }
1119#endif
1120
1121 if (inst_fault != NoFault) {
1122 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1123 head_inst->seqNum, head_inst->pcState());
1124
1125 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1126 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1127 return false;
1128 }
1129
1130 head_inst->setCompleted();
1131
1132#if USE_CHECKER
1133 if (cpu->checker && head_inst->isStore()) {
1134 cpu->checker->verify(head_inst);
1135 }
1136#endif
1137
1138 assert(!thread[tid]->inSyscall);
1139
1140 // Mark that we're in state update mode so that the trap's
1141 // execution doesn't generate extra squashes.
1142 thread[tid]->inSyscall = true;
1143
1144 // Execute the trap. Although it's slightly unrealistic in
1145 // terms of timing (as it doesn't wait for the full timing of
1146 // the trap event to complete before updating state), it's
1147 // needed to update the state as soon as possible. This
1148 // prevents external agents from changing any specific state
1149 // that the trap need.
1150 cpu->trap(inst_fault, tid, head_inst->staticInst);
1151
1152 // Exit state update mode to avoid accidental updating.
1153 thread[tid]->inSyscall = false;
1154
1155 commitStatus[tid] = TrapPending;
1156
1157 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1158 head_inst->seqNum);
1159 if (head_inst->traceData) {
1160 if (DTRACE(ExecFaulting)) {
1161 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1162 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1163 head_inst->traceData->dump();
1164 }
1165 delete head_inst->traceData;
1166 head_inst->traceData = NULL;
1167 }
1168
1169 // Generate trap squash event.
1170 generateTrapEvent(tid);
1171 return false;
1172 }
1173
1174 updateComInstStats(head_inst);
1175
1176#if FULL_SYSTEM
1177 if (thread[tid]->profile) {
1178 thread[tid]->profilePC = head_inst->instAddr();
1179 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1180 head_inst->staticInst);
1181
1182 if (node)
1183 thread[tid]->profileNode = node;
1184 }
1185 if (CPA::available()) {
1186 if (head_inst->isControl()) {
1187 ThreadContext *tc = thread[tid]->getTC();
1188 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1189 }
1190 }
1191#endif
|
1194 if (head_inst->traceData) {
1195 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1196 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1197 head_inst->traceData->dump();
1198 delete head_inst->traceData;
1199 head_inst->traceData = NULL;
1200 }
1201
1202 // Update the commit rename map
1203 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1204 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1205 head_inst->renamedDestRegIdx(i));
1206 }
1207
1208 // Finally clear the head ROB entry.
1209 rob->retireHead(tid);
1210
1211#if TRACING_ON
1212 // Print info needed by the pipeline activity viewer.
1213 DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
1214 head_inst->fetchTick,
1215 head_inst->instAddr(),
1216 head_inst->microPC(),
1217 head_inst->seqNum,
1218 head_inst->staticInst->disassemble(head_inst->instAddr()));
1219 DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", head_inst->decodeTick);
1220 DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", head_inst->renameTick);
1221 DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", head_inst->dispatchTick);
1222 DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", head_inst->issueTick);
1223 DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", head_inst->completeTick);
1224 DPRINTFR(O3PipeView, "O3PipeView:retire:%llu\n", curTick());
1225#endif
1226
1227 // If this was a store, record it for this cycle.
1228 if (head_inst->isStore())
1229 committedStores[tid] = true;
1230
1231 // Return true to indicate that we have committed an instruction.
1232 return true;
1233}
1234
1235template <class Impl>
1236void
1237DefaultCommit<Impl>::getInsts()
1238{
1239 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1240
1241 // Read any renamed instructions and place them into the ROB.
1242 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1243
1244 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1245 DynInstPtr inst;
1246
1247 inst = fromRename->insts[inst_num];
1248 ThreadID tid = inst->threadNumber;
1249
1250 if (!inst->isSquashed() &&
1251 commitStatus[tid] != ROBSquashing &&
1252 commitStatus[tid] != TrapPending) {
1253 changedROBNumEntries[tid] = true;
1254
1255 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1256 inst->pcState(), inst->seqNum, tid);
1257
1258 rob->insertInst(inst);
1259
1260 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1261
1262 youngestSeqNum[tid] = inst->seqNum;
1263 } else {
1264 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1265 "squashed, skipping.\n",
1266 inst->pcState(), inst->seqNum, tid);
1267 }
1268 }
1269}
1270
1271template <class Impl>
1272void
1273DefaultCommit<Impl>::skidInsert()
1274{
1275 DPRINTF(Commit, "Attempting to any instructions from rename into "
1276 "skidBuffer.\n");
1277
1278 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1279 DynInstPtr inst = fromRename->insts[inst_num];
1280
1281 if (!inst->isSquashed()) {
1282 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1283 "skidBuffer.\n", inst->pcState(), inst->seqNum,
1284 inst->threadNumber);
1285 skidBuffer.push(inst);
1286 } else {
1287 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1288 "squashed, skipping.\n",
1289 inst->pcState(), inst->seqNum, inst->threadNumber);
1290 }
1291 }
1292}
1293
1294template <class Impl>
1295void
1296DefaultCommit<Impl>::markCompletedInsts()
1297{
1298 // Grab completed insts out of the IEW instruction queue, and mark
1299 // instructions completed within the ROB.
1300 for (int inst_num = 0;
1301 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1302 ++inst_num)
1303 {
1304 if (!fromIEW->insts[inst_num]->isSquashed()) {
1305 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1306 "within ROB.\n",
1307 fromIEW->insts[inst_num]->threadNumber,
1308 fromIEW->insts[inst_num]->pcState(),
1309 fromIEW->insts[inst_num]->seqNum);
1310
1311 // Mark the instruction as ready to commit.
1312 fromIEW->insts[inst_num]->setCanCommit();
1313 }
1314 }
1315}
1316
1317template <class Impl>
1318bool
1319DefaultCommit<Impl>::robDoneSquashing()
1320{
1321 list<ThreadID>::iterator threads = activeThreads->begin();
1322 list<ThreadID>::iterator end = activeThreads->end();
1323
1324 while (threads != end) {
1325 ThreadID tid = *threads++;
1326
1327 if (!rob->isDoneSquashing(tid))
1328 return false;
1329 }
1330
1331 return true;
1332}
1333
1334template <class Impl>
1335void
1336DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1337{
1338 ThreadID tid = inst->threadNumber;
1339
1340 //
1341 // Pick off the software prefetches
1342 //
1343#ifdef TARGET_ALPHA
1344 if (inst->isDataPrefetch()) {
1345 statComSwp[tid]++;
1346 } else {
1347 statComInst[tid]++;
1348 }
1349#else
1350 statComInst[tid]++;
1351#endif
1352
1353 //
1354 // Control Instructions
1355 //
1356 if (inst->isControl())
1357 statComBranches[tid]++;
1358
1359 //
1360 // Memory references
1361 //
1362 if (inst->isMemRef()) {
1363 statComRefs[tid]++;
1364
1365 if (inst->isLoad()) {
1366 statComLoads[tid]++;
1367 }
1368 }
1369
1370 if (inst->isMemBarrier()) {
1371 statComMembars[tid]++;
1372 }
1373
1374 // Integer Instruction
1375 if (inst->isInteger())
1376 statComInteger[tid]++;
1377
1378 // Floating Point Instruction
1379 if (inst->isFloating())
1380 statComFloating[tid]++;
1381
1382 // Function Calls
1383 if (inst->isCall())
1384 statComFunctionCalls[tid]++;
1385
1386}
1387
1388////////////////////////////////////////
1389// //
1390// SMT COMMIT POLICY MAINTAINED HERE //
1391// //
1392////////////////////////////////////////
1393template <class Impl>
1394ThreadID
1395DefaultCommit<Impl>::getCommittingThread()
1396{
1397 if (numThreads > 1) {
1398 switch (commitPolicy) {
1399
1400 case Aggressive:
1401 //If Policy is Aggressive, commit will call
1402 //this function multiple times per
1403 //cycle
1404 return oldestReady();
1405
1406 case RoundRobin:
1407 return roundRobin();
1408
1409 case OldestReady:
1410 return oldestReady();
1411
1412 default:
1413 return InvalidThreadID;
1414 }
1415 } else {
1416 assert(!activeThreads->empty());
1417 ThreadID tid = activeThreads->front();
1418
1419 if (commitStatus[tid] == Running ||
1420 commitStatus[tid] == Idle ||
1421 commitStatus[tid] == FetchTrapPending) {
1422 return tid;
1423 } else {
1424 return InvalidThreadID;
1425 }
1426 }
1427}
1428
1429template<class Impl>
1430ThreadID
1431DefaultCommit<Impl>::roundRobin()
1432{
1433 list<ThreadID>::iterator pri_iter = priority_list.begin();
1434 list<ThreadID>::iterator end = priority_list.end();
1435
1436 while (pri_iter != end) {
1437 ThreadID tid = *pri_iter;
1438
1439 if (commitStatus[tid] == Running ||
1440 commitStatus[tid] == Idle ||
1441 commitStatus[tid] == FetchTrapPending) {
1442
1443 if (rob->isHeadReady(tid)) {
1444 priority_list.erase(pri_iter);
1445 priority_list.push_back(tid);
1446
1447 return tid;
1448 }
1449 }
1450
1451 pri_iter++;
1452 }
1453
1454 return InvalidThreadID;
1455}
1456
1457template<class Impl>
1458ThreadID
1459DefaultCommit<Impl>::oldestReady()
1460{
1461 unsigned oldest = 0;
1462 bool first = true;
1463
1464 list<ThreadID>::iterator threads = activeThreads->begin();
1465 list<ThreadID>::iterator end = activeThreads->end();
1466
1467 while (threads != end) {
1468 ThreadID tid = *threads++;
1469
1470 if (!rob->isEmpty(tid) &&
1471 (commitStatus[tid] == Running ||
1472 commitStatus[tid] == Idle ||
1473 commitStatus[tid] == FetchTrapPending)) {
1474
1475 if (rob->isHeadReady(tid)) {
1476
1477 DynInstPtr head_inst = rob->readHeadInst(tid);
1478
1479 if (first) {
1480 oldest = tid;
1481 first = false;
1482 } else if (head_inst->seqNum < oldest) {
1483 oldest = tid;
1484 }
1485 }
1486 }
1487 }
1488
1489 if (!first) {
1490 return oldest;
1491 } else {
1492 return InvalidThreadID;
1493 }
1494}
| 1194 if (head_inst->traceData) {
1195 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1196 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1197 head_inst->traceData->dump();
1198 delete head_inst->traceData;
1199 head_inst->traceData = NULL;
1200 }
1201
1202 // Update the commit rename map
1203 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1204 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1205 head_inst->renamedDestRegIdx(i));
1206 }
1207
1208 // Finally clear the head ROB entry.
1209 rob->retireHead(tid);
1210
1211#if TRACING_ON
1212 // Print info needed by the pipeline activity viewer.
1213 DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
1214 head_inst->fetchTick,
1215 head_inst->instAddr(),
1216 head_inst->microPC(),
1217 head_inst->seqNum,
1218 head_inst->staticInst->disassemble(head_inst->instAddr()));
1219 DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", head_inst->decodeTick);
1220 DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", head_inst->renameTick);
1221 DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", head_inst->dispatchTick);
1222 DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", head_inst->issueTick);
1223 DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", head_inst->completeTick);
1224 DPRINTFR(O3PipeView, "O3PipeView:retire:%llu\n", curTick());
1225#endif
1226
1227 // If this was a store, record it for this cycle.
1228 if (head_inst->isStore())
1229 committedStores[tid] = true;
1230
1231 // Return true to indicate that we have committed an instruction.
1232 return true;
1233}
1234
1235template <class Impl>
1236void
1237DefaultCommit<Impl>::getInsts()
1238{
1239 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1240
1241 // Read any renamed instructions and place them into the ROB.
1242 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1243
1244 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1245 DynInstPtr inst;
1246
1247 inst = fromRename->insts[inst_num];
1248 ThreadID tid = inst->threadNumber;
1249
1250 if (!inst->isSquashed() &&
1251 commitStatus[tid] != ROBSquashing &&
1252 commitStatus[tid] != TrapPending) {
1253 changedROBNumEntries[tid] = true;
1254
1255 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1256 inst->pcState(), inst->seqNum, tid);
1257
1258 rob->insertInst(inst);
1259
1260 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1261
1262 youngestSeqNum[tid] = inst->seqNum;
1263 } else {
1264 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1265 "squashed, skipping.\n",
1266 inst->pcState(), inst->seqNum, tid);
1267 }
1268 }
1269}
1270
1271template <class Impl>
1272void
1273DefaultCommit<Impl>::skidInsert()
1274{
1275 DPRINTF(Commit, "Attempting to any instructions from rename into "
1276 "skidBuffer.\n");
1277
1278 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1279 DynInstPtr inst = fromRename->insts[inst_num];
1280
1281 if (!inst->isSquashed()) {
1282 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1283 "skidBuffer.\n", inst->pcState(), inst->seqNum,
1284 inst->threadNumber);
1285 skidBuffer.push(inst);
1286 } else {
1287 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1288 "squashed, skipping.\n",
1289 inst->pcState(), inst->seqNum, inst->threadNumber);
1290 }
1291 }
1292}
1293
1294template <class Impl>
1295void
1296DefaultCommit<Impl>::markCompletedInsts()
1297{
1298 // Grab completed insts out of the IEW instruction queue, and mark
1299 // instructions completed within the ROB.
1300 for (int inst_num = 0;
1301 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1302 ++inst_num)
1303 {
1304 if (!fromIEW->insts[inst_num]->isSquashed()) {
1305 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1306 "within ROB.\n",
1307 fromIEW->insts[inst_num]->threadNumber,
1308 fromIEW->insts[inst_num]->pcState(),
1309 fromIEW->insts[inst_num]->seqNum);
1310
1311 // Mark the instruction as ready to commit.
1312 fromIEW->insts[inst_num]->setCanCommit();
1313 }
1314 }
1315}
1316
1317template <class Impl>
1318bool
1319DefaultCommit<Impl>::robDoneSquashing()
1320{
1321 list<ThreadID>::iterator threads = activeThreads->begin();
1322 list<ThreadID>::iterator end = activeThreads->end();
1323
1324 while (threads != end) {
1325 ThreadID tid = *threads++;
1326
1327 if (!rob->isDoneSquashing(tid))
1328 return false;
1329 }
1330
1331 return true;
1332}
1333
1334template <class Impl>
1335void
1336DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1337{
1338 ThreadID tid = inst->threadNumber;
1339
1340 //
1341 // Pick off the software prefetches
1342 //
1343#ifdef TARGET_ALPHA
1344 if (inst->isDataPrefetch()) {
1345 statComSwp[tid]++;
1346 } else {
1347 statComInst[tid]++;
1348 }
1349#else
1350 statComInst[tid]++;
1351#endif
1352
1353 //
1354 // Control Instructions
1355 //
1356 if (inst->isControl())
1357 statComBranches[tid]++;
1358
1359 //
1360 // Memory references
1361 //
1362 if (inst->isMemRef()) {
1363 statComRefs[tid]++;
1364
1365 if (inst->isLoad()) {
1366 statComLoads[tid]++;
1367 }
1368 }
1369
1370 if (inst->isMemBarrier()) {
1371 statComMembars[tid]++;
1372 }
1373
1374 // Integer Instruction
1375 if (inst->isInteger())
1376 statComInteger[tid]++;
1377
1378 // Floating Point Instruction
1379 if (inst->isFloating())
1380 statComFloating[tid]++;
1381
1382 // Function Calls
1383 if (inst->isCall())
1384 statComFunctionCalls[tid]++;
1385
1386}
1387
1388////////////////////////////////////////
1389// //
1390// SMT COMMIT POLICY MAINTAINED HERE //
1391// //
1392////////////////////////////////////////
1393template <class Impl>
1394ThreadID
1395DefaultCommit<Impl>::getCommittingThread()
1396{
1397 if (numThreads > 1) {
1398 switch (commitPolicy) {
1399
1400 case Aggressive:
1401 //If Policy is Aggressive, commit will call
1402 //this function multiple times per
1403 //cycle
1404 return oldestReady();
1405
1406 case RoundRobin:
1407 return roundRobin();
1408
1409 case OldestReady:
1410 return oldestReady();
1411
1412 default:
1413 return InvalidThreadID;
1414 }
1415 } else {
1416 assert(!activeThreads->empty());
1417 ThreadID tid = activeThreads->front();
1418
1419 if (commitStatus[tid] == Running ||
1420 commitStatus[tid] == Idle ||
1421 commitStatus[tid] == FetchTrapPending) {
1422 return tid;
1423 } else {
1424 return InvalidThreadID;
1425 }
1426 }
1427}
1428
1429template<class Impl>
1430ThreadID
1431DefaultCommit<Impl>::roundRobin()
1432{
1433 list<ThreadID>::iterator pri_iter = priority_list.begin();
1434 list<ThreadID>::iterator end = priority_list.end();
1435
1436 while (pri_iter != end) {
1437 ThreadID tid = *pri_iter;
1438
1439 if (commitStatus[tid] == Running ||
1440 commitStatus[tid] == Idle ||
1441 commitStatus[tid] == FetchTrapPending) {
1442
1443 if (rob->isHeadReady(tid)) {
1444 priority_list.erase(pri_iter);
1445 priority_list.push_back(tid);
1446
1447 return tid;
1448 }
1449 }
1450
1451 pri_iter++;
1452 }
1453
1454 return InvalidThreadID;
1455}
1456
1457template<class Impl>
1458ThreadID
1459DefaultCommit<Impl>::oldestReady()
1460{
1461 unsigned oldest = 0;
1462 bool first = true;
1463
1464 list<ThreadID>::iterator threads = activeThreads->begin();
1465 list<ThreadID>::iterator end = activeThreads->end();
1466
1467 while (threads != end) {
1468 ThreadID tid = *threads++;
1469
1470 if (!rob->isEmpty(tid) &&
1471 (commitStatus[tid] == Running ||
1472 commitStatus[tid] == Idle ||
1473 commitStatus[tid] == FetchTrapPending)) {
1474
1475 if (rob->isHeadReady(tid)) {
1476
1477 DynInstPtr head_inst = rob->readHeadInst(tid);
1478
1479 if (first) {
1480 oldest = tid;
1481 first = false;
1482 } else if (head_inst->seqNum < oldest) {
1483 oldest = tid;
1484 }
1485 }
1486 }
1487 }
1488
1489 if (!first) {
1490 return oldest;
1491 } else {
1492 return InvalidThreadID;
1493 }
1494}
|