2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include <algorithm>
33#include <string>
34
35#include "arch/utility.hh"
36#include "base/cp_annotate.hh"
37#include "base/loader/symtab.hh"
38#include "base/timebuf.hh"
39#include "config/full_system.hh"
40#include "config/the_isa.hh"
41#include "config/use_checker.hh"
42#include "cpu/exetrace.hh"
43#include "cpu/o3/commit.hh"
44#include "cpu/o3/thread_state.hh"
45#include "params/DerivO3CPU.hh"
46
47#if USE_CHECKER
48#include "cpu/checker/cpu.hh"
49#endif
50
51using namespace std;
52
53template <class Impl>
54DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
55 ThreadID _tid)
56 : Event(CPU_Tick_Pri), commit(_commit), tid(_tid)
57{
58 this->setFlags(AutoDelete);
59}
60
61template <class Impl>
62void
63DefaultCommit<Impl>::TrapEvent::process()
64{
65 // This will get reset by commit if it was switched out at the
66 // time of this event processing.
67 commit->trapSquash[tid] = true;
68}
69
70template <class Impl>
71const char *
72DefaultCommit<Impl>::TrapEvent::description() const
73{
74 return "Trap";
75}
76
77template <class Impl>
78DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
79 : cpu(_cpu),
80 squashCounter(0),
81 iewToCommitDelay(params->iewToCommitDelay),
82 commitToIEWDelay(params->commitToIEWDelay),
83 renameToROBDelay(params->renameToROBDelay),
84 fetchToCommitDelay(params->commitToFetchDelay),
85 renameWidth(params->renameWidth),
86 commitWidth(params->commitWidth),
87 numThreads(params->numThreads),
88 drainPending(false),
89 switchedOut(false),
90 trapLatency(params->trapLatency)
91{
92 _status = Active;
93 _nextStatus = Inactive;
94 std::string policy = params->smtCommitPolicy;
95
96 //Convert string to lowercase
97 std::transform(policy.begin(), policy.end(), policy.begin(),
98 (int(*)(int)) tolower);
99
100 //Assign commit policy
101 if (policy == "aggressive"){
102 commitPolicy = Aggressive;
103
104 DPRINTF(Commit,"Commit Policy set to Aggressive.");
105 } else if (policy == "roundrobin"){
106 commitPolicy = RoundRobin;
107
108 //Set-Up Priority List
109 for (ThreadID tid = 0; tid < numThreads; tid++) {
110 priority_list.push_back(tid);
111 }
112
113 DPRINTF(Commit,"Commit Policy set to Round Robin.");
114 } else if (policy == "oldestready"){
115 commitPolicy = OldestReady;
116
117 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
118 } else {
119 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
120 "RoundRobin,OldestReady}");
121 }
122
123 for (ThreadID tid = 0; tid < numThreads; tid++) {
124 commitStatus[tid] = Idle;
125 changedROBNumEntries[tid] = false;
126 checkEmptyROB[tid] = false;
127 trapInFlight[tid] = false;
128 committedStores[tid] = false;
129 trapSquash[tid] = false;
130 tcSquash[tid] = false;
131 pc[tid].set(0);
132 }
133#if FULL_SYSTEM
134 interrupt = NoFault;
135#endif
136}
137
138template <class Impl>
139std::string
140DefaultCommit<Impl>::name() const
141{
142 return cpu->name() + ".commit";
143}
144
145template <class Impl>
146void
147DefaultCommit<Impl>::regStats()
148{
149 using namespace Stats;
150 commitCommittedInsts
151 .name(name() + ".commitCommittedInsts")
152 .desc("The number of committed instructions")
153 .prereq(commitCommittedInsts);
154 commitSquashedInsts
155 .name(name() + ".commitSquashedInsts")
156 .desc("The number of squashed insts skipped by commit")
157 .prereq(commitSquashedInsts);
158 commitSquashEvents
159 .name(name() + ".commitSquashEvents")
160 .desc("The number of times commit is told to squash")
161 .prereq(commitSquashEvents);
162 commitNonSpecStalls
163 .name(name() + ".commitNonSpecStalls")
164 .desc("The number of times commit has been forced to stall to "
165 "communicate backwards")
166 .prereq(commitNonSpecStalls);
167 branchMispredicts
168 .name(name() + ".branchMispredicts")
169 .desc("The number of times a branch was mispredicted")
170 .prereq(branchMispredicts);
171 numCommittedDist
172 .init(0,commitWidth,1)
173 .name(name() + ".COM:committed_per_cycle")
174 .desc("Number of insts commited each cycle")
175 .flags(Stats::pdf)
176 ;
177
178 statComInst
179 .init(cpu->numThreads)
180 .name(name() + ".COM:count")
181 .desc("Number of instructions committed")
182 .flags(total)
183 ;
184
185 statComSwp
186 .init(cpu->numThreads)
187 .name(name() + ".COM:swp_count")
188 .desc("Number of s/w prefetches committed")
189 .flags(total)
190 ;
191
192 statComRefs
193 .init(cpu->numThreads)
194 .name(name() + ".COM:refs")
195 .desc("Number of memory references committed")
196 .flags(total)
197 ;
198
199 statComLoads
200 .init(cpu->numThreads)
201 .name(name() + ".COM:loads")
202 .desc("Number of loads committed")
203 .flags(total)
204 ;
205
206 statComMembars
207 .init(cpu->numThreads)
208 .name(name() + ".COM:membars")
209 .desc("Number of memory barriers committed")
210 .flags(total)
211 ;
212
213 statComBranches
214 .init(cpu->numThreads)
215 .name(name() + ".COM:branches")
216 .desc("Number of branches committed")
217 .flags(total)
218 ;
219
220 commitEligible
221 .init(cpu->numThreads)
222 .name(name() + ".COM:bw_limited")
223 .desc("number of insts not committed due to BW limits")
224 .flags(total)
225 ;
226
227 commitEligibleSamples
228 .name(name() + ".COM:bw_lim_events")
229 .desc("number cycles where commit BW limit reached")
230 ;
231}
232
233template <class Impl>
234void
235DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
236{
237 thread = threads;
238}
239
240template <class Impl>
241void
242DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
243{
244 timeBuffer = tb_ptr;
245
246 // Setup wire to send information back to IEW.
247 toIEW = timeBuffer->getWire(0);
248
249 // Setup wire to read data from IEW (for the ROB).
250 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
251}
252
253template <class Impl>
254void
255DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
256{
257 fetchQueue = fq_ptr;
258
259 // Setup wire to get instructions from rename (for the ROB).
260 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
261}
262
263template <class Impl>
264void
265DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
266{
267 renameQueue = rq_ptr;
268
269 // Setup wire to get instructions from rename (for the ROB).
270 fromRename = renameQueue->getWire(-renameToROBDelay);
271}
272
273template <class Impl>
274void
275DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
276{
277 iewQueue = iq_ptr;
278
279 // Setup wire to get instructions from IEW.
280 fromIEW = iewQueue->getWire(-iewToCommitDelay);
281}
282
283template <class Impl>
284void
285DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
286{
287 iewStage = iew_stage;
288}
289
290template<class Impl>
291void
292DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
293{
294 activeThreads = at_ptr;
295}
296
297template <class Impl>
298void
299DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
300{
301 for (ThreadID tid = 0; tid < numThreads; tid++)
302 renameMap[tid] = &rm_ptr[tid];
303}
304
305template <class Impl>
306void
307DefaultCommit<Impl>::setROB(ROB *rob_ptr)
308{
309 rob = rob_ptr;
310}
311
312template <class Impl>
313void
314DefaultCommit<Impl>::initStage()
315{
316 rob->setActiveThreads(activeThreads);
317 rob->resetEntries();
318
319 // Broadcast the number of free entries.
320 for (ThreadID tid = 0; tid < numThreads; tid++) {
321 toIEW->commitInfo[tid].usedROB = true;
322 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
323 toIEW->commitInfo[tid].emptyROB = true;
324 }
325
326 // Commit must broadcast the number of free entries it has at the
327 // start of the simulation, so it starts as active.
328 cpu->activateStage(O3CPU::CommitIdx);
329
330 cpu->activityThisCycle();
331 trapLatency = cpu->ticks(trapLatency);
332}
333
334template <class Impl>
335bool
336DefaultCommit<Impl>::drain()
337{
338 drainPending = true;
339
340 return false;
341}
342
343template <class Impl>
344void
345DefaultCommit<Impl>::switchOut()
346{
347 switchedOut = true;
348 drainPending = false;
349 rob->switchOut();
350}
351
352template <class Impl>
353void
354DefaultCommit<Impl>::resume()
355{
356 drainPending = false;
357}
358
359template <class Impl>
360void
361DefaultCommit<Impl>::takeOverFrom()
362{
363 switchedOut = false;
364 _status = Active;
365 _nextStatus = Inactive;
366 for (ThreadID tid = 0; tid < numThreads; tid++) {
367 commitStatus[tid] = Idle;
368 changedROBNumEntries[tid] = false;
369 trapSquash[tid] = false;
370 tcSquash[tid] = false;
371 }
372 squashCounter = 0;
373 rob->takeOverFrom();
374}
375
376template <class Impl>
377void
378DefaultCommit<Impl>::updateStatus()
379{
380 // reset ROB changed variable
381 list<ThreadID>::iterator threads = activeThreads->begin();
382 list<ThreadID>::iterator end = activeThreads->end();
383
384 while (threads != end) {
385 ThreadID tid = *threads++;
386
387 changedROBNumEntries[tid] = false;
388
389 // Also check if any of the threads has a trap pending
390 if (commitStatus[tid] == TrapPending ||
391 commitStatus[tid] == FetchTrapPending) {
392 _nextStatus = Active;
393 }
394 }
395
396 if (_nextStatus == Inactive && _status == Active) {
397 DPRINTF(Activity, "Deactivating stage.\n");
398 cpu->deactivateStage(O3CPU::CommitIdx);
399 } else if (_nextStatus == Active && _status == Inactive) {
400 DPRINTF(Activity, "Activating stage.\n");
401 cpu->activateStage(O3CPU::CommitIdx);
402 }
403
404 _status = _nextStatus;
405}
406
407template <class Impl>
408void
409DefaultCommit<Impl>::setNextStatus()
410{
411 int squashes = 0;
412
413 list<ThreadID>::iterator threads = activeThreads->begin();
414 list<ThreadID>::iterator end = activeThreads->end();
415
416 while (threads != end) {
417 ThreadID tid = *threads++;
418
419 if (commitStatus[tid] == ROBSquashing) {
420 squashes++;
421 }
422 }
423
424 squashCounter = squashes;
425
426 // If commit is currently squashing, then it will have activity for the
427 // next cycle. Set its next status as active.
428 if (squashCounter) {
429 _nextStatus = Active;
430 }
431}
432
433template <class Impl>
434bool
435DefaultCommit<Impl>::changedROBEntries()
436{
437 list<ThreadID>::iterator threads = activeThreads->begin();
438 list<ThreadID>::iterator end = activeThreads->end();
439
440 while (threads != end) {
441 ThreadID tid = *threads++;
442
443 if (changedROBNumEntries[tid]) {
444 return true;
445 }
446 }
447
448 return false;
449}
450
451template <class Impl>
452size_t
453DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
454{
455 return rob->numFreeEntries(tid);
456}
457
458template <class Impl>
459void
460DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
461{
462 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
463
464 TrapEvent *trap = new TrapEvent(this, tid);
465
466 cpu->schedule(trap, curTick + trapLatency);
467 trapInFlight[tid] = true;
468}
469
470template <class Impl>
471void
472DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
473{
474 assert(!trapInFlight[tid]);
475 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
476
477 tcSquash[tid] = true;
478}
479
480template <class Impl>
481void
482DefaultCommit<Impl>::squashAll(ThreadID tid)
483{
484 // If we want to include the squashing instruction in the squash,
485 // then use one older sequence number.
486 // Hopefully this doesn't mess things up. Basically I want to squash
487 // all instructions of this thread.
488 InstSeqNum squashed_inst = rob->isEmpty() ?
489 0 : rob->readHeadInst(tid)->seqNum - 1;
490
491 // All younger instructions will be squashed. Set the sequence
492 // number as the youngest instruction in the ROB (0 in this case.
493 // Hopefully nothing breaks.)
494 youngestSeqNum[tid] = 0;
495
496 rob->squash(squashed_inst, tid);
497 changedROBNumEntries[tid] = true;
498
499 // Send back the sequence number of the squashed instruction.
500 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
501
502 // Send back the squash signal to tell stages that they should
503 // squash.
504 toIEW->commitInfo[tid].squash = true;
505
506 // Send back the rob squashing signal so other stages know that
507 // the ROB is in the process of squashing.
508 toIEW->commitInfo[tid].robSquashing = true;
509
510 toIEW->commitInfo[tid].branchMispredict = false;
511
512 toIEW->commitInfo[tid].pc = pc[tid];
513}
514
515template <class Impl>
516void
517DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
518{
519 squashAll(tid);
520
521 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
522
523 thread[tid]->trapPending = false;
524 thread[tid]->inSyscall = false;
525 trapInFlight[tid] = false;
526
527 trapSquash[tid] = false;
528
529 commitStatus[tid] = ROBSquashing;
530 cpu->activityThisCycle();
531}
532
533template <class Impl>
534void
535DefaultCommit<Impl>::squashFromTC(ThreadID tid)
536{
537 squashAll(tid);
538
539 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
540
541 thread[tid]->inSyscall = false;
542 assert(!thread[tid]->trapPending);
543
544 commitStatus[tid] = ROBSquashing;
545 cpu->activityThisCycle();
546
547 tcSquash[tid] = false;
548}
549
550template <class Impl>
551void
552DefaultCommit<Impl>::tick()
553{
554 wroteToTimeBuffer = false;
555 _nextStatus = Inactive;
556
557 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
558 cpu->signalDrained();
559 drainPending = false;
560 return;
561 }
562
563 if (activeThreads->empty())
564 return;
565
566 list<ThreadID>::iterator threads = activeThreads->begin();
567 list<ThreadID>::iterator end = activeThreads->end();
568
569 // Check if any of the threads are done squashing. Change the
570 // status if they are done.
571 while (threads != end) {
572 ThreadID tid = *threads++;
573
574 // Clear the bit saying if the thread has committed stores
575 // this cycle.
576 committedStores[tid] = false;
577
578 if (commitStatus[tid] == ROBSquashing) {
579
580 if (rob->isDoneSquashing(tid)) {
581 commitStatus[tid] = Running;
582 } else {
583 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
584 " insts this cycle.\n", tid);
585 rob->doSquash(tid);
586 toIEW->commitInfo[tid].robSquashing = true;
587 wroteToTimeBuffer = true;
588 }
589 }
590 }
591
592 commit();
593
594 markCompletedInsts();
595
596 threads = activeThreads->begin();
597
598 while (threads != end) {
599 ThreadID tid = *threads++;
600
601 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
602 // The ROB has more instructions it can commit. Its next status
603 // will be active.
604 _nextStatus = Active;
605
606 DynInstPtr inst = rob->readHeadInst(tid);
607
608 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
609 " ROB and ready to commit\n",
610 tid, inst->seqNum, inst->pcState());
611
612 } else if (!rob->isEmpty(tid)) {
613 DynInstPtr inst = rob->readHeadInst(tid);
614
615 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
616 "%s is head of ROB and not ready\n",
617 tid, inst->seqNum, inst->pcState());
618 }
619
620 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
621 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
622 }
623
624
625 if (wroteToTimeBuffer) {
626 DPRINTF(Activity, "Activity This Cycle.\n");
627 cpu->activityThisCycle();
628 }
629
630 updateStatus();
631}
632
633#if FULL_SYSTEM
634template <class Impl>
635void
636DefaultCommit<Impl>::handleInterrupt()
637{
638 if (interrupt != NoFault) {
639 // Wait until the ROB is empty and all stores have drained in
640 // order to enter the interrupt.
641 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
642 // Squash or record that I need to squash this cycle if
643 // an interrupt needed to be handled.
644 DPRINTF(Commit, "Interrupt detected.\n");
645
646 // Clear the interrupt now that it's going to be handled
647 toIEW->commitInfo[0].clearInterrupt = true;
648
649 assert(!thread[0]->inSyscall);
650 thread[0]->inSyscall = true;
651
652 // CPU will handle interrupt.
653 cpu->processInterrupts(interrupt);
654
655 thread[0]->inSyscall = false;
656
657 commitStatus[0] = TrapPending;
658
659 // Generate trap squash event.
660 generateTrapEvent(0);
661
662 interrupt = NoFault;
663 } else {
664 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
665 }
666 } else if (commitStatus[0] != TrapPending &&
667 cpu->checkInterrupts(cpu->tcBase(0)) &&
668 !trapSquash[0] &&
669 !tcSquash[0]) {
670 // Process interrupts if interrupts are enabled, not in PAL
671 // mode, and no other traps or external squashes are currently
672 // pending.
673 // @todo: Allow other threads to handle interrupts.
674
675 // Get any interrupt that happened
676 interrupt = cpu->getInterrupts();
677
678 if (interrupt != NoFault) {
679 // Tell fetch that there is an interrupt pending. This
680 // will make fetch wait until it sees a non PAL-mode PC,
681 // at which point it stops fetching instructions.
682 toIEW->commitInfo[0].interruptPending = true;
683 }
684 }
685}
686#endif // FULL_SYSTEM
687
688template <class Impl>
689void
690DefaultCommit<Impl>::commit()
691{
692
693#if FULL_SYSTEM
694 // Check for any interrupt, and start processing it. Or if we
695 // have an outstanding interrupt and are at a point when it is
696 // valid to take an interrupt, process it.
697 if (cpu->checkInterrupts(cpu->tcBase(0))) {
698 handleInterrupt();
699 }
700#endif // FULL_SYSTEM
701
702 ////////////////////////////////////
703 // Check for any possible squashes, handle them first
704 ////////////////////////////////////
705 list<ThreadID>::iterator threads = activeThreads->begin();
706 list<ThreadID>::iterator end = activeThreads->end();
707
708 while (threads != end) {
709 ThreadID tid = *threads++;
710
711 // Not sure which one takes priority. I think if we have
712 // both, that's a bad sign.
713 if (trapSquash[tid] == true) {
714 assert(!tcSquash[tid]);
715 squashFromTrap(tid);
716 } else if (tcSquash[tid] == true) {
717 assert(commitStatus[tid] != TrapPending);
718 squashFromTC(tid);
719 }
720
721 // Squashed sequence number must be older than youngest valid
722 // instruction in the ROB. This prevents squashes from younger
723 // instructions overriding squashes from older instructions.
724 if (fromIEW->squash[tid] &&
725 commitStatus[tid] != TrapPending &&
726 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
727
728 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
729 tid,
730 fromIEW->mispredPC[tid],
731 fromIEW->squashedSeqNum[tid]);
732
733 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
734 tid,
735 fromIEW->pc[tid].nextInstAddr());
736
737 commitStatus[tid] = ROBSquashing;
738
739 // If we want to include the squashing instruction in the squash,
740 // then use one older sequence number.
741 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
742
743 if (fromIEW->includeSquashInst[tid] == true) {
744 squashed_inst--;
745 }
746
747 // All younger instructions will be squashed. Set the sequence
748 // number as the youngest instruction in the ROB.
749 youngestSeqNum[tid] = squashed_inst;
750
751 rob->squash(squashed_inst, tid);
752 changedROBNumEntries[tid] = true;
753
754 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
755
756 toIEW->commitInfo[tid].squash = true;
757
758 // Send back the rob squashing signal so other stages know that
759 // the ROB is in the process of squashing.
760 toIEW->commitInfo[tid].robSquashing = true;
761
762 toIEW->commitInfo[tid].branchMispredict =
763 fromIEW->branchMispredict[tid];
764
765 toIEW->commitInfo[tid].branchTaken =
766 fromIEW->branchTaken[tid];
767
768 toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
769
770 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
771
772 if (toIEW->commitInfo[tid].branchMispredict) {
773 ++branchMispredicts;
774 }
775 }
776
777 }
778
779 setNextStatus();
780
781 if (squashCounter != numThreads) {
782 // If we're not currently squashing, then get instructions.
783 getInsts();
784
785 // Try to commit any instructions.
786 commitInsts();
787 }
788
789 //Check for any activity
790 threads = activeThreads->begin();
791
792 while (threads != end) {
793 ThreadID tid = *threads++;
794
795 if (changedROBNumEntries[tid]) {
796 toIEW->commitInfo[tid].usedROB = true;
797 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
798
799 wroteToTimeBuffer = true;
800 changedROBNumEntries[tid] = false;
801 if (rob->isEmpty(tid))
802 checkEmptyROB[tid] = true;
803 }
804
805 // ROB is only considered "empty" for previous stages if: a)
806 // ROB is empty, b) there are no outstanding stores, c) IEW
807 // stage has received any information regarding stores that
808 // committed.
809 // c) is checked by making sure to not consider the ROB empty
810 // on the same cycle as when stores have been committed.
811 // @todo: Make this handle multi-cycle communication between
812 // commit and IEW.
813 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
814 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
815 checkEmptyROB[tid] = false;
816 toIEW->commitInfo[tid].usedROB = true;
817 toIEW->commitInfo[tid].emptyROB = true;
818 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
819 wroteToTimeBuffer = true;
820 }
821
822 }
823}
824
825template <class Impl>
826void
827DefaultCommit<Impl>::commitInsts()
828{
829 ////////////////////////////////////
830 // Handle commit
831 // Note that commit will be handled prior to putting new
832 // instructions in the ROB so that the ROB only tries to commit
833 // instructions it has in this current cycle, and not instructions
834 // it is writing in during this cycle. Can't commit and squash
835 // things at the same time...
836 ////////////////////////////////////
837
838 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
839
840 unsigned num_committed = 0;
841
842 DynInstPtr head_inst;
843
844 // Commit as many instructions as possible until the commit bandwidth
845 // limit is reached, or it becomes impossible to commit any more.
846 while (num_committed < commitWidth) {
847 int commit_thread = getCommittingThread();
848
849 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
850 break;
851
852 head_inst = rob->readHeadInst(commit_thread);
853
854 ThreadID tid = head_inst->threadNumber;
855
856 assert(tid == commit_thread);
857
858 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
859 head_inst->seqNum, tid);
860
861 // If the head instruction is squashed, it is ready to retire
862 // (be removed from the ROB) at any time.
863 if (head_inst->isSquashed()) {
864
865 DPRINTF(Commit, "Retiring squashed instruction from "
866 "ROB.\n");
867
868 rob->retireHead(commit_thread);
869
870 ++commitSquashedInsts;
871
872 // Record that the number of ROB entries has changed.
873 changedROBNumEntries[tid] = true;
874 } else {
875 pc[tid] = head_inst->pcState();
876
877 // Increment the total number of non-speculative instructions
878 // executed.
879 // Hack for now: it really shouldn't happen until after the
880 // commit is deemed to be successful, but this count is needed
881 // for syscalls.
882 thread[tid]->funcExeInst++;
883
884 // Try to commit the head instruction.
885 bool commit_success = commitHead(head_inst, num_committed);
886
887 if (commit_success) {
888 ++num_committed;
889
890 changedROBNumEntries[tid] = true;
891
892 // Set the doneSeqNum to the youngest committed instruction.
893 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
894
895 ++commitCommittedInsts;
896
897 // To match the old model, don't count nops and instruction
898 // prefetches towards the total commit count.
899 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
900 cpu->instDone(tid);
901 }
902
| 14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#include <algorithm>
45#include <string>
46
47#include "arch/utility.hh"
48#include "base/cp_annotate.hh"
49#include "base/loader/symtab.hh"
50#include "base/timebuf.hh"
51#include "config/full_system.hh"
52#include "config/the_isa.hh"
53#include "config/use_checker.hh"
54#include "cpu/exetrace.hh"
55#include "cpu/o3/commit.hh"
56#include "cpu/o3/thread_state.hh"
57#include "params/DerivO3CPU.hh"
58
59#if USE_CHECKER
60#include "cpu/checker/cpu.hh"
61#endif
62
63using namespace std;
64
65template <class Impl>
66DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
67 ThreadID _tid)
68 : Event(CPU_Tick_Pri), commit(_commit), tid(_tid)
69{
70 this->setFlags(AutoDelete);
71}
72
73template <class Impl>
74void
75DefaultCommit<Impl>::TrapEvent::process()
76{
77 // This will get reset by commit if it was switched out at the
78 // time of this event processing.
79 commit->trapSquash[tid] = true;
80}
81
82template <class Impl>
83const char *
84DefaultCommit<Impl>::TrapEvent::description() const
85{
86 return "Trap";
87}
88
89template <class Impl>
90DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
91 : cpu(_cpu),
92 squashCounter(0),
93 iewToCommitDelay(params->iewToCommitDelay),
94 commitToIEWDelay(params->commitToIEWDelay),
95 renameToROBDelay(params->renameToROBDelay),
96 fetchToCommitDelay(params->commitToFetchDelay),
97 renameWidth(params->renameWidth),
98 commitWidth(params->commitWidth),
99 numThreads(params->numThreads),
100 drainPending(false),
101 switchedOut(false),
102 trapLatency(params->trapLatency)
103{
104 _status = Active;
105 _nextStatus = Inactive;
106 std::string policy = params->smtCommitPolicy;
107
108 //Convert string to lowercase
109 std::transform(policy.begin(), policy.end(), policy.begin(),
110 (int(*)(int)) tolower);
111
112 //Assign commit policy
113 if (policy == "aggressive"){
114 commitPolicy = Aggressive;
115
116 DPRINTF(Commit,"Commit Policy set to Aggressive.");
117 } else if (policy == "roundrobin"){
118 commitPolicy = RoundRobin;
119
120 //Set-Up Priority List
121 for (ThreadID tid = 0; tid < numThreads; tid++) {
122 priority_list.push_back(tid);
123 }
124
125 DPRINTF(Commit,"Commit Policy set to Round Robin.");
126 } else if (policy == "oldestready"){
127 commitPolicy = OldestReady;
128
129 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
130 } else {
131 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
132 "RoundRobin,OldestReady}");
133 }
134
135 for (ThreadID tid = 0; tid < numThreads; tid++) {
136 commitStatus[tid] = Idle;
137 changedROBNumEntries[tid] = false;
138 checkEmptyROB[tid] = false;
139 trapInFlight[tid] = false;
140 committedStores[tid] = false;
141 trapSquash[tid] = false;
142 tcSquash[tid] = false;
143 pc[tid].set(0);
144 }
145#if FULL_SYSTEM
146 interrupt = NoFault;
147#endif
148}
149
150template <class Impl>
151std::string
152DefaultCommit<Impl>::name() const
153{
154 return cpu->name() + ".commit";
155}
156
157template <class Impl>
158void
159DefaultCommit<Impl>::regStats()
160{
161 using namespace Stats;
162 commitCommittedInsts
163 .name(name() + ".commitCommittedInsts")
164 .desc("The number of committed instructions")
165 .prereq(commitCommittedInsts);
166 commitSquashedInsts
167 .name(name() + ".commitSquashedInsts")
168 .desc("The number of squashed insts skipped by commit")
169 .prereq(commitSquashedInsts);
170 commitSquashEvents
171 .name(name() + ".commitSquashEvents")
172 .desc("The number of times commit is told to squash")
173 .prereq(commitSquashEvents);
174 commitNonSpecStalls
175 .name(name() + ".commitNonSpecStalls")
176 .desc("The number of times commit has been forced to stall to "
177 "communicate backwards")
178 .prereq(commitNonSpecStalls);
179 branchMispredicts
180 .name(name() + ".branchMispredicts")
181 .desc("The number of times a branch was mispredicted")
182 .prereq(branchMispredicts);
183 numCommittedDist
184 .init(0,commitWidth,1)
185 .name(name() + ".COM:committed_per_cycle")
186 .desc("Number of insts commited each cycle")
187 .flags(Stats::pdf)
188 ;
189
190 statComInst
191 .init(cpu->numThreads)
192 .name(name() + ".COM:count")
193 .desc("Number of instructions committed")
194 .flags(total)
195 ;
196
197 statComSwp
198 .init(cpu->numThreads)
199 .name(name() + ".COM:swp_count")
200 .desc("Number of s/w prefetches committed")
201 .flags(total)
202 ;
203
204 statComRefs
205 .init(cpu->numThreads)
206 .name(name() + ".COM:refs")
207 .desc("Number of memory references committed")
208 .flags(total)
209 ;
210
211 statComLoads
212 .init(cpu->numThreads)
213 .name(name() + ".COM:loads")
214 .desc("Number of loads committed")
215 .flags(total)
216 ;
217
218 statComMembars
219 .init(cpu->numThreads)
220 .name(name() + ".COM:membars")
221 .desc("Number of memory barriers committed")
222 .flags(total)
223 ;
224
225 statComBranches
226 .init(cpu->numThreads)
227 .name(name() + ".COM:branches")
228 .desc("Number of branches committed")
229 .flags(total)
230 ;
231
232 commitEligible
233 .init(cpu->numThreads)
234 .name(name() + ".COM:bw_limited")
235 .desc("number of insts not committed due to BW limits")
236 .flags(total)
237 ;
238
239 commitEligibleSamples
240 .name(name() + ".COM:bw_lim_events")
241 .desc("number cycles where commit BW limit reached")
242 ;
243}
244
245template <class Impl>
246void
247DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
248{
249 thread = threads;
250}
251
252template <class Impl>
253void
254DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
255{
256 timeBuffer = tb_ptr;
257
258 // Setup wire to send information back to IEW.
259 toIEW = timeBuffer->getWire(0);
260
261 // Setup wire to read data from IEW (for the ROB).
262 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
263}
264
265template <class Impl>
266void
267DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
268{
269 fetchQueue = fq_ptr;
270
271 // Setup wire to get instructions from rename (for the ROB).
272 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
273}
274
275template <class Impl>
276void
277DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
278{
279 renameQueue = rq_ptr;
280
281 // Setup wire to get instructions from rename (for the ROB).
282 fromRename = renameQueue->getWire(-renameToROBDelay);
283}
284
285template <class Impl>
286void
287DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
288{
289 iewQueue = iq_ptr;
290
291 // Setup wire to get instructions from IEW.
292 fromIEW = iewQueue->getWire(-iewToCommitDelay);
293}
294
295template <class Impl>
296void
297DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
298{
299 iewStage = iew_stage;
300}
301
302template<class Impl>
303void
304DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
305{
306 activeThreads = at_ptr;
307}
308
309template <class Impl>
310void
311DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
312{
313 for (ThreadID tid = 0; tid < numThreads; tid++)
314 renameMap[tid] = &rm_ptr[tid];
315}
316
317template <class Impl>
318void
319DefaultCommit<Impl>::setROB(ROB *rob_ptr)
320{
321 rob = rob_ptr;
322}
323
324template <class Impl>
325void
326DefaultCommit<Impl>::initStage()
327{
328 rob->setActiveThreads(activeThreads);
329 rob->resetEntries();
330
331 // Broadcast the number of free entries.
332 for (ThreadID tid = 0; tid < numThreads; tid++) {
333 toIEW->commitInfo[tid].usedROB = true;
334 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
335 toIEW->commitInfo[tid].emptyROB = true;
336 }
337
338 // Commit must broadcast the number of free entries it has at the
339 // start of the simulation, so it starts as active.
340 cpu->activateStage(O3CPU::CommitIdx);
341
342 cpu->activityThisCycle();
343 trapLatency = cpu->ticks(trapLatency);
344}
345
346template <class Impl>
347bool
348DefaultCommit<Impl>::drain()
349{
350 drainPending = true;
351
352 return false;
353}
354
355template <class Impl>
356void
357DefaultCommit<Impl>::switchOut()
358{
359 switchedOut = true;
360 drainPending = false;
361 rob->switchOut();
362}
363
364template <class Impl>
365void
366DefaultCommit<Impl>::resume()
367{
368 drainPending = false;
369}
370
371template <class Impl>
372void
373DefaultCommit<Impl>::takeOverFrom()
374{
375 switchedOut = false;
376 _status = Active;
377 _nextStatus = Inactive;
378 for (ThreadID tid = 0; tid < numThreads; tid++) {
379 commitStatus[tid] = Idle;
380 changedROBNumEntries[tid] = false;
381 trapSquash[tid] = false;
382 tcSquash[tid] = false;
383 }
384 squashCounter = 0;
385 rob->takeOverFrom();
386}
387
388template <class Impl>
389void
390DefaultCommit<Impl>::updateStatus()
391{
392 // reset ROB changed variable
393 list<ThreadID>::iterator threads = activeThreads->begin();
394 list<ThreadID>::iterator end = activeThreads->end();
395
396 while (threads != end) {
397 ThreadID tid = *threads++;
398
399 changedROBNumEntries[tid] = false;
400
401 // Also check if any of the threads has a trap pending
402 if (commitStatus[tid] == TrapPending ||
403 commitStatus[tid] == FetchTrapPending) {
404 _nextStatus = Active;
405 }
406 }
407
408 if (_nextStatus == Inactive && _status == Active) {
409 DPRINTF(Activity, "Deactivating stage.\n");
410 cpu->deactivateStage(O3CPU::CommitIdx);
411 } else if (_nextStatus == Active && _status == Inactive) {
412 DPRINTF(Activity, "Activating stage.\n");
413 cpu->activateStage(O3CPU::CommitIdx);
414 }
415
416 _status = _nextStatus;
417}
418
419template <class Impl>
420void
421DefaultCommit<Impl>::setNextStatus()
422{
423 int squashes = 0;
424
425 list<ThreadID>::iterator threads = activeThreads->begin();
426 list<ThreadID>::iterator end = activeThreads->end();
427
428 while (threads != end) {
429 ThreadID tid = *threads++;
430
431 if (commitStatus[tid] == ROBSquashing) {
432 squashes++;
433 }
434 }
435
436 squashCounter = squashes;
437
438 // If commit is currently squashing, then it will have activity for the
439 // next cycle. Set its next status as active.
440 if (squashCounter) {
441 _nextStatus = Active;
442 }
443}
444
445template <class Impl>
446bool
447DefaultCommit<Impl>::changedROBEntries()
448{
449 list<ThreadID>::iterator threads = activeThreads->begin();
450 list<ThreadID>::iterator end = activeThreads->end();
451
452 while (threads != end) {
453 ThreadID tid = *threads++;
454
455 if (changedROBNumEntries[tid]) {
456 return true;
457 }
458 }
459
460 return false;
461}
462
463template <class Impl>
464size_t
465DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
466{
467 return rob->numFreeEntries(tid);
468}
469
470template <class Impl>
471void
472DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
473{
474 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
475
476 TrapEvent *trap = new TrapEvent(this, tid);
477
478 cpu->schedule(trap, curTick + trapLatency);
479 trapInFlight[tid] = true;
480}
481
482template <class Impl>
483void
484DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
485{
486 assert(!trapInFlight[tid]);
487 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
488
489 tcSquash[tid] = true;
490}
491
492template <class Impl>
493void
494DefaultCommit<Impl>::squashAll(ThreadID tid)
495{
496 // If we want to include the squashing instruction in the squash,
497 // then use one older sequence number.
498 // Hopefully this doesn't mess things up. Basically I want to squash
499 // all instructions of this thread.
500 InstSeqNum squashed_inst = rob->isEmpty() ?
501 0 : rob->readHeadInst(tid)->seqNum - 1;
502
503 // All younger instructions will be squashed. Set the sequence
504 // number as the youngest instruction in the ROB (0 in this case.
505 // Hopefully nothing breaks.)
506 youngestSeqNum[tid] = 0;
507
508 rob->squash(squashed_inst, tid);
509 changedROBNumEntries[tid] = true;
510
511 // Send back the sequence number of the squashed instruction.
512 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
513
514 // Send back the squash signal to tell stages that they should
515 // squash.
516 toIEW->commitInfo[tid].squash = true;
517
518 // Send back the rob squashing signal so other stages know that
519 // the ROB is in the process of squashing.
520 toIEW->commitInfo[tid].robSquashing = true;
521
522 toIEW->commitInfo[tid].branchMispredict = false;
523
524 toIEW->commitInfo[tid].pc = pc[tid];
525}
526
527template <class Impl>
528void
529DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
530{
531 squashAll(tid);
532
533 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
534
535 thread[tid]->trapPending = false;
536 thread[tid]->inSyscall = false;
537 trapInFlight[tid] = false;
538
539 trapSquash[tid] = false;
540
541 commitStatus[tid] = ROBSquashing;
542 cpu->activityThisCycle();
543}
544
545template <class Impl>
546void
547DefaultCommit<Impl>::squashFromTC(ThreadID tid)
548{
549 squashAll(tid);
550
551 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
552
553 thread[tid]->inSyscall = false;
554 assert(!thread[tid]->trapPending);
555
556 commitStatus[tid] = ROBSquashing;
557 cpu->activityThisCycle();
558
559 tcSquash[tid] = false;
560}
561
562template <class Impl>
563void
564DefaultCommit<Impl>::tick()
565{
566 wroteToTimeBuffer = false;
567 _nextStatus = Inactive;
568
569 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
570 cpu->signalDrained();
571 drainPending = false;
572 return;
573 }
574
575 if (activeThreads->empty())
576 return;
577
578 list<ThreadID>::iterator threads = activeThreads->begin();
579 list<ThreadID>::iterator end = activeThreads->end();
580
581 // Check if any of the threads are done squashing. Change the
582 // status if they are done.
583 while (threads != end) {
584 ThreadID tid = *threads++;
585
586 // Clear the bit saying if the thread has committed stores
587 // this cycle.
588 committedStores[tid] = false;
589
590 if (commitStatus[tid] == ROBSquashing) {
591
592 if (rob->isDoneSquashing(tid)) {
593 commitStatus[tid] = Running;
594 } else {
595 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
596 " insts this cycle.\n", tid);
597 rob->doSquash(tid);
598 toIEW->commitInfo[tid].robSquashing = true;
599 wroteToTimeBuffer = true;
600 }
601 }
602 }
603
604 commit();
605
606 markCompletedInsts();
607
608 threads = activeThreads->begin();
609
610 while (threads != end) {
611 ThreadID tid = *threads++;
612
613 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
614 // The ROB has more instructions it can commit. Its next status
615 // will be active.
616 _nextStatus = Active;
617
618 DynInstPtr inst = rob->readHeadInst(tid);
619
620 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
621 " ROB and ready to commit\n",
622 tid, inst->seqNum, inst->pcState());
623
624 } else if (!rob->isEmpty(tid)) {
625 DynInstPtr inst = rob->readHeadInst(tid);
626
627 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
628 "%s is head of ROB and not ready\n",
629 tid, inst->seqNum, inst->pcState());
630 }
631
632 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
633 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
634 }
635
636
637 if (wroteToTimeBuffer) {
638 DPRINTF(Activity, "Activity This Cycle.\n");
639 cpu->activityThisCycle();
640 }
641
642 updateStatus();
643}
644
645#if FULL_SYSTEM
646template <class Impl>
647void
648DefaultCommit<Impl>::handleInterrupt()
649{
650 if (interrupt != NoFault) {
651 // Wait until the ROB is empty and all stores have drained in
652 // order to enter the interrupt.
653 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
654 // Squash or record that I need to squash this cycle if
655 // an interrupt needed to be handled.
656 DPRINTF(Commit, "Interrupt detected.\n");
657
658 // Clear the interrupt now that it's going to be handled
659 toIEW->commitInfo[0].clearInterrupt = true;
660
661 assert(!thread[0]->inSyscall);
662 thread[0]->inSyscall = true;
663
664 // CPU will handle interrupt.
665 cpu->processInterrupts(interrupt);
666
667 thread[0]->inSyscall = false;
668
669 commitStatus[0] = TrapPending;
670
671 // Generate trap squash event.
672 generateTrapEvent(0);
673
674 interrupt = NoFault;
675 } else {
676 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
677 }
678 } else if (commitStatus[0] != TrapPending &&
679 cpu->checkInterrupts(cpu->tcBase(0)) &&
680 !trapSquash[0] &&
681 !tcSquash[0]) {
682 // Process interrupts if interrupts are enabled, not in PAL
683 // mode, and no other traps or external squashes are currently
684 // pending.
685 // @todo: Allow other threads to handle interrupts.
686
687 // Get any interrupt that happened
688 interrupt = cpu->getInterrupts();
689
690 if (interrupt != NoFault) {
691 // Tell fetch that there is an interrupt pending. This
692 // will make fetch wait until it sees a non PAL-mode PC,
693 // at which point it stops fetching instructions.
694 toIEW->commitInfo[0].interruptPending = true;
695 }
696 }
697}
698#endif // FULL_SYSTEM
699
700template <class Impl>
701void
702DefaultCommit<Impl>::commit()
703{
704
705#if FULL_SYSTEM
706 // Check for any interrupt, and start processing it. Or if we
707 // have an outstanding interrupt and are at a point when it is
708 // valid to take an interrupt, process it.
709 if (cpu->checkInterrupts(cpu->tcBase(0))) {
710 handleInterrupt();
711 }
712#endif // FULL_SYSTEM
713
714 ////////////////////////////////////
715 // Check for any possible squashes, handle them first
716 ////////////////////////////////////
717 list<ThreadID>::iterator threads = activeThreads->begin();
718 list<ThreadID>::iterator end = activeThreads->end();
719
720 while (threads != end) {
721 ThreadID tid = *threads++;
722
723 // Not sure which one takes priority. I think if we have
724 // both, that's a bad sign.
725 if (trapSquash[tid] == true) {
726 assert(!tcSquash[tid]);
727 squashFromTrap(tid);
728 } else if (tcSquash[tid] == true) {
729 assert(commitStatus[tid] != TrapPending);
730 squashFromTC(tid);
731 }
732
733 // Squashed sequence number must be older than youngest valid
734 // instruction in the ROB. This prevents squashes from younger
735 // instructions overriding squashes from older instructions.
736 if (fromIEW->squash[tid] &&
737 commitStatus[tid] != TrapPending &&
738 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
739
740 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
741 tid,
742 fromIEW->mispredPC[tid],
743 fromIEW->squashedSeqNum[tid]);
744
745 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
746 tid,
747 fromIEW->pc[tid].nextInstAddr());
748
749 commitStatus[tid] = ROBSquashing;
750
751 // If we want to include the squashing instruction in the squash,
752 // then use one older sequence number.
753 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
754
755 if (fromIEW->includeSquashInst[tid] == true) {
756 squashed_inst--;
757 }
758
759 // All younger instructions will be squashed. Set the sequence
760 // number as the youngest instruction in the ROB.
761 youngestSeqNum[tid] = squashed_inst;
762
763 rob->squash(squashed_inst, tid);
764 changedROBNumEntries[tid] = true;
765
766 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
767
768 toIEW->commitInfo[tid].squash = true;
769
770 // Send back the rob squashing signal so other stages know that
771 // the ROB is in the process of squashing.
772 toIEW->commitInfo[tid].robSquashing = true;
773
774 toIEW->commitInfo[tid].branchMispredict =
775 fromIEW->branchMispredict[tid];
776
777 toIEW->commitInfo[tid].branchTaken =
778 fromIEW->branchTaken[tid];
779
780 toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
781
782 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
783
784 if (toIEW->commitInfo[tid].branchMispredict) {
785 ++branchMispredicts;
786 }
787 }
788
789 }
790
791 setNextStatus();
792
793 if (squashCounter != numThreads) {
794 // If we're not currently squashing, then get instructions.
795 getInsts();
796
797 // Try to commit any instructions.
798 commitInsts();
799 }
800
801 //Check for any activity
802 threads = activeThreads->begin();
803
804 while (threads != end) {
805 ThreadID tid = *threads++;
806
807 if (changedROBNumEntries[tid]) {
808 toIEW->commitInfo[tid].usedROB = true;
809 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
810
811 wroteToTimeBuffer = true;
812 changedROBNumEntries[tid] = false;
813 if (rob->isEmpty(tid))
814 checkEmptyROB[tid] = true;
815 }
816
817 // ROB is only considered "empty" for previous stages if: a)
818 // ROB is empty, b) there are no outstanding stores, c) IEW
819 // stage has received any information regarding stores that
820 // committed.
821 // c) is checked by making sure to not consider the ROB empty
822 // on the same cycle as when stores have been committed.
823 // @todo: Make this handle multi-cycle communication between
824 // commit and IEW.
825 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
826 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
827 checkEmptyROB[tid] = false;
828 toIEW->commitInfo[tid].usedROB = true;
829 toIEW->commitInfo[tid].emptyROB = true;
830 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
831 wroteToTimeBuffer = true;
832 }
833
834 }
835}
836
837template <class Impl>
838void
839DefaultCommit<Impl>::commitInsts()
840{
841 ////////////////////////////////////
842 // Handle commit
843 // Note that commit will be handled prior to putting new
844 // instructions in the ROB so that the ROB only tries to commit
845 // instructions it has in this current cycle, and not instructions
846 // it is writing in during this cycle. Can't commit and squash
847 // things at the same time...
848 ////////////////////////////////////
849
850 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
851
852 unsigned num_committed = 0;
853
854 DynInstPtr head_inst;
855
856 // Commit as many instructions as possible until the commit bandwidth
857 // limit is reached, or it becomes impossible to commit any more.
858 while (num_committed < commitWidth) {
859 int commit_thread = getCommittingThread();
860
861 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
862 break;
863
864 head_inst = rob->readHeadInst(commit_thread);
865
866 ThreadID tid = head_inst->threadNumber;
867
868 assert(tid == commit_thread);
869
870 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
871 head_inst->seqNum, tid);
872
873 // If the head instruction is squashed, it is ready to retire
874 // (be removed from the ROB) at any time.
875 if (head_inst->isSquashed()) {
876
877 DPRINTF(Commit, "Retiring squashed instruction from "
878 "ROB.\n");
879
880 rob->retireHead(commit_thread);
881
882 ++commitSquashedInsts;
883
884 // Record that the number of ROB entries has changed.
885 changedROBNumEntries[tid] = true;
886 } else {
887 pc[tid] = head_inst->pcState();
888
889 // Increment the total number of non-speculative instructions
890 // executed.
891 // Hack for now: it really shouldn't happen until after the
892 // commit is deemed to be successful, but this count is needed
893 // for syscalls.
894 thread[tid]->funcExeInst++;
895
896 // Try to commit the head instruction.
897 bool commit_success = commitHead(head_inst, num_committed);
898
899 if (commit_success) {
900 ++num_committed;
901
902 changedROBNumEntries[tid] = true;
903
904 // Set the doneSeqNum to the youngest committed instruction.
905 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
906
907 ++commitCommittedInsts;
908
909 // To match the old model, don't count nops and instruction
910 // prefetches towards the total commit count.
911 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
912 cpu->instDone(tid);
913 }
914
|
903 TheISA::advancePC(pc[tid], head_inst->staticInst);
904
905 int count = 0;
906 Addr oldpc;
907 // Debug statement. Checks to make sure we're not
908 // currently updating state while handling PC events.
909 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
910 do {
911 oldpc = pc[tid].instAddr();
912 cpu->system->pcEventQueue.service(thread[tid]->getTC());
913 count++;
914 } while (oldpc != pc[tid].instAddr());
915 if (count > 1) {
916 DPRINTF(Commit,
917 "PC skip function event, stopping commit\n");
918 break;
919 }
920 } else {
921 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
922 "[tid:%i] [sn:%i].\n",
923 head_inst->pcState(), tid ,head_inst->seqNum);
924 break;
925 }
926 }
927 }
928
929 DPRINTF(CommitRate, "%i\n", num_committed);
930 numCommittedDist.sample(num_committed);
931
932 if (num_committed == commitWidth) {
933 commitEligibleSamples++;
934 }
935}
936
937template <class Impl>
938bool
939DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
940{
941 assert(head_inst);
942
943 ThreadID tid = head_inst->threadNumber;
944
945 // If the instruction is not executed yet, then it will need extra
946 // handling. Signal backwards that it should be executed.
947 if (!head_inst->isExecuted()) {
948 // Keep this number correct. We have not yet actually executed
949 // and committed this instruction.
950 thread[tid]->funcExeInst--;
951
952 if (head_inst->isNonSpeculative() ||
953 head_inst->isStoreConditional() ||
954 head_inst->isMemBarrier() ||
955 head_inst->isWriteBarrier()) {
956
957 DPRINTF(Commit, "Encountered a barrier or non-speculative "
958 "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
959 head_inst->seqNum, head_inst->pcState());
960
961 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
962 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
963 return false;
964 }
965
966 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
967
968 // Change the instruction so it won't try to commit again until
969 // it is executed.
970 head_inst->clearCanCommit();
971
972 ++commitNonSpecStalls;
973
974 return false;
975 } else if (head_inst->isLoad()) {
976 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
977 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
978 return false;
979 }
980
981 assert(head_inst->uncacheable());
982 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
983 head_inst->seqNum, head_inst->pcState());
984
985 // Send back the non-speculative instruction's sequence
986 // number. Tell the lsq to re-execute the load.
987 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
988 toIEW->commitInfo[tid].uncached = true;
989 toIEW->commitInfo[tid].uncachedLoad = head_inst;
990
991 head_inst->clearCanCommit();
992
993 return false;
994 } else {
995 panic("Trying to commit un-executed instruction "
996 "of unknown type!\n");
997 }
998 }
999
1000 if (head_inst->isThreadSync()) {
1001 // Not handled for now.
1002 panic("Thread sync instructions are not handled yet.\n");
1003 }
1004
1005 // Check if the instruction caused a fault. If so, trap.
1006 Fault inst_fault = head_inst->getFault();
1007
1008 // Stores mark themselves as completed.
1009 if (!head_inst->isStore() && inst_fault == NoFault) {
1010 head_inst->setCompleted();
1011 }
1012
1013#if USE_CHECKER
1014 // Use checker prior to updating anything due to traps or PC
1015 // based events.
1016 if (cpu->checker) {
1017 cpu->checker->verify(head_inst);
1018 }
1019#endif
1020
1021 if (inst_fault != NoFault) {
1022 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1023 head_inst->seqNum, head_inst->pcState());
1024
1025 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1026 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1027 return false;
1028 }
1029
1030 head_inst->setCompleted();
1031
1032#if USE_CHECKER
1033 if (cpu->checker && head_inst->isStore()) {
1034 cpu->checker->verify(head_inst);
1035 }
1036#endif
1037
1038 assert(!thread[tid]->inSyscall);
1039
1040 // Mark that we're in state update mode so that the trap's
1041 // execution doesn't generate extra squashes.
1042 thread[tid]->inSyscall = true;
1043
1044 // Execute the trap. Although it's slightly unrealistic in
1045 // terms of timing (as it doesn't wait for the full timing of
1046 // the trap event to complete before updating state), it's
1047 // needed to update the state as soon as possible. This
1048 // prevents external agents from changing any specific state
1049 // that the trap need.
1050 cpu->trap(inst_fault, tid, head_inst->staticInst);
1051
1052 // Exit state update mode to avoid accidental updating.
1053 thread[tid]->inSyscall = false;
1054
1055 commitStatus[tid] = TrapPending;
1056
1057 if (head_inst->traceData) {
1058 if (DTRACE(ExecFaulting)) {
1059 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1060 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1061 head_inst->traceData->dump();
1062 }
1063 delete head_inst->traceData;
1064 head_inst->traceData = NULL;
1065 }
1066
1067 // Generate trap squash event.
1068 generateTrapEvent(tid);
1069 return false;
1070 }
1071
1072 updateComInstStats(head_inst);
1073
1074#if FULL_SYSTEM
1075 if (thread[tid]->profile) {
1076 thread[tid]->profilePC = head_inst->instAddr();
1077 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1078 head_inst->staticInst);
1079
1080 if (node)
1081 thread[tid]->profileNode = node;
1082 }
1083 if (CPA::available()) {
1084 if (head_inst->isControl()) {
1085 ThreadContext *tc = thread[tid]->getTC();
1086 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1087 }
1088 }
1089#endif
1090
1091 if (head_inst->traceData) {
1092 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1093 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1094 head_inst->traceData->dump();
1095 delete head_inst->traceData;
1096 head_inst->traceData = NULL;
1097 }
1098
1099 // Update the commit rename map
1100 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1101 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1102 head_inst->renamedDestRegIdx(i));
1103 }
1104
1105 if (head_inst->isCopy())
1106 panic("Should not commit any copy instructions!");
1107
1108 // Finally clear the head ROB entry.
1109 rob->retireHead(tid);
1110
1111 // If this was a store, record it for this cycle.
1112 if (head_inst->isStore())
1113 committedStores[tid] = true;
1114
1115 // Return true to indicate that we have committed an instruction.
1116 return true;
1117}
1118
1119template <class Impl>
1120void
1121DefaultCommit<Impl>::getInsts()
1122{
1123 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1124
1125 // Read any renamed instructions and place them into the ROB.
1126 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1127
1128 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1129 DynInstPtr inst;
1130
1131 inst = fromRename->insts[inst_num];
1132 ThreadID tid = inst->threadNumber;
1133
1134 if (!inst->isSquashed() &&
1135 commitStatus[tid] != ROBSquashing &&
1136 commitStatus[tid] != TrapPending) {
1137 changedROBNumEntries[tid] = true;
1138
1139 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1140 inst->pcState(), inst->seqNum, tid);
1141
1142 rob->insertInst(inst);
1143
1144 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1145
1146 youngestSeqNum[tid] = inst->seqNum;
1147 } else {
1148 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1149 "squashed, skipping.\n",
1150 inst->pcState(), inst->seqNum, tid);
1151 }
1152 }
1153}
1154
1155template <class Impl>
1156void
1157DefaultCommit<Impl>::skidInsert()
1158{
1159 DPRINTF(Commit, "Attempting to any instructions from rename into "
1160 "skidBuffer.\n");
1161
1162 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1163 DynInstPtr inst = fromRename->insts[inst_num];
1164
1165 if (!inst->isSquashed()) {
1166 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1167 "skidBuffer.\n", inst->pcState(), inst->seqNum,
1168 inst->threadNumber);
1169 skidBuffer.push(inst);
1170 } else {
1171 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1172 "squashed, skipping.\n",
1173 inst->pcState(), inst->seqNum, inst->threadNumber);
1174 }
1175 }
1176}
1177
1178template <class Impl>
1179void
1180DefaultCommit<Impl>::markCompletedInsts()
1181{
1182 // Grab completed insts out of the IEW instruction queue, and mark
1183 // instructions completed within the ROB.
1184 for (int inst_num = 0;
1185 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1186 ++inst_num)
1187 {
1188 if (!fromIEW->insts[inst_num]->isSquashed()) {
1189 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1190 "within ROB.\n",
1191 fromIEW->insts[inst_num]->threadNumber,
1192 fromIEW->insts[inst_num]->pcState(),
1193 fromIEW->insts[inst_num]->seqNum);
1194
1195 // Mark the instruction as ready to commit.
1196 fromIEW->insts[inst_num]->setCanCommit();
1197 }
1198 }
1199}
1200
1201template <class Impl>
1202bool
1203DefaultCommit<Impl>::robDoneSquashing()
1204{
1205 list<ThreadID>::iterator threads = activeThreads->begin();
1206 list<ThreadID>::iterator end = activeThreads->end();
1207
1208 while (threads != end) {
1209 ThreadID tid = *threads++;
1210
1211 if (!rob->isDoneSquashing(tid))
1212 return false;
1213 }
1214
1215 return true;
1216}
1217
1218template <class Impl>
1219void
1220DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1221{
1222 ThreadID tid = inst->threadNumber;
1223
1224 //
1225 // Pick off the software prefetches
1226 //
1227#ifdef TARGET_ALPHA
1228 if (inst->isDataPrefetch()) {
1229 statComSwp[tid]++;
1230 } else {
1231 statComInst[tid]++;
1232 }
1233#else
1234 statComInst[tid]++;
1235#endif
1236
1237 //
1238 // Control Instructions
1239 //
1240 if (inst->isControl())
1241 statComBranches[tid]++;
1242
1243 //
1244 // Memory references
1245 //
1246 if (inst->isMemRef()) {
1247 statComRefs[tid]++;
1248
1249 if (inst->isLoad()) {
1250 statComLoads[tid]++;
1251 }
1252 }
1253
1254 if (inst->isMemBarrier()) {
1255 statComMembars[tid]++;
1256 }
1257}
1258
1259////////////////////////////////////////
1260// //
1261// SMT COMMIT POLICY MAINTAINED HERE //
1262// //
1263////////////////////////////////////////
1264template <class Impl>
1265ThreadID
1266DefaultCommit<Impl>::getCommittingThread()
1267{
1268 if (numThreads > 1) {
1269 switch (commitPolicy) {
1270
1271 case Aggressive:
1272 //If Policy is Aggressive, commit will call
1273 //this function multiple times per
1274 //cycle
1275 return oldestReady();
1276
1277 case RoundRobin:
1278 return roundRobin();
1279
1280 case OldestReady:
1281 return oldestReady();
1282
1283 default:
1284 return InvalidThreadID;
1285 }
1286 } else {
1287 assert(!activeThreads->empty());
1288 ThreadID tid = activeThreads->front();
1289
1290 if (commitStatus[tid] == Running ||
1291 commitStatus[tid] == Idle ||
1292 commitStatus[tid] == FetchTrapPending) {
1293 return tid;
1294 } else {
1295 return InvalidThreadID;
1296 }
1297 }
1298}
1299
1300template<class Impl>
1301ThreadID
1302DefaultCommit<Impl>::roundRobin()
1303{
1304 list<ThreadID>::iterator pri_iter = priority_list.begin();
1305 list<ThreadID>::iterator end = priority_list.end();
1306
1307 while (pri_iter != end) {
1308 ThreadID tid = *pri_iter;
1309
1310 if (commitStatus[tid] == Running ||
1311 commitStatus[tid] == Idle ||
1312 commitStatus[tid] == FetchTrapPending) {
1313
1314 if (rob->isHeadReady(tid)) {
1315 priority_list.erase(pri_iter);
1316 priority_list.push_back(tid);
1317
1318 return tid;
1319 }
1320 }
1321
1322 pri_iter++;
1323 }
1324
1325 return InvalidThreadID;
1326}
1327
1328template<class Impl>
1329ThreadID
1330DefaultCommit<Impl>::oldestReady()
1331{
1332 unsigned oldest = 0;
1333 bool first = true;
1334
1335 list<ThreadID>::iterator threads = activeThreads->begin();
1336 list<ThreadID>::iterator end = activeThreads->end();
1337
1338 while (threads != end) {
1339 ThreadID tid = *threads++;
1340
1341 if (!rob->isEmpty(tid) &&
1342 (commitStatus[tid] == Running ||
1343 commitStatus[tid] == Idle ||
1344 commitStatus[tid] == FetchTrapPending)) {
1345
1346 if (rob->isHeadReady(tid)) {
1347
1348 DynInstPtr head_inst = rob->readHeadInst(tid);
1349
1350 if (first) {
1351 oldest = tid;
1352 first = false;
1353 } else if (head_inst->seqNum < oldest) {
1354 oldest = tid;
1355 }
1356 }
1357 }
1358 }
1359
1360 if (!first) {
1361 return oldest;
1362 } else {
1363 return InvalidThreadID;
1364 }
1365}
| 918 TheISA::advancePC(pc[tid], head_inst->staticInst);
919
920 int count = 0;
921 Addr oldpc;
922 // Debug statement. Checks to make sure we're not
923 // currently updating state while handling PC events.
924 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
925 do {
926 oldpc = pc[tid].instAddr();
927 cpu->system->pcEventQueue.service(thread[tid]->getTC());
928 count++;
929 } while (oldpc != pc[tid].instAddr());
930 if (count > 1) {
931 DPRINTF(Commit,
932 "PC skip function event, stopping commit\n");
933 break;
934 }
935 } else {
936 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
937 "[tid:%i] [sn:%i].\n",
938 head_inst->pcState(), tid ,head_inst->seqNum);
939 break;
940 }
941 }
942 }
943
944 DPRINTF(CommitRate, "%i\n", num_committed);
945 numCommittedDist.sample(num_committed);
946
947 if (num_committed == commitWidth) {
948 commitEligibleSamples++;
949 }
950}
951
952template <class Impl>
953bool
954DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
955{
956 assert(head_inst);
957
958 ThreadID tid = head_inst->threadNumber;
959
960 // If the instruction is not executed yet, then it will need extra
961 // handling. Signal backwards that it should be executed.
962 if (!head_inst->isExecuted()) {
963 // Keep this number correct. We have not yet actually executed
964 // and committed this instruction.
965 thread[tid]->funcExeInst--;
966
967 if (head_inst->isNonSpeculative() ||
968 head_inst->isStoreConditional() ||
969 head_inst->isMemBarrier() ||
970 head_inst->isWriteBarrier()) {
971
972 DPRINTF(Commit, "Encountered a barrier or non-speculative "
973 "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
974 head_inst->seqNum, head_inst->pcState());
975
976 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
977 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
978 return false;
979 }
980
981 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
982
983 // Change the instruction so it won't try to commit again until
984 // it is executed.
985 head_inst->clearCanCommit();
986
987 ++commitNonSpecStalls;
988
989 return false;
990 } else if (head_inst->isLoad()) {
991 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
992 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
993 return false;
994 }
995
996 assert(head_inst->uncacheable());
997 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
998 head_inst->seqNum, head_inst->pcState());
999
1000 // Send back the non-speculative instruction's sequence
1001 // number. Tell the lsq to re-execute the load.
1002 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1003 toIEW->commitInfo[tid].uncached = true;
1004 toIEW->commitInfo[tid].uncachedLoad = head_inst;
1005
1006 head_inst->clearCanCommit();
1007
1008 return false;
1009 } else {
1010 panic("Trying to commit un-executed instruction "
1011 "of unknown type!\n");
1012 }
1013 }
1014
1015 if (head_inst->isThreadSync()) {
1016 // Not handled for now.
1017 panic("Thread sync instructions are not handled yet.\n");
1018 }
1019
1020 // Check if the instruction caused a fault. If so, trap.
1021 Fault inst_fault = head_inst->getFault();
1022
1023 // Stores mark themselves as completed.
1024 if (!head_inst->isStore() && inst_fault == NoFault) {
1025 head_inst->setCompleted();
1026 }
1027
1028#if USE_CHECKER
1029 // Use checker prior to updating anything due to traps or PC
1030 // based events.
1031 if (cpu->checker) {
1032 cpu->checker->verify(head_inst);
1033 }
1034#endif
1035
1036 if (inst_fault != NoFault) {
1037 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1038 head_inst->seqNum, head_inst->pcState());
1039
1040 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1041 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1042 return false;
1043 }
1044
1045 head_inst->setCompleted();
1046
1047#if USE_CHECKER
1048 if (cpu->checker && head_inst->isStore()) {
1049 cpu->checker->verify(head_inst);
1050 }
1051#endif
1052
1053 assert(!thread[tid]->inSyscall);
1054
1055 // Mark that we're in state update mode so that the trap's
1056 // execution doesn't generate extra squashes.
1057 thread[tid]->inSyscall = true;
1058
1059 // Execute the trap. Although it's slightly unrealistic in
1060 // terms of timing (as it doesn't wait for the full timing of
1061 // the trap event to complete before updating state), it's
1062 // needed to update the state as soon as possible. This
1063 // prevents external agents from changing any specific state
1064 // that the trap need.
1065 cpu->trap(inst_fault, tid, head_inst->staticInst);
1066
1067 // Exit state update mode to avoid accidental updating.
1068 thread[tid]->inSyscall = false;
1069
1070 commitStatus[tid] = TrapPending;
1071
1072 if (head_inst->traceData) {
1073 if (DTRACE(ExecFaulting)) {
1074 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1075 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1076 head_inst->traceData->dump();
1077 }
1078 delete head_inst->traceData;
1079 head_inst->traceData = NULL;
1080 }
1081
1082 // Generate trap squash event.
1083 generateTrapEvent(tid);
1084 return false;
1085 }
1086
1087 updateComInstStats(head_inst);
1088
1089#if FULL_SYSTEM
1090 if (thread[tid]->profile) {
1091 thread[tid]->profilePC = head_inst->instAddr();
1092 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1093 head_inst->staticInst);
1094
1095 if (node)
1096 thread[tid]->profileNode = node;
1097 }
1098 if (CPA::available()) {
1099 if (head_inst->isControl()) {
1100 ThreadContext *tc = thread[tid]->getTC();
1101 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1102 }
1103 }
1104#endif
1105
1106 if (head_inst->traceData) {
1107 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1108 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1109 head_inst->traceData->dump();
1110 delete head_inst->traceData;
1111 head_inst->traceData = NULL;
1112 }
1113
1114 // Update the commit rename map
1115 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1116 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1117 head_inst->renamedDestRegIdx(i));
1118 }
1119
1120 if (head_inst->isCopy())
1121 panic("Should not commit any copy instructions!");
1122
1123 // Finally clear the head ROB entry.
1124 rob->retireHead(tid);
1125
1126 // If this was a store, record it for this cycle.
1127 if (head_inst->isStore())
1128 committedStores[tid] = true;
1129
1130 // Return true to indicate that we have committed an instruction.
1131 return true;
1132}
1133
1134template <class Impl>
1135void
1136DefaultCommit<Impl>::getInsts()
1137{
1138 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1139
1140 // Read any renamed instructions and place them into the ROB.
1141 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1142
1143 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1144 DynInstPtr inst;
1145
1146 inst = fromRename->insts[inst_num];
1147 ThreadID tid = inst->threadNumber;
1148
1149 if (!inst->isSquashed() &&
1150 commitStatus[tid] != ROBSquashing &&
1151 commitStatus[tid] != TrapPending) {
1152 changedROBNumEntries[tid] = true;
1153
1154 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1155 inst->pcState(), inst->seqNum, tid);
1156
1157 rob->insertInst(inst);
1158
1159 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1160
1161 youngestSeqNum[tid] = inst->seqNum;
1162 } else {
1163 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1164 "squashed, skipping.\n",
1165 inst->pcState(), inst->seqNum, tid);
1166 }
1167 }
1168}
1169
1170template <class Impl>
1171void
1172DefaultCommit<Impl>::skidInsert()
1173{
1174 DPRINTF(Commit, "Attempting to any instructions from rename into "
1175 "skidBuffer.\n");
1176
1177 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1178 DynInstPtr inst = fromRename->insts[inst_num];
1179
1180 if (!inst->isSquashed()) {
1181 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1182 "skidBuffer.\n", inst->pcState(), inst->seqNum,
1183 inst->threadNumber);
1184 skidBuffer.push(inst);
1185 } else {
1186 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1187 "squashed, skipping.\n",
1188 inst->pcState(), inst->seqNum, inst->threadNumber);
1189 }
1190 }
1191}
1192
1193template <class Impl>
1194void
1195DefaultCommit<Impl>::markCompletedInsts()
1196{
1197 // Grab completed insts out of the IEW instruction queue, and mark
1198 // instructions completed within the ROB.
1199 for (int inst_num = 0;
1200 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1201 ++inst_num)
1202 {
1203 if (!fromIEW->insts[inst_num]->isSquashed()) {
1204 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1205 "within ROB.\n",
1206 fromIEW->insts[inst_num]->threadNumber,
1207 fromIEW->insts[inst_num]->pcState(),
1208 fromIEW->insts[inst_num]->seqNum);
1209
1210 // Mark the instruction as ready to commit.
1211 fromIEW->insts[inst_num]->setCanCommit();
1212 }
1213 }
1214}
1215
1216template <class Impl>
1217bool
1218DefaultCommit<Impl>::robDoneSquashing()
1219{
1220 list<ThreadID>::iterator threads = activeThreads->begin();
1221 list<ThreadID>::iterator end = activeThreads->end();
1222
1223 while (threads != end) {
1224 ThreadID tid = *threads++;
1225
1226 if (!rob->isDoneSquashing(tid))
1227 return false;
1228 }
1229
1230 return true;
1231}
1232
1233template <class Impl>
1234void
1235DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1236{
1237 ThreadID tid = inst->threadNumber;
1238
1239 //
1240 // Pick off the software prefetches
1241 //
1242#ifdef TARGET_ALPHA
1243 if (inst->isDataPrefetch()) {
1244 statComSwp[tid]++;
1245 } else {
1246 statComInst[tid]++;
1247 }
1248#else
1249 statComInst[tid]++;
1250#endif
1251
1252 //
1253 // Control Instructions
1254 //
1255 if (inst->isControl())
1256 statComBranches[tid]++;
1257
1258 //
1259 // Memory references
1260 //
1261 if (inst->isMemRef()) {
1262 statComRefs[tid]++;
1263
1264 if (inst->isLoad()) {
1265 statComLoads[tid]++;
1266 }
1267 }
1268
1269 if (inst->isMemBarrier()) {
1270 statComMembars[tid]++;
1271 }
1272}
1273
1274////////////////////////////////////////
1275// //
1276// SMT COMMIT POLICY MAINTAINED HERE //
1277// //
1278////////////////////////////////////////
1279template <class Impl>
1280ThreadID
1281DefaultCommit<Impl>::getCommittingThread()
1282{
1283 if (numThreads > 1) {
1284 switch (commitPolicy) {
1285
1286 case Aggressive:
1287 //If Policy is Aggressive, commit will call
1288 //this function multiple times per
1289 //cycle
1290 return oldestReady();
1291
1292 case RoundRobin:
1293 return roundRobin();
1294
1295 case OldestReady:
1296 return oldestReady();
1297
1298 default:
1299 return InvalidThreadID;
1300 }
1301 } else {
1302 assert(!activeThreads->empty());
1303 ThreadID tid = activeThreads->front();
1304
1305 if (commitStatus[tid] == Running ||
1306 commitStatus[tid] == Idle ||
1307 commitStatus[tid] == FetchTrapPending) {
1308 return tid;
1309 } else {
1310 return InvalidThreadID;
1311 }
1312 }
1313}
1314
1315template<class Impl>
1316ThreadID
1317DefaultCommit<Impl>::roundRobin()
1318{
1319 list<ThreadID>::iterator pri_iter = priority_list.begin();
1320 list<ThreadID>::iterator end = priority_list.end();
1321
1322 while (pri_iter != end) {
1323 ThreadID tid = *pri_iter;
1324
1325 if (commitStatus[tid] == Running ||
1326 commitStatus[tid] == Idle ||
1327 commitStatus[tid] == FetchTrapPending) {
1328
1329 if (rob->isHeadReady(tid)) {
1330 priority_list.erase(pri_iter);
1331 priority_list.push_back(tid);
1332
1333 return tid;
1334 }
1335 }
1336
1337 pri_iter++;
1338 }
1339
1340 return InvalidThreadID;
1341}
1342
1343template<class Impl>
1344ThreadID
1345DefaultCommit<Impl>::oldestReady()
1346{
1347 unsigned oldest = 0;
1348 bool first = true;
1349
1350 list<ThreadID>::iterator threads = activeThreads->begin();
1351 list<ThreadID>::iterator end = activeThreads->end();
1352
1353 while (threads != end) {
1354 ThreadID tid = *threads++;
1355
1356 if (!rob->isEmpty(tid) &&
1357 (commitStatus[tid] == Running ||
1358 commitStatus[tid] == Idle ||
1359 commitStatus[tid] == FetchTrapPending)) {
1360
1361 if (rob->isHeadReady(tid)) {
1362
1363 DynInstPtr head_inst = rob->readHeadInst(tid);
1364
1365 if (first) {
1366 oldest = tid;
1367 first = false;
1368 } else if (head_inst->seqNum < oldest) {
1369 oldest = tid;
1370 }
1371 }
1372 }
1373 }
1374
1375 if (!first) {
1376 return oldest;
1377 } else {
1378 return InvalidThreadID;
1379 }
1380}
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