69{
70 return "Trap";
71}
72
73template <class Impl>
74DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, Params *params)
75 : cpu(_cpu),
76 squashCounter(0),
77 iewToCommitDelay(params->iewToCommitDelay),
78 commitToIEWDelay(params->commitToIEWDelay),
79 renameToROBDelay(params->renameToROBDelay),
80 fetchToCommitDelay(params->commitToFetchDelay),
81 renameWidth(params->renameWidth),
82 commitWidth(params->commitWidth),
83 numThreads(params->numberOfThreads),
84 drainPending(false),
85 switchedOut(false),
86 trapLatency(params->trapLatency)
87{
88 _status = Active;
89 _nextStatus = Inactive;
90 std::string policy = params->smtCommitPolicy;
91
92 //Convert string to lowercase
93 std::transform(policy.begin(), policy.end(), policy.begin(),
94 (int(*)(int)) tolower);
95
96 //Assign commit policy
97 if (policy == "aggressive"){
98 commitPolicy = Aggressive;
99
100 DPRINTF(Commit,"Commit Policy set to Aggressive.");
101 } else if (policy == "roundrobin"){
102 commitPolicy = RoundRobin;
103
104 //Set-Up Priority List
105 for (int tid=0; tid < numThreads; tid++) {
106 priority_list.push_back(tid);
107 }
108
109 DPRINTF(Commit,"Commit Policy set to Round Robin.");
110 } else if (policy == "oldestready"){
111 commitPolicy = OldestReady;
112
113 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
114 } else {
115 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
116 "RoundRobin,OldestReady}");
117 }
118
119 for (int i=0; i < numThreads; i++) {
120 commitStatus[i] = Idle;
121 changedROBNumEntries[i] = false;
122 checkEmptyROB[i] = false;
123 trapInFlight[i] = false;
124 committedStores[i] = false;
125 trapSquash[i] = false;
126 tcSquash[i] = false;
127 microPC[i] = nextMicroPC[i] = PC[i] = nextPC[i] = nextNPC[i] = 0;
128 }
129#if FULL_SYSTEM
130 interrupt = NoFault;
131#endif
132}
133
134template <class Impl>
135std::string
136DefaultCommit<Impl>::name() const
137{
138 return cpu->name() + ".commit";
139}
140
141template <class Impl>
142void
143DefaultCommit<Impl>::regStats()
144{
145 using namespace Stats;
146 commitCommittedInsts
147 .name(name() + ".commitCommittedInsts")
148 .desc("The number of committed instructions")
149 .prereq(commitCommittedInsts);
150 commitSquashedInsts
151 .name(name() + ".commitSquashedInsts")
152 .desc("The number of squashed insts skipped by commit")
153 .prereq(commitSquashedInsts);
154 commitSquashEvents
155 .name(name() + ".commitSquashEvents")
156 .desc("The number of times commit is told to squash")
157 .prereq(commitSquashEvents);
158 commitNonSpecStalls
159 .name(name() + ".commitNonSpecStalls")
160 .desc("The number of times commit has been forced to stall to "
161 "communicate backwards")
162 .prereq(commitNonSpecStalls);
163 branchMispredicts
164 .name(name() + ".branchMispredicts")
165 .desc("The number of times a branch was mispredicted")
166 .prereq(branchMispredicts);
167 numCommittedDist
168 .init(0,commitWidth,1)
169 .name(name() + ".COM:committed_per_cycle")
170 .desc("Number of insts commited each cycle")
171 .flags(Stats::pdf)
172 ;
173
174 statComInst
175 .init(cpu->number_of_threads)
176 .name(name() + ".COM:count")
177 .desc("Number of instructions committed")
178 .flags(total)
179 ;
180
181 statComSwp
182 .init(cpu->number_of_threads)
183 .name(name() + ".COM:swp_count")
184 .desc("Number of s/w prefetches committed")
185 .flags(total)
186 ;
187
188 statComRefs
189 .init(cpu->number_of_threads)
190 .name(name() + ".COM:refs")
191 .desc("Number of memory references committed")
192 .flags(total)
193 ;
194
195 statComLoads
196 .init(cpu->number_of_threads)
197 .name(name() + ".COM:loads")
198 .desc("Number of loads committed")
199 .flags(total)
200 ;
201
202 statComMembars
203 .init(cpu->number_of_threads)
204 .name(name() + ".COM:membars")
205 .desc("Number of memory barriers committed")
206 .flags(total)
207 ;
208
209 statComBranches
210 .init(cpu->number_of_threads)
211 .name(name() + ".COM:branches")
212 .desc("Number of branches committed")
213 .flags(total)
214 ;
215
216 commitEligible
217 .init(cpu->number_of_threads)
218 .name(name() + ".COM:bw_limited")
219 .desc("number of insts not committed due to BW limits")
220 .flags(total)
221 ;
222
223 commitEligibleSamples
224 .name(name() + ".COM:bw_lim_events")
225 .desc("number cycles where commit BW limit reached")
226 ;
227}
228
229template <class Impl>
230void
231DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
232{
233 thread = threads;
234}
235
236template <class Impl>
237void
238DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
239{
240 timeBuffer = tb_ptr;
241
242 // Setup wire to send information back to IEW.
243 toIEW = timeBuffer->getWire(0);
244
245 // Setup wire to read data from IEW (for the ROB).
246 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
247}
248
249template <class Impl>
250void
251DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
252{
253 fetchQueue = fq_ptr;
254
255 // Setup wire to get instructions from rename (for the ROB).
256 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
257}
258
259template <class Impl>
260void
261DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
262{
263 renameQueue = rq_ptr;
264
265 // Setup wire to get instructions from rename (for the ROB).
266 fromRename = renameQueue->getWire(-renameToROBDelay);
267}
268
269template <class Impl>
270void
271DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
272{
273 iewQueue = iq_ptr;
274
275 // Setup wire to get instructions from IEW.
276 fromIEW = iewQueue->getWire(-iewToCommitDelay);
277}
278
279template <class Impl>
280void
281DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
282{
283 iewStage = iew_stage;
284}
285
286template<class Impl>
287void
288DefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
289{
290 activeThreads = at_ptr;
291}
292
293template <class Impl>
294void
295DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
296{
297 for (int i=0; i < numThreads; i++) {
298 renameMap[i] = &rm_ptr[i];
299 }
300}
301
302template <class Impl>
303void
304DefaultCommit<Impl>::setROB(ROB *rob_ptr)
305{
306 rob = rob_ptr;
307}
308
309template <class Impl>
310void
311DefaultCommit<Impl>::initStage()
312{
313 rob->setActiveThreads(activeThreads);
314 rob->resetEntries();
315
316 // Broadcast the number of free entries.
317 for (int i=0; i < numThreads; i++) {
318 toIEW->commitInfo[i].usedROB = true;
319 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
320 toIEW->commitInfo[i].emptyROB = true;
321 }
322
323 // Commit must broadcast the number of free entries it has at the
324 // start of the simulation, so it starts as active.
325 cpu->activateStage(O3CPU::CommitIdx);
326
327 cpu->activityThisCycle();
328 trapLatency = cpu->ticks(trapLatency);
329}
330
331template <class Impl>
332bool
333DefaultCommit<Impl>::drain()
334{
335 drainPending = true;
336
337 return false;
338}
339
340template <class Impl>
341void
342DefaultCommit<Impl>::switchOut()
343{
344 switchedOut = true;
345 drainPending = false;
346 rob->switchOut();
347}
348
349template <class Impl>
350void
351DefaultCommit<Impl>::resume()
352{
353 drainPending = false;
354}
355
356template <class Impl>
357void
358DefaultCommit<Impl>::takeOverFrom()
359{
360 switchedOut = false;
361 _status = Active;
362 _nextStatus = Inactive;
363 for (int i=0; i < numThreads; i++) {
364 commitStatus[i] = Idle;
365 changedROBNumEntries[i] = false;
366 trapSquash[i] = false;
367 tcSquash[i] = false;
368 }
369 squashCounter = 0;
370 rob->takeOverFrom();
371}
372
373template <class Impl>
374void
375DefaultCommit<Impl>::updateStatus()
376{
377 // reset ROB changed variable
378 std::list<unsigned>::iterator threads = activeThreads->begin();
379 std::list<unsigned>::iterator end = activeThreads->end();
380
381 while (threads != end) {
382 unsigned tid = *threads++;
383
384 changedROBNumEntries[tid] = false;
385
386 // Also check if any of the threads has a trap pending
387 if (commitStatus[tid] == TrapPending ||
388 commitStatus[tid] == FetchTrapPending) {
389 _nextStatus = Active;
390 }
391 }
392
393 if (_nextStatus == Inactive && _status == Active) {
394 DPRINTF(Activity, "Deactivating stage.\n");
395 cpu->deactivateStage(O3CPU::CommitIdx);
396 } else if (_nextStatus == Active && _status == Inactive) {
397 DPRINTF(Activity, "Activating stage.\n");
398 cpu->activateStage(O3CPU::CommitIdx);
399 }
400
401 _status = _nextStatus;
402}
403
404template <class Impl>
405void
406DefaultCommit<Impl>::setNextStatus()
407{
408 int squashes = 0;
409
410 std::list<unsigned>::iterator threads = activeThreads->begin();
411 std::list<unsigned>::iterator end = activeThreads->end();
412
413 while (threads != end) {
414 unsigned tid = *threads++;
415
416 if (commitStatus[tid] == ROBSquashing) {
417 squashes++;
418 }
419 }
420
421 squashCounter = squashes;
422
423 // If commit is currently squashing, then it will have activity for the
424 // next cycle. Set its next status as active.
425 if (squashCounter) {
426 _nextStatus = Active;
427 }
428}
429
430template <class Impl>
431bool
432DefaultCommit<Impl>::changedROBEntries()
433{
434 std::list<unsigned>::iterator threads = activeThreads->begin();
435 std::list<unsigned>::iterator end = activeThreads->end();
436
437 while (threads != end) {
438 unsigned tid = *threads++;
439
440 if (changedROBNumEntries[tid]) {
441 return true;
442 }
443 }
444
445 return false;
446}
447
448template <class Impl>
449unsigned
450DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
451{
452 return rob->numFreeEntries(tid);
453}
454
455template <class Impl>
456void
457DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
458{
459 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
460
461 TrapEvent *trap = new TrapEvent(this, tid);
462
463 trap->schedule(curTick + trapLatency);
464 trapInFlight[tid] = true;
465}
466
467template <class Impl>
468void
469DefaultCommit<Impl>::generateTCEvent(unsigned tid)
470{
471 assert(!trapInFlight[tid]);
472 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
473
474 tcSquash[tid] = true;
475}
476
477template <class Impl>
478void
479DefaultCommit<Impl>::squashAll(unsigned tid)
480{
481 // If we want to include the squashing instruction in the squash,
482 // then use one older sequence number.
483 // Hopefully this doesn't mess things up. Basically I want to squash
484 // all instructions of this thread.
485 InstSeqNum squashed_inst = rob->isEmpty() ?
486 0 : rob->readHeadInst(tid)->seqNum - 1;
487
488 // All younger instructions will be squashed. Set the sequence
489 // number as the youngest instruction in the ROB (0 in this case.
490 // Hopefully nothing breaks.)
491 youngestSeqNum[tid] = 0;
492
493 rob->squash(squashed_inst, tid);
494 changedROBNumEntries[tid] = true;
495
496 // Send back the sequence number of the squashed instruction.
497 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
498
499 // Send back the squash signal to tell stages that they should
500 // squash.
501 toIEW->commitInfo[tid].squash = true;
502
503 // Send back the rob squashing signal so other stages know that
504 // the ROB is in the process of squashing.
505 toIEW->commitInfo[tid].robSquashing = true;
506
507 toIEW->commitInfo[tid].branchMispredict = false;
508
509 toIEW->commitInfo[tid].nextPC = PC[tid];
510 toIEW->commitInfo[tid].nextNPC = nextPC[tid];
511 toIEW->commitInfo[tid].nextMicroPC = nextMicroPC[tid];
512}
513
514template <class Impl>
515void
516DefaultCommit<Impl>::squashFromTrap(unsigned tid)
517{
518 squashAll(tid);
519
520 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
521
522 thread[tid]->trapPending = false;
523 thread[tid]->inSyscall = false;
524 trapInFlight[tid] = false;
525
526 trapSquash[tid] = false;
527
528 commitStatus[tid] = ROBSquashing;
529 cpu->activityThisCycle();
530}
531
532template <class Impl>
533void
534DefaultCommit<Impl>::squashFromTC(unsigned tid)
535{
536 squashAll(tid);
537
538 DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
539
540 thread[tid]->inSyscall = false;
541 assert(!thread[tid]->trapPending);
542
543 commitStatus[tid] = ROBSquashing;
544 cpu->activityThisCycle();
545
546 tcSquash[tid] = false;
547}
548
549template <class Impl>
550void
551DefaultCommit<Impl>::tick()
552{
553 wroteToTimeBuffer = false;
554 _nextStatus = Inactive;
555
556 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
557 cpu->signalDrained();
558 drainPending = false;
559 return;
560 }
561
562 if (activeThreads->empty())
563 return;
564
565 std::list<unsigned>::iterator threads = activeThreads->begin();
566 std::list<unsigned>::iterator end = activeThreads->end();
567
568 // Check if any of the threads are done squashing. Change the
569 // status if they are done.
570 while (threads != end) {
571 unsigned tid = *threads++;
572
573 // Clear the bit saying if the thread has committed stores
574 // this cycle.
575 committedStores[tid] = false;
576
577 if (commitStatus[tid] == ROBSquashing) {
578
579 if (rob->isDoneSquashing(tid)) {
580 commitStatus[tid] = Running;
581 } else {
582 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
583 " insts this cycle.\n", tid);
584 rob->doSquash(tid);
585 toIEW->commitInfo[tid].robSquashing = true;
586 wroteToTimeBuffer = true;
587 }
588 }
589 }
590
591 commit();
592
593 markCompletedInsts();
594
595 threads = activeThreads->begin();
596
597 while (threads != end) {
598 unsigned tid = *threads++;
599
600 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
601 // The ROB has more instructions it can commit. Its next status
602 // will be active.
603 _nextStatus = Active;
604
605 DynInstPtr inst = rob->readHeadInst(tid);
606
607 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
608 " ROB and ready to commit\n",
609 tid, inst->seqNum, inst->readPC());
610
611 } else if (!rob->isEmpty(tid)) {
612 DynInstPtr inst = rob->readHeadInst(tid);
613
614 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
615 "%#x is head of ROB and not ready\n",
616 tid, inst->seqNum, inst->readPC());
617 }
618
619 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
620 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
621 }
622
623
624 if (wroteToTimeBuffer) {
625 DPRINTF(Activity, "Activity This Cycle.\n");
626 cpu->activityThisCycle();
627 }
628
629 updateStatus();
630}
631
632#if FULL_SYSTEM
633template <class Impl>
634void
635DefaultCommit<Impl>::handleInterrupt()
636{
637 if (interrupt != NoFault) {
638 // Wait until the ROB is empty and all stores have drained in
639 // order to enter the interrupt.
640 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
641 // Squash or record that I need to squash this cycle if
642 // an interrupt needed to be handled.
643 DPRINTF(Commit, "Interrupt detected.\n");
644
645 // Clear the interrupt now that it's going to be handled
646 toIEW->commitInfo[0].clearInterrupt = true;
647
648 assert(!thread[0]->inSyscall);
649 thread[0]->inSyscall = true;
650
651 // CPU will handle interrupt.
652 cpu->processInterrupts(interrupt);
653
654 thread[0]->inSyscall = false;
655
656 commitStatus[0] = TrapPending;
657
658 // Generate trap squash event.
659 generateTrapEvent(0);
660
661 interrupt = NoFault;
662 } else {
663 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
664 }
665 } else if (commitStatus[0] != TrapPending &&
666 cpu->check_interrupts(cpu->tcBase(0)) &&
667 !trapSquash[0] &&
668 !tcSquash[0]) {
669 // Process interrupts if interrupts are enabled, not in PAL
670 // mode, and no other traps or external squashes are currently
671 // pending.
672 // @todo: Allow other threads to handle interrupts.
673
674 // Get any interrupt that happened
675 interrupt = cpu->getInterrupts();
676
677 if (interrupt != NoFault) {
678 // Tell fetch that there is an interrupt pending. This
679 // will make fetch wait until it sees a non PAL-mode PC,
680 // at which point it stops fetching instructions.
681 toIEW->commitInfo[0].interruptPending = true;
682 }
683 }
684}
685#endif // FULL_SYSTEM
686
687template <class Impl>
688void
689DefaultCommit<Impl>::commit()
690{
691
692#if FULL_SYSTEM
693 // Check for any interrupt, and start processing it. Or if we
694 // have an outstanding interrupt and are at a point when it is
695 // valid to take an interrupt, process it.
696 if (cpu->check_interrupts(cpu->tcBase(0))) {
697 handleInterrupt();
698 }
699#endif // FULL_SYSTEM
700
701 ////////////////////////////////////
702 // Check for any possible squashes, handle them first
703 ////////////////////////////////////
704 std::list<unsigned>::iterator threads = activeThreads->begin();
705 std::list<unsigned>::iterator end = activeThreads->end();
706
707 while (threads != end) {
708 unsigned tid = *threads++;
709
710 // Not sure which one takes priority. I think if we have
711 // both, that's a bad sign.
712 if (trapSquash[tid] == true) {
713 assert(!tcSquash[tid]);
714 squashFromTrap(tid);
715 } else if (tcSquash[tid] == true) {
716 assert(commitStatus[tid] != TrapPending);
717 squashFromTC(tid);
718 }
719
720 // Squashed sequence number must be older than youngest valid
721 // instruction in the ROB. This prevents squashes from younger
722 // instructions overriding squashes from older instructions.
723 if (fromIEW->squash[tid] &&
724 commitStatus[tid] != TrapPending &&
725 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
726
727 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
728 tid,
729 fromIEW->mispredPC[tid],
730 fromIEW->squashedSeqNum[tid]);
731
732 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
733 tid,
734 fromIEW->nextPC[tid]);
735
736 commitStatus[tid] = ROBSquashing;
737
738 // If we want to include the squashing instruction in the squash,
739 // then use one older sequence number.
740 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
741
742 if (fromIEW->includeSquashInst[tid] == true) {
743 squashed_inst--;
744 }
745
746 // All younger instructions will be squashed. Set the sequence
747 // number as the youngest instruction in the ROB.
748 youngestSeqNum[tid] = squashed_inst;
749
750 rob->squash(squashed_inst, tid);
751 changedROBNumEntries[tid] = true;
752
753 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
754
755 toIEW->commitInfo[tid].squash = true;
756
757 // Send back the rob squashing signal so other stages know that
758 // the ROB is in the process of squashing.
759 toIEW->commitInfo[tid].robSquashing = true;
760
761 toIEW->commitInfo[tid].branchMispredict =
762 fromIEW->branchMispredict[tid];
763
764 toIEW->commitInfo[tid].branchTaken =
765 fromIEW->branchTaken[tid];
766
767 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
768 toIEW->commitInfo[tid].nextNPC = fromIEW->nextNPC[tid];
769 toIEW->commitInfo[tid].nextMicroPC = fromIEW->nextMicroPC[tid];
770
771 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
772
773 if (toIEW->commitInfo[tid].branchMispredict) {
774 ++branchMispredicts;
775 }
776 }
777
778 }
779
780 setNextStatus();
781
782 if (squashCounter != numThreads) {
783 // If we're not currently squashing, then get instructions.
784 getInsts();
785
786 // Try to commit any instructions.
787 commitInsts();
788 }
789
790 //Check for any activity
791 threads = activeThreads->begin();
792
793 while (threads != end) {
794 unsigned tid = *threads++;
795
796 if (changedROBNumEntries[tid]) {
797 toIEW->commitInfo[tid].usedROB = true;
798 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
799
800 wroteToTimeBuffer = true;
801 changedROBNumEntries[tid] = false;
802 if (rob->isEmpty(tid))
803 checkEmptyROB[tid] = true;
804 }
805
806 // ROB is only considered "empty" for previous stages if: a)
807 // ROB is empty, b) there are no outstanding stores, c) IEW
808 // stage has received any information regarding stores that
809 // committed.
810 // c) is checked by making sure to not consider the ROB empty
811 // on the same cycle as when stores have been committed.
812 // @todo: Make this handle multi-cycle communication between
813 // commit and IEW.
814 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
815 !iewStage->hasStoresToWB() && !committedStores[tid]) {
816 checkEmptyROB[tid] = false;
817 toIEW->commitInfo[tid].usedROB = true;
818 toIEW->commitInfo[tid].emptyROB = true;
819 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
820 wroteToTimeBuffer = true;
821 }
822
823 }
824}
825
826template <class Impl>
827void
828DefaultCommit<Impl>::commitInsts()
829{
830 ////////////////////////////////////
831 // Handle commit
832 // Note that commit will be handled prior to putting new
833 // instructions in the ROB so that the ROB only tries to commit
834 // instructions it has in this current cycle, and not instructions
835 // it is writing in during this cycle. Can't commit and squash
836 // things at the same time...
837 ////////////////////////////////////
838
839 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
840
841 unsigned num_committed = 0;
842
843 DynInstPtr head_inst;
844
845 // Commit as many instructions as possible until the commit bandwidth
846 // limit is reached, or it becomes impossible to commit any more.
847 while (num_committed < commitWidth) {
848 int commit_thread = getCommittingThread();
849
850 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
851 break;
852
853 head_inst = rob->readHeadInst(commit_thread);
854
855 int tid = head_inst->threadNumber;
856
857 assert(tid == commit_thread);
858
859 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
860 head_inst->seqNum, tid);
861
862 // If the head instruction is squashed, it is ready to retire
863 // (be removed from the ROB) at any time.
864 if (head_inst->isSquashed()) {
865
866 DPRINTF(Commit, "Retiring squashed instruction from "
867 "ROB.\n");
868
869 rob->retireHead(commit_thread);
870
871 ++commitSquashedInsts;
872
873 // Record that the number of ROB entries has changed.
874 changedROBNumEntries[tid] = true;
875 } else {
876 PC[tid] = head_inst->readPC();
877 nextPC[tid] = head_inst->readNextPC();
878 nextNPC[tid] = head_inst->readNextNPC();
879 nextMicroPC[tid] = head_inst->readNextMicroPC();
880
881 // Increment the total number of non-speculative instructions
882 // executed.
883 // Hack for now: it really shouldn't happen until after the
884 // commit is deemed to be successful, but this count is needed
885 // for syscalls.
886 thread[tid]->funcExeInst++;
887
888 // Try to commit the head instruction.
889 bool commit_success = commitHead(head_inst, num_committed);
890
891 if (commit_success) {
892 ++num_committed;
893
894 changedROBNumEntries[tid] = true;
895
896 // Set the doneSeqNum to the youngest committed instruction.
897 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
898
899 ++commitCommittedInsts;
900
901 // To match the old model, don't count nops and instruction
902 // prefetches towards the total commit count.
903 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
904 cpu->instDone(tid);
905 }
906
907 PC[tid] = nextPC[tid];
908 nextPC[tid] = nextNPC[tid];
909 nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
910 microPC[tid] = nextMicroPC[tid];
911 nextMicroPC[tid] = microPC[tid] + 1;
912
913 int count = 0;
914 Addr oldpc;
915 // Debug statement. Checks to make sure we're not
916 // currently updating state while handling PC events.
917 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
918 do {
919 oldpc = PC[tid];
920 cpu->system->pcEventQueue.service(thread[tid]->getTC());
921 count++;
922 } while (oldpc != PC[tid]);
923 if (count > 1) {
924 DPRINTF(Commit,
925 "PC skip function event, stopping commit\n");
926 break;
927 }
928 } else {
929 DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
930 "[tid:%i] [sn:%i].\n",
931 head_inst->readPC(), tid ,head_inst->seqNum);
932 break;
933 }
934 }
935 }
936
937 DPRINTF(CommitRate, "%i\n", num_committed);
938 numCommittedDist.sample(num_committed);
939
940 if (num_committed == commitWidth) {
941 commitEligibleSamples++;
942 }
943}
944
945template <class Impl>
946bool
947DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
948{
949 assert(head_inst);
950
951 int tid = head_inst->threadNumber;
952
953 // If the instruction is not executed yet, then it will need extra
954 // handling. Signal backwards that it should be executed.
955 if (!head_inst->isExecuted()) {
956 // Keep this number correct. We have not yet actually executed
957 // and committed this instruction.
958 thread[tid]->funcExeInst--;
959
960 if (head_inst->isNonSpeculative() ||
961 head_inst->isStoreConditional() ||
962 head_inst->isMemBarrier() ||
963 head_inst->isWriteBarrier()) {
964
965 DPRINTF(Commit, "Encountered a barrier or non-speculative "
966 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
967 head_inst->seqNum, head_inst->readPC());
968
969 if (inst_num > 0 || iewStage->hasStoresToWB()) {
970 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
971 return false;
972 }
973
974 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
975
976 // Change the instruction so it won't try to commit again until
977 // it is executed.
978 head_inst->clearCanCommit();
979
980 ++commitNonSpecStalls;
981
982 return false;
983 } else if (head_inst->isLoad()) {
984 if (inst_num > 0 || iewStage->hasStoresToWB()) {
985 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
986 return false;
987 }
988
989 assert(head_inst->uncacheable());
990 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
991 head_inst->seqNum, head_inst->readPC());
992
993 // Send back the non-speculative instruction's sequence
994 // number. Tell the lsq to re-execute the load.
995 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
996 toIEW->commitInfo[tid].uncached = true;
997 toIEW->commitInfo[tid].uncachedLoad = head_inst;
998
999 head_inst->clearCanCommit();
1000
1001 return false;
1002 } else {
1003 panic("Trying to commit un-executed instruction "
1004 "of unknown type!\n");
1005 }
1006 }
1007
1008 if (head_inst->isThreadSync()) {
1009 // Not handled for now.
1010 panic("Thread sync instructions are not handled yet.\n");
1011 }
1012
1013 // Check if the instruction caused a fault. If so, trap.
1014 Fault inst_fault = head_inst->getFault();
1015
1016 // Stores mark themselves as completed.
1017 if (!head_inst->isStore() && inst_fault == NoFault) {
1018 head_inst->setCompleted();
1019 }
1020
1021#if USE_CHECKER
1022 // Use checker prior to updating anything due to traps or PC
1023 // based events.
1024 if (cpu->checker) {
1025 cpu->checker->verify(head_inst);
1026 }
1027#endif
1028
1029 // DTB will sometimes need the machine instruction for when
1030 // faults happen. So we will set it here, prior to the DTB
1031 // possibly needing it for its fault.
1032 thread[tid]->setInst(
1033 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1034
1035 if (inst_fault != NoFault) {
1036 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1037 head_inst->seqNum, head_inst->readPC());
1038
1039 if (iewStage->hasStoresToWB() || inst_num > 0) {
1040 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1041 return false;
1042 }
1043
1044 head_inst->setCompleted();
1045
1046#if USE_CHECKER
1047 if (cpu->checker && head_inst->isStore()) {
1048 cpu->checker->verify(head_inst);
1049 }
1050#endif
1051
1052 assert(!thread[tid]->inSyscall);
1053
1054 // Mark that we're in state update mode so that the trap's
1055 // execution doesn't generate extra squashes.
1056 thread[tid]->inSyscall = true;
1057
1058 // Execute the trap. Although it's slightly unrealistic in
1059 // terms of timing (as it doesn't wait for the full timing of
1060 // the trap event to complete before updating state), it's
1061 // needed to update the state as soon as possible. This
1062 // prevents external agents from changing any specific state
1063 // that the trap need.
1064 cpu->trap(inst_fault, tid);
1065
1066 // Exit state update mode to avoid accidental updating.
1067 thread[tid]->inSyscall = false;
1068
1069 commitStatus[tid] = TrapPending;
1070
1071 if (head_inst->traceData) {
1072 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1073 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1074 head_inst->traceData->dump();
1075 delete head_inst->traceData;
1076 head_inst->traceData = NULL;
1077 }
1078
1079 // Generate trap squash event.
1080 generateTrapEvent(tid);
1081// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC());
1082 return false;
1083 }
1084
1085 updateComInstStats(head_inst);
1086
1087#if FULL_SYSTEM
1088 if (thread[tid]->profile) {
1089// bool usermode = TheISA::inUserMode(thread[tid]->getTC());
1090// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC();
1091 thread[tid]->profilePC = head_inst->readPC();
1092 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1093 head_inst->staticInst);
1094
1095 if (node)
1096 thread[tid]->profileNode = node;
1097 }
1098#endif
1099
1100 if (head_inst->traceData) {
1101 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1102 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1103 head_inst->traceData->dump();
1104 delete head_inst->traceData;
1105 head_inst->traceData = NULL;
1106 }
1107
1108 // Update the commit rename map
1109 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1110 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1111 head_inst->renamedDestRegIdx(i));
1112 }
1113
1114 if (head_inst->isCopy())
1115 panic("Should not commit any copy instructions!");
1116
1117 // Finally clear the head ROB entry.
1118 rob->retireHead(tid);
1119
1120 // If this was a store, record it for this cycle.
1121 if (head_inst->isStore())
1122 committedStores[tid] = true;
1123
1124 // Return true to indicate that we have committed an instruction.
1125 return true;
1126}
1127
1128template <class Impl>
1129void
1130DefaultCommit<Impl>::getInsts()
1131{
1132 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1133
1134 // Read any renamed instructions and place them into the ROB.
1135 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1136
1137 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1138 DynInstPtr inst;
1139
1140 inst = fromRename->insts[inst_num];
1141 int tid = inst->threadNumber;
1142
1143 if (!inst->isSquashed() &&
1144 commitStatus[tid] != ROBSquashing &&
1145 commitStatus[tid] != TrapPending) {
1146 changedROBNumEntries[tid] = true;
1147
1148 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1149 inst->readPC(), inst->seqNum, tid);
1150
1151 rob->insertInst(inst);
1152
1153 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1154
1155 youngestSeqNum[tid] = inst->seqNum;
1156 } else {
1157 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1158 "squashed, skipping.\n",
1159 inst->readPC(), inst->seqNum, tid);
1160 }
1161 }
1162}
1163
1164template <class Impl>
1165void
1166DefaultCommit<Impl>::skidInsert()
1167{
1168 DPRINTF(Commit, "Attempting to any instructions from rename into "
1169 "skidBuffer.\n");
1170
1171 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1172 DynInstPtr inst = fromRename->insts[inst_num];
1173
1174 if (!inst->isSquashed()) {
1175 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1176 "skidBuffer.\n", inst->readPC(), inst->seqNum,
1177 inst->threadNumber);
1178 skidBuffer.push(inst);
1179 } else {
1180 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1181 "squashed, skipping.\n",
1182 inst->readPC(), inst->seqNum, inst->threadNumber);
1183 }
1184 }
1185}
1186
1187template <class Impl>
1188void
1189DefaultCommit<Impl>::markCompletedInsts()
1190{
1191 // Grab completed insts out of the IEW instruction queue, and mark
1192 // instructions completed within the ROB.
1193 for (int inst_num = 0;
1194 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1195 ++inst_num)
1196 {
1197 if (!fromIEW->insts[inst_num]->isSquashed()) {
1198 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1199 "within ROB.\n",
1200 fromIEW->insts[inst_num]->threadNumber,
1201 fromIEW->insts[inst_num]->readPC(),
1202 fromIEW->insts[inst_num]->seqNum);
1203
1204 // Mark the instruction as ready to commit.
1205 fromIEW->insts[inst_num]->setCanCommit();
1206 }
1207 }
1208}
1209
1210template <class Impl>
1211bool
1212DefaultCommit<Impl>::robDoneSquashing()
1213{
1214 std::list<unsigned>::iterator threads = activeThreads->begin();
1215 std::list<unsigned>::iterator end = activeThreads->end();
1216
1217 while (threads != end) {
1218 unsigned tid = *threads++;
1219
1220 if (!rob->isDoneSquashing(tid))
1221 return false;
1222 }
1223
1224 return true;
1225}
1226
1227template <class Impl>
1228void
1229DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1230{
1231 unsigned thread = inst->threadNumber;
1232
1233 //
1234 // Pick off the software prefetches
1235 //
1236#ifdef TARGET_ALPHA
1237 if (inst->isDataPrefetch()) {
1238 statComSwp[thread]++;
1239 } else {
1240 statComInst[thread]++;
1241 }
1242#else
1243 statComInst[thread]++;
1244#endif
1245
1246 //
1247 // Control Instructions
1248 //
1249 if (inst->isControl())
1250 statComBranches[thread]++;
1251
1252 //
1253 // Memory references
1254 //
1255 if (inst->isMemRef()) {
1256 statComRefs[thread]++;
1257
1258 if (inst->isLoad()) {
1259 statComLoads[thread]++;
1260 }
1261 }
1262
1263 if (inst->isMemBarrier()) {
1264 statComMembars[thread]++;
1265 }
1266}
1267
1268////////////////////////////////////////
1269// //
1270// SMT COMMIT POLICY MAINTAINED HERE //
1271// //
1272////////////////////////////////////////
1273template <class Impl>
1274int
1275DefaultCommit<Impl>::getCommittingThread()
1276{
1277 if (numThreads > 1) {
1278 switch (commitPolicy) {
1279
1280 case Aggressive:
1281 //If Policy is Aggressive, commit will call
1282 //this function multiple times per
1283 //cycle
1284 return oldestReady();
1285
1286 case RoundRobin:
1287 return roundRobin();
1288
1289 case OldestReady:
1290 return oldestReady();
1291
1292 default:
1293 return -1;
1294 }
1295 } else {
1296 assert(!activeThreads->empty());
1297 int tid = activeThreads->front();
1298
1299 if (commitStatus[tid] == Running ||
1300 commitStatus[tid] == Idle ||
1301 commitStatus[tid] == FetchTrapPending) {
1302 return tid;
1303 } else {
1304 return -1;
1305 }
1306 }
1307}
1308
1309template<class Impl>
1310int
1311DefaultCommit<Impl>::roundRobin()
1312{
1313 std::list<unsigned>::iterator pri_iter = priority_list.begin();
1314 std::list<unsigned>::iterator end = priority_list.end();
1315
1316 while (pri_iter != end) {
1317 unsigned tid = *pri_iter;
1318
1319 if (commitStatus[tid] == Running ||
1320 commitStatus[tid] == Idle ||
1321 commitStatus[tid] == FetchTrapPending) {
1322
1323 if (rob->isHeadReady(tid)) {
1324 priority_list.erase(pri_iter);
1325 priority_list.push_back(tid);
1326
1327 return tid;
1328 }
1329 }
1330
1331 pri_iter++;
1332 }
1333
1334 return -1;
1335}
1336
1337template<class Impl>
1338int
1339DefaultCommit<Impl>::oldestReady()
1340{
1341 unsigned oldest = 0;
1342 bool first = true;
1343
1344 std::list<unsigned>::iterator threads = activeThreads->begin();
1345 std::list<unsigned>::iterator end = activeThreads->end();
1346
1347 while (threads != end) {
1348 unsigned tid = *threads++;
1349
1350 if (!rob->isEmpty(tid) &&
1351 (commitStatus[tid] == Running ||
1352 commitStatus[tid] == Idle ||
1353 commitStatus[tid] == FetchTrapPending)) {
1354
1355 if (rob->isHeadReady(tid)) {
1356
1357 DynInstPtr head_inst = rob->readHeadInst(tid);
1358
1359 if (first) {
1360 oldest = tid;
1361 first = false;
1362 } else if (head_inst->seqNum < oldest) {
1363 oldest = tid;
1364 }
1365 }
1366 }
1367 }
1368
1369 if (!first) {
1370 return oldest;
1371 } else {
1372 return -1;
1373 }
1374}
| 69{
70 return "Trap";
71}
72
73template <class Impl>
74DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, Params *params)
75 : cpu(_cpu),
76 squashCounter(0),
77 iewToCommitDelay(params->iewToCommitDelay),
78 commitToIEWDelay(params->commitToIEWDelay),
79 renameToROBDelay(params->renameToROBDelay),
80 fetchToCommitDelay(params->commitToFetchDelay),
81 renameWidth(params->renameWidth),
82 commitWidth(params->commitWidth),
83 numThreads(params->numberOfThreads),
84 drainPending(false),
85 switchedOut(false),
86 trapLatency(params->trapLatency)
87{
88 _status = Active;
89 _nextStatus = Inactive;
90 std::string policy = params->smtCommitPolicy;
91
92 //Convert string to lowercase
93 std::transform(policy.begin(), policy.end(), policy.begin(),
94 (int(*)(int)) tolower);
95
96 //Assign commit policy
97 if (policy == "aggressive"){
98 commitPolicy = Aggressive;
99
100 DPRINTF(Commit,"Commit Policy set to Aggressive.");
101 } else if (policy == "roundrobin"){
102 commitPolicy = RoundRobin;
103
104 //Set-Up Priority List
105 for (int tid=0; tid < numThreads; tid++) {
106 priority_list.push_back(tid);
107 }
108
109 DPRINTF(Commit,"Commit Policy set to Round Robin.");
110 } else if (policy == "oldestready"){
111 commitPolicy = OldestReady;
112
113 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
114 } else {
115 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
116 "RoundRobin,OldestReady}");
117 }
118
119 for (int i=0; i < numThreads; i++) {
120 commitStatus[i] = Idle;
121 changedROBNumEntries[i] = false;
122 checkEmptyROB[i] = false;
123 trapInFlight[i] = false;
124 committedStores[i] = false;
125 trapSquash[i] = false;
126 tcSquash[i] = false;
127 microPC[i] = nextMicroPC[i] = PC[i] = nextPC[i] = nextNPC[i] = 0;
128 }
129#if FULL_SYSTEM
130 interrupt = NoFault;
131#endif
132}
133
134template <class Impl>
135std::string
136DefaultCommit<Impl>::name() const
137{
138 return cpu->name() + ".commit";
139}
140
141template <class Impl>
142void
143DefaultCommit<Impl>::regStats()
144{
145 using namespace Stats;
146 commitCommittedInsts
147 .name(name() + ".commitCommittedInsts")
148 .desc("The number of committed instructions")
149 .prereq(commitCommittedInsts);
150 commitSquashedInsts
151 .name(name() + ".commitSquashedInsts")
152 .desc("The number of squashed insts skipped by commit")
153 .prereq(commitSquashedInsts);
154 commitSquashEvents
155 .name(name() + ".commitSquashEvents")
156 .desc("The number of times commit is told to squash")
157 .prereq(commitSquashEvents);
158 commitNonSpecStalls
159 .name(name() + ".commitNonSpecStalls")
160 .desc("The number of times commit has been forced to stall to "
161 "communicate backwards")
162 .prereq(commitNonSpecStalls);
163 branchMispredicts
164 .name(name() + ".branchMispredicts")
165 .desc("The number of times a branch was mispredicted")
166 .prereq(branchMispredicts);
167 numCommittedDist
168 .init(0,commitWidth,1)
169 .name(name() + ".COM:committed_per_cycle")
170 .desc("Number of insts commited each cycle")
171 .flags(Stats::pdf)
172 ;
173
174 statComInst
175 .init(cpu->number_of_threads)
176 .name(name() + ".COM:count")
177 .desc("Number of instructions committed")
178 .flags(total)
179 ;
180
181 statComSwp
182 .init(cpu->number_of_threads)
183 .name(name() + ".COM:swp_count")
184 .desc("Number of s/w prefetches committed")
185 .flags(total)
186 ;
187
188 statComRefs
189 .init(cpu->number_of_threads)
190 .name(name() + ".COM:refs")
191 .desc("Number of memory references committed")
192 .flags(total)
193 ;
194
195 statComLoads
196 .init(cpu->number_of_threads)
197 .name(name() + ".COM:loads")
198 .desc("Number of loads committed")
199 .flags(total)
200 ;
201
202 statComMembars
203 .init(cpu->number_of_threads)
204 .name(name() + ".COM:membars")
205 .desc("Number of memory barriers committed")
206 .flags(total)
207 ;
208
209 statComBranches
210 .init(cpu->number_of_threads)
211 .name(name() + ".COM:branches")
212 .desc("Number of branches committed")
213 .flags(total)
214 ;
215
216 commitEligible
217 .init(cpu->number_of_threads)
218 .name(name() + ".COM:bw_limited")
219 .desc("number of insts not committed due to BW limits")
220 .flags(total)
221 ;
222
223 commitEligibleSamples
224 .name(name() + ".COM:bw_lim_events")
225 .desc("number cycles where commit BW limit reached")
226 ;
227}
228
229template <class Impl>
230void
231DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
232{
233 thread = threads;
234}
235
236template <class Impl>
237void
238DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
239{
240 timeBuffer = tb_ptr;
241
242 // Setup wire to send information back to IEW.
243 toIEW = timeBuffer->getWire(0);
244
245 // Setup wire to read data from IEW (for the ROB).
246 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
247}
248
249template <class Impl>
250void
251DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
252{
253 fetchQueue = fq_ptr;
254
255 // Setup wire to get instructions from rename (for the ROB).
256 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
257}
258
259template <class Impl>
260void
261DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
262{
263 renameQueue = rq_ptr;
264
265 // Setup wire to get instructions from rename (for the ROB).
266 fromRename = renameQueue->getWire(-renameToROBDelay);
267}
268
269template <class Impl>
270void
271DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
272{
273 iewQueue = iq_ptr;
274
275 // Setup wire to get instructions from IEW.
276 fromIEW = iewQueue->getWire(-iewToCommitDelay);
277}
278
279template <class Impl>
280void
281DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
282{
283 iewStage = iew_stage;
284}
285
286template<class Impl>
287void
288DefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
289{
290 activeThreads = at_ptr;
291}
292
293template <class Impl>
294void
295DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
296{
297 for (int i=0; i < numThreads; i++) {
298 renameMap[i] = &rm_ptr[i];
299 }
300}
301
302template <class Impl>
303void
304DefaultCommit<Impl>::setROB(ROB *rob_ptr)
305{
306 rob = rob_ptr;
307}
308
309template <class Impl>
310void
311DefaultCommit<Impl>::initStage()
312{
313 rob->setActiveThreads(activeThreads);
314 rob->resetEntries();
315
316 // Broadcast the number of free entries.
317 for (int i=0; i < numThreads; i++) {
318 toIEW->commitInfo[i].usedROB = true;
319 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
320 toIEW->commitInfo[i].emptyROB = true;
321 }
322
323 // Commit must broadcast the number of free entries it has at the
324 // start of the simulation, so it starts as active.
325 cpu->activateStage(O3CPU::CommitIdx);
326
327 cpu->activityThisCycle();
328 trapLatency = cpu->ticks(trapLatency);
329}
330
331template <class Impl>
332bool
333DefaultCommit<Impl>::drain()
334{
335 drainPending = true;
336
337 return false;
338}
339
340template <class Impl>
341void
342DefaultCommit<Impl>::switchOut()
343{
344 switchedOut = true;
345 drainPending = false;
346 rob->switchOut();
347}
348
349template <class Impl>
350void
351DefaultCommit<Impl>::resume()
352{
353 drainPending = false;
354}
355
356template <class Impl>
357void
358DefaultCommit<Impl>::takeOverFrom()
359{
360 switchedOut = false;
361 _status = Active;
362 _nextStatus = Inactive;
363 for (int i=0; i < numThreads; i++) {
364 commitStatus[i] = Idle;
365 changedROBNumEntries[i] = false;
366 trapSquash[i] = false;
367 tcSquash[i] = false;
368 }
369 squashCounter = 0;
370 rob->takeOverFrom();
371}
372
373template <class Impl>
374void
375DefaultCommit<Impl>::updateStatus()
376{
377 // reset ROB changed variable
378 std::list<unsigned>::iterator threads = activeThreads->begin();
379 std::list<unsigned>::iterator end = activeThreads->end();
380
381 while (threads != end) {
382 unsigned tid = *threads++;
383
384 changedROBNumEntries[tid] = false;
385
386 // Also check if any of the threads has a trap pending
387 if (commitStatus[tid] == TrapPending ||
388 commitStatus[tid] == FetchTrapPending) {
389 _nextStatus = Active;
390 }
391 }
392
393 if (_nextStatus == Inactive && _status == Active) {
394 DPRINTF(Activity, "Deactivating stage.\n");
395 cpu->deactivateStage(O3CPU::CommitIdx);
396 } else if (_nextStatus == Active && _status == Inactive) {
397 DPRINTF(Activity, "Activating stage.\n");
398 cpu->activateStage(O3CPU::CommitIdx);
399 }
400
401 _status = _nextStatus;
402}
403
404template <class Impl>
405void
406DefaultCommit<Impl>::setNextStatus()
407{
408 int squashes = 0;
409
410 std::list<unsigned>::iterator threads = activeThreads->begin();
411 std::list<unsigned>::iterator end = activeThreads->end();
412
413 while (threads != end) {
414 unsigned tid = *threads++;
415
416 if (commitStatus[tid] == ROBSquashing) {
417 squashes++;
418 }
419 }
420
421 squashCounter = squashes;
422
423 // If commit is currently squashing, then it will have activity for the
424 // next cycle. Set its next status as active.
425 if (squashCounter) {
426 _nextStatus = Active;
427 }
428}
429
430template <class Impl>
431bool
432DefaultCommit<Impl>::changedROBEntries()
433{
434 std::list<unsigned>::iterator threads = activeThreads->begin();
435 std::list<unsigned>::iterator end = activeThreads->end();
436
437 while (threads != end) {
438 unsigned tid = *threads++;
439
440 if (changedROBNumEntries[tid]) {
441 return true;
442 }
443 }
444
445 return false;
446}
447
448template <class Impl>
449unsigned
450DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
451{
452 return rob->numFreeEntries(tid);
453}
454
455template <class Impl>
456void
457DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
458{
459 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
460
461 TrapEvent *trap = new TrapEvent(this, tid);
462
463 trap->schedule(curTick + trapLatency);
464 trapInFlight[tid] = true;
465}
466
467template <class Impl>
468void
469DefaultCommit<Impl>::generateTCEvent(unsigned tid)
470{
471 assert(!trapInFlight[tid]);
472 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
473
474 tcSquash[tid] = true;
475}
476
477template <class Impl>
478void
479DefaultCommit<Impl>::squashAll(unsigned tid)
480{
481 // If we want to include the squashing instruction in the squash,
482 // then use one older sequence number.
483 // Hopefully this doesn't mess things up. Basically I want to squash
484 // all instructions of this thread.
485 InstSeqNum squashed_inst = rob->isEmpty() ?
486 0 : rob->readHeadInst(tid)->seqNum - 1;
487
488 // All younger instructions will be squashed. Set the sequence
489 // number as the youngest instruction in the ROB (0 in this case.
490 // Hopefully nothing breaks.)
491 youngestSeqNum[tid] = 0;
492
493 rob->squash(squashed_inst, tid);
494 changedROBNumEntries[tid] = true;
495
496 // Send back the sequence number of the squashed instruction.
497 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
498
499 // Send back the squash signal to tell stages that they should
500 // squash.
501 toIEW->commitInfo[tid].squash = true;
502
503 // Send back the rob squashing signal so other stages know that
504 // the ROB is in the process of squashing.
505 toIEW->commitInfo[tid].robSquashing = true;
506
507 toIEW->commitInfo[tid].branchMispredict = false;
508
509 toIEW->commitInfo[tid].nextPC = PC[tid];
510 toIEW->commitInfo[tid].nextNPC = nextPC[tid];
511 toIEW->commitInfo[tid].nextMicroPC = nextMicroPC[tid];
512}
513
514template <class Impl>
515void
516DefaultCommit<Impl>::squashFromTrap(unsigned tid)
517{
518 squashAll(tid);
519
520 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
521
522 thread[tid]->trapPending = false;
523 thread[tid]->inSyscall = false;
524 trapInFlight[tid] = false;
525
526 trapSquash[tid] = false;
527
528 commitStatus[tid] = ROBSquashing;
529 cpu->activityThisCycle();
530}
531
532template <class Impl>
533void
534DefaultCommit<Impl>::squashFromTC(unsigned tid)
535{
536 squashAll(tid);
537
538 DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
539
540 thread[tid]->inSyscall = false;
541 assert(!thread[tid]->trapPending);
542
543 commitStatus[tid] = ROBSquashing;
544 cpu->activityThisCycle();
545
546 tcSquash[tid] = false;
547}
548
549template <class Impl>
550void
551DefaultCommit<Impl>::tick()
552{
553 wroteToTimeBuffer = false;
554 _nextStatus = Inactive;
555
556 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
557 cpu->signalDrained();
558 drainPending = false;
559 return;
560 }
561
562 if (activeThreads->empty())
563 return;
564
565 std::list<unsigned>::iterator threads = activeThreads->begin();
566 std::list<unsigned>::iterator end = activeThreads->end();
567
568 // Check if any of the threads are done squashing. Change the
569 // status if they are done.
570 while (threads != end) {
571 unsigned tid = *threads++;
572
573 // Clear the bit saying if the thread has committed stores
574 // this cycle.
575 committedStores[tid] = false;
576
577 if (commitStatus[tid] == ROBSquashing) {
578
579 if (rob->isDoneSquashing(tid)) {
580 commitStatus[tid] = Running;
581 } else {
582 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
583 " insts this cycle.\n", tid);
584 rob->doSquash(tid);
585 toIEW->commitInfo[tid].robSquashing = true;
586 wroteToTimeBuffer = true;
587 }
588 }
589 }
590
591 commit();
592
593 markCompletedInsts();
594
595 threads = activeThreads->begin();
596
597 while (threads != end) {
598 unsigned tid = *threads++;
599
600 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
601 // The ROB has more instructions it can commit. Its next status
602 // will be active.
603 _nextStatus = Active;
604
605 DynInstPtr inst = rob->readHeadInst(tid);
606
607 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
608 " ROB and ready to commit\n",
609 tid, inst->seqNum, inst->readPC());
610
611 } else if (!rob->isEmpty(tid)) {
612 DynInstPtr inst = rob->readHeadInst(tid);
613
614 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
615 "%#x is head of ROB and not ready\n",
616 tid, inst->seqNum, inst->readPC());
617 }
618
619 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
620 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
621 }
622
623
624 if (wroteToTimeBuffer) {
625 DPRINTF(Activity, "Activity This Cycle.\n");
626 cpu->activityThisCycle();
627 }
628
629 updateStatus();
630}
631
632#if FULL_SYSTEM
633template <class Impl>
634void
635DefaultCommit<Impl>::handleInterrupt()
636{
637 if (interrupt != NoFault) {
638 // Wait until the ROB is empty and all stores have drained in
639 // order to enter the interrupt.
640 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
641 // Squash or record that I need to squash this cycle if
642 // an interrupt needed to be handled.
643 DPRINTF(Commit, "Interrupt detected.\n");
644
645 // Clear the interrupt now that it's going to be handled
646 toIEW->commitInfo[0].clearInterrupt = true;
647
648 assert(!thread[0]->inSyscall);
649 thread[0]->inSyscall = true;
650
651 // CPU will handle interrupt.
652 cpu->processInterrupts(interrupt);
653
654 thread[0]->inSyscall = false;
655
656 commitStatus[0] = TrapPending;
657
658 // Generate trap squash event.
659 generateTrapEvent(0);
660
661 interrupt = NoFault;
662 } else {
663 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
664 }
665 } else if (commitStatus[0] != TrapPending &&
666 cpu->check_interrupts(cpu->tcBase(0)) &&
667 !trapSquash[0] &&
668 !tcSquash[0]) {
669 // Process interrupts if interrupts are enabled, not in PAL
670 // mode, and no other traps or external squashes are currently
671 // pending.
672 // @todo: Allow other threads to handle interrupts.
673
674 // Get any interrupt that happened
675 interrupt = cpu->getInterrupts();
676
677 if (interrupt != NoFault) {
678 // Tell fetch that there is an interrupt pending. This
679 // will make fetch wait until it sees a non PAL-mode PC,
680 // at which point it stops fetching instructions.
681 toIEW->commitInfo[0].interruptPending = true;
682 }
683 }
684}
685#endif // FULL_SYSTEM
686
687template <class Impl>
688void
689DefaultCommit<Impl>::commit()
690{
691
692#if FULL_SYSTEM
693 // Check for any interrupt, and start processing it. Or if we
694 // have an outstanding interrupt and are at a point when it is
695 // valid to take an interrupt, process it.
696 if (cpu->check_interrupts(cpu->tcBase(0))) {
697 handleInterrupt();
698 }
699#endif // FULL_SYSTEM
700
701 ////////////////////////////////////
702 // Check for any possible squashes, handle them first
703 ////////////////////////////////////
704 std::list<unsigned>::iterator threads = activeThreads->begin();
705 std::list<unsigned>::iterator end = activeThreads->end();
706
707 while (threads != end) {
708 unsigned tid = *threads++;
709
710 // Not sure which one takes priority. I think if we have
711 // both, that's a bad sign.
712 if (trapSquash[tid] == true) {
713 assert(!tcSquash[tid]);
714 squashFromTrap(tid);
715 } else if (tcSquash[tid] == true) {
716 assert(commitStatus[tid] != TrapPending);
717 squashFromTC(tid);
718 }
719
720 // Squashed sequence number must be older than youngest valid
721 // instruction in the ROB. This prevents squashes from younger
722 // instructions overriding squashes from older instructions.
723 if (fromIEW->squash[tid] &&
724 commitStatus[tid] != TrapPending &&
725 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
726
727 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
728 tid,
729 fromIEW->mispredPC[tid],
730 fromIEW->squashedSeqNum[tid]);
731
732 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
733 tid,
734 fromIEW->nextPC[tid]);
735
736 commitStatus[tid] = ROBSquashing;
737
738 // If we want to include the squashing instruction in the squash,
739 // then use one older sequence number.
740 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
741
742 if (fromIEW->includeSquashInst[tid] == true) {
743 squashed_inst--;
744 }
745
746 // All younger instructions will be squashed. Set the sequence
747 // number as the youngest instruction in the ROB.
748 youngestSeqNum[tid] = squashed_inst;
749
750 rob->squash(squashed_inst, tid);
751 changedROBNumEntries[tid] = true;
752
753 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
754
755 toIEW->commitInfo[tid].squash = true;
756
757 // Send back the rob squashing signal so other stages know that
758 // the ROB is in the process of squashing.
759 toIEW->commitInfo[tid].robSquashing = true;
760
761 toIEW->commitInfo[tid].branchMispredict =
762 fromIEW->branchMispredict[tid];
763
764 toIEW->commitInfo[tid].branchTaken =
765 fromIEW->branchTaken[tid];
766
767 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
768 toIEW->commitInfo[tid].nextNPC = fromIEW->nextNPC[tid];
769 toIEW->commitInfo[tid].nextMicroPC = fromIEW->nextMicroPC[tid];
770
771 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
772
773 if (toIEW->commitInfo[tid].branchMispredict) {
774 ++branchMispredicts;
775 }
776 }
777
778 }
779
780 setNextStatus();
781
782 if (squashCounter != numThreads) {
783 // If we're not currently squashing, then get instructions.
784 getInsts();
785
786 // Try to commit any instructions.
787 commitInsts();
788 }
789
790 //Check for any activity
791 threads = activeThreads->begin();
792
793 while (threads != end) {
794 unsigned tid = *threads++;
795
796 if (changedROBNumEntries[tid]) {
797 toIEW->commitInfo[tid].usedROB = true;
798 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
799
800 wroteToTimeBuffer = true;
801 changedROBNumEntries[tid] = false;
802 if (rob->isEmpty(tid))
803 checkEmptyROB[tid] = true;
804 }
805
806 // ROB is only considered "empty" for previous stages if: a)
807 // ROB is empty, b) there are no outstanding stores, c) IEW
808 // stage has received any information regarding stores that
809 // committed.
810 // c) is checked by making sure to not consider the ROB empty
811 // on the same cycle as when stores have been committed.
812 // @todo: Make this handle multi-cycle communication between
813 // commit and IEW.
814 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
815 !iewStage->hasStoresToWB() && !committedStores[tid]) {
816 checkEmptyROB[tid] = false;
817 toIEW->commitInfo[tid].usedROB = true;
818 toIEW->commitInfo[tid].emptyROB = true;
819 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
820 wroteToTimeBuffer = true;
821 }
822
823 }
824}
825
826template <class Impl>
827void
828DefaultCommit<Impl>::commitInsts()
829{
830 ////////////////////////////////////
831 // Handle commit
832 // Note that commit will be handled prior to putting new
833 // instructions in the ROB so that the ROB only tries to commit
834 // instructions it has in this current cycle, and not instructions
835 // it is writing in during this cycle. Can't commit and squash
836 // things at the same time...
837 ////////////////////////////////////
838
839 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
840
841 unsigned num_committed = 0;
842
843 DynInstPtr head_inst;
844
845 // Commit as many instructions as possible until the commit bandwidth
846 // limit is reached, or it becomes impossible to commit any more.
847 while (num_committed < commitWidth) {
848 int commit_thread = getCommittingThread();
849
850 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
851 break;
852
853 head_inst = rob->readHeadInst(commit_thread);
854
855 int tid = head_inst->threadNumber;
856
857 assert(tid == commit_thread);
858
859 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
860 head_inst->seqNum, tid);
861
862 // If the head instruction is squashed, it is ready to retire
863 // (be removed from the ROB) at any time.
864 if (head_inst->isSquashed()) {
865
866 DPRINTF(Commit, "Retiring squashed instruction from "
867 "ROB.\n");
868
869 rob->retireHead(commit_thread);
870
871 ++commitSquashedInsts;
872
873 // Record that the number of ROB entries has changed.
874 changedROBNumEntries[tid] = true;
875 } else {
876 PC[tid] = head_inst->readPC();
877 nextPC[tid] = head_inst->readNextPC();
878 nextNPC[tid] = head_inst->readNextNPC();
879 nextMicroPC[tid] = head_inst->readNextMicroPC();
880
881 // Increment the total number of non-speculative instructions
882 // executed.
883 // Hack for now: it really shouldn't happen until after the
884 // commit is deemed to be successful, but this count is needed
885 // for syscalls.
886 thread[tid]->funcExeInst++;
887
888 // Try to commit the head instruction.
889 bool commit_success = commitHead(head_inst, num_committed);
890
891 if (commit_success) {
892 ++num_committed;
893
894 changedROBNumEntries[tid] = true;
895
896 // Set the doneSeqNum to the youngest committed instruction.
897 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
898
899 ++commitCommittedInsts;
900
901 // To match the old model, don't count nops and instruction
902 // prefetches towards the total commit count.
903 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
904 cpu->instDone(tid);
905 }
906
907 PC[tid] = nextPC[tid];
908 nextPC[tid] = nextNPC[tid];
909 nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
910 microPC[tid] = nextMicroPC[tid];
911 nextMicroPC[tid] = microPC[tid] + 1;
912
913 int count = 0;
914 Addr oldpc;
915 // Debug statement. Checks to make sure we're not
916 // currently updating state while handling PC events.
917 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
918 do {
919 oldpc = PC[tid];
920 cpu->system->pcEventQueue.service(thread[tid]->getTC());
921 count++;
922 } while (oldpc != PC[tid]);
923 if (count > 1) {
924 DPRINTF(Commit,
925 "PC skip function event, stopping commit\n");
926 break;
927 }
928 } else {
929 DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
930 "[tid:%i] [sn:%i].\n",
931 head_inst->readPC(), tid ,head_inst->seqNum);
932 break;
933 }
934 }
935 }
936
937 DPRINTF(CommitRate, "%i\n", num_committed);
938 numCommittedDist.sample(num_committed);
939
940 if (num_committed == commitWidth) {
941 commitEligibleSamples++;
942 }
943}
944
945template <class Impl>
946bool
947DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
948{
949 assert(head_inst);
950
951 int tid = head_inst->threadNumber;
952
953 // If the instruction is not executed yet, then it will need extra
954 // handling. Signal backwards that it should be executed.
955 if (!head_inst->isExecuted()) {
956 // Keep this number correct. We have not yet actually executed
957 // and committed this instruction.
958 thread[tid]->funcExeInst--;
959
960 if (head_inst->isNonSpeculative() ||
961 head_inst->isStoreConditional() ||
962 head_inst->isMemBarrier() ||
963 head_inst->isWriteBarrier()) {
964
965 DPRINTF(Commit, "Encountered a barrier or non-speculative "
966 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
967 head_inst->seqNum, head_inst->readPC());
968
969 if (inst_num > 0 || iewStage->hasStoresToWB()) {
970 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
971 return false;
972 }
973
974 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
975
976 // Change the instruction so it won't try to commit again until
977 // it is executed.
978 head_inst->clearCanCommit();
979
980 ++commitNonSpecStalls;
981
982 return false;
983 } else if (head_inst->isLoad()) {
984 if (inst_num > 0 || iewStage->hasStoresToWB()) {
985 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
986 return false;
987 }
988
989 assert(head_inst->uncacheable());
990 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
991 head_inst->seqNum, head_inst->readPC());
992
993 // Send back the non-speculative instruction's sequence
994 // number. Tell the lsq to re-execute the load.
995 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
996 toIEW->commitInfo[tid].uncached = true;
997 toIEW->commitInfo[tid].uncachedLoad = head_inst;
998
999 head_inst->clearCanCommit();
1000
1001 return false;
1002 } else {
1003 panic("Trying to commit un-executed instruction "
1004 "of unknown type!\n");
1005 }
1006 }
1007
1008 if (head_inst->isThreadSync()) {
1009 // Not handled for now.
1010 panic("Thread sync instructions are not handled yet.\n");
1011 }
1012
1013 // Check if the instruction caused a fault. If so, trap.
1014 Fault inst_fault = head_inst->getFault();
1015
1016 // Stores mark themselves as completed.
1017 if (!head_inst->isStore() && inst_fault == NoFault) {
1018 head_inst->setCompleted();
1019 }
1020
1021#if USE_CHECKER
1022 // Use checker prior to updating anything due to traps or PC
1023 // based events.
1024 if (cpu->checker) {
1025 cpu->checker->verify(head_inst);
1026 }
1027#endif
1028
1029 // DTB will sometimes need the machine instruction for when
1030 // faults happen. So we will set it here, prior to the DTB
1031 // possibly needing it for its fault.
1032 thread[tid]->setInst(
1033 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1034
1035 if (inst_fault != NoFault) {
1036 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1037 head_inst->seqNum, head_inst->readPC());
1038
1039 if (iewStage->hasStoresToWB() || inst_num > 0) {
1040 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1041 return false;
1042 }
1043
1044 head_inst->setCompleted();
1045
1046#if USE_CHECKER
1047 if (cpu->checker && head_inst->isStore()) {
1048 cpu->checker->verify(head_inst);
1049 }
1050#endif
1051
1052 assert(!thread[tid]->inSyscall);
1053
1054 // Mark that we're in state update mode so that the trap's
1055 // execution doesn't generate extra squashes.
1056 thread[tid]->inSyscall = true;
1057
1058 // Execute the trap. Although it's slightly unrealistic in
1059 // terms of timing (as it doesn't wait for the full timing of
1060 // the trap event to complete before updating state), it's
1061 // needed to update the state as soon as possible. This
1062 // prevents external agents from changing any specific state
1063 // that the trap need.
1064 cpu->trap(inst_fault, tid);
1065
1066 // Exit state update mode to avoid accidental updating.
1067 thread[tid]->inSyscall = false;
1068
1069 commitStatus[tid] = TrapPending;
1070
1071 if (head_inst->traceData) {
1072 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1073 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1074 head_inst->traceData->dump();
1075 delete head_inst->traceData;
1076 head_inst->traceData = NULL;
1077 }
1078
1079 // Generate trap squash event.
1080 generateTrapEvent(tid);
1081// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC());
1082 return false;
1083 }
1084
1085 updateComInstStats(head_inst);
1086
1087#if FULL_SYSTEM
1088 if (thread[tid]->profile) {
1089// bool usermode = TheISA::inUserMode(thread[tid]->getTC());
1090// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC();
1091 thread[tid]->profilePC = head_inst->readPC();
1092 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1093 head_inst->staticInst);
1094
1095 if (node)
1096 thread[tid]->profileNode = node;
1097 }
1098#endif
1099
1100 if (head_inst->traceData) {
1101 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1102 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1103 head_inst->traceData->dump();
1104 delete head_inst->traceData;
1105 head_inst->traceData = NULL;
1106 }
1107
1108 // Update the commit rename map
1109 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1110 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1111 head_inst->renamedDestRegIdx(i));
1112 }
1113
1114 if (head_inst->isCopy())
1115 panic("Should not commit any copy instructions!");
1116
1117 // Finally clear the head ROB entry.
1118 rob->retireHead(tid);
1119
1120 // If this was a store, record it for this cycle.
1121 if (head_inst->isStore())
1122 committedStores[tid] = true;
1123
1124 // Return true to indicate that we have committed an instruction.
1125 return true;
1126}
1127
1128template <class Impl>
1129void
1130DefaultCommit<Impl>::getInsts()
1131{
1132 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1133
1134 // Read any renamed instructions and place them into the ROB.
1135 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1136
1137 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1138 DynInstPtr inst;
1139
1140 inst = fromRename->insts[inst_num];
1141 int tid = inst->threadNumber;
1142
1143 if (!inst->isSquashed() &&
1144 commitStatus[tid] != ROBSquashing &&
1145 commitStatus[tid] != TrapPending) {
1146 changedROBNumEntries[tid] = true;
1147
1148 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1149 inst->readPC(), inst->seqNum, tid);
1150
1151 rob->insertInst(inst);
1152
1153 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1154
1155 youngestSeqNum[tid] = inst->seqNum;
1156 } else {
1157 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1158 "squashed, skipping.\n",
1159 inst->readPC(), inst->seqNum, tid);
1160 }
1161 }
1162}
1163
1164template <class Impl>
1165void
1166DefaultCommit<Impl>::skidInsert()
1167{
1168 DPRINTF(Commit, "Attempting to any instructions from rename into "
1169 "skidBuffer.\n");
1170
1171 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1172 DynInstPtr inst = fromRename->insts[inst_num];
1173
1174 if (!inst->isSquashed()) {
1175 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1176 "skidBuffer.\n", inst->readPC(), inst->seqNum,
1177 inst->threadNumber);
1178 skidBuffer.push(inst);
1179 } else {
1180 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1181 "squashed, skipping.\n",
1182 inst->readPC(), inst->seqNum, inst->threadNumber);
1183 }
1184 }
1185}
1186
1187template <class Impl>
1188void
1189DefaultCommit<Impl>::markCompletedInsts()
1190{
1191 // Grab completed insts out of the IEW instruction queue, and mark
1192 // instructions completed within the ROB.
1193 for (int inst_num = 0;
1194 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1195 ++inst_num)
1196 {
1197 if (!fromIEW->insts[inst_num]->isSquashed()) {
1198 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1199 "within ROB.\n",
1200 fromIEW->insts[inst_num]->threadNumber,
1201 fromIEW->insts[inst_num]->readPC(),
1202 fromIEW->insts[inst_num]->seqNum);
1203
1204 // Mark the instruction as ready to commit.
1205 fromIEW->insts[inst_num]->setCanCommit();
1206 }
1207 }
1208}
1209
1210template <class Impl>
1211bool
1212DefaultCommit<Impl>::robDoneSquashing()
1213{
1214 std::list<unsigned>::iterator threads = activeThreads->begin();
1215 std::list<unsigned>::iterator end = activeThreads->end();
1216
1217 while (threads != end) {
1218 unsigned tid = *threads++;
1219
1220 if (!rob->isDoneSquashing(tid))
1221 return false;
1222 }
1223
1224 return true;
1225}
1226
1227template <class Impl>
1228void
1229DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1230{
1231 unsigned thread = inst->threadNumber;
1232
1233 //
1234 // Pick off the software prefetches
1235 //
1236#ifdef TARGET_ALPHA
1237 if (inst->isDataPrefetch()) {
1238 statComSwp[thread]++;
1239 } else {
1240 statComInst[thread]++;
1241 }
1242#else
1243 statComInst[thread]++;
1244#endif
1245
1246 //
1247 // Control Instructions
1248 //
1249 if (inst->isControl())
1250 statComBranches[thread]++;
1251
1252 //
1253 // Memory references
1254 //
1255 if (inst->isMemRef()) {
1256 statComRefs[thread]++;
1257
1258 if (inst->isLoad()) {
1259 statComLoads[thread]++;
1260 }
1261 }
1262
1263 if (inst->isMemBarrier()) {
1264 statComMembars[thread]++;
1265 }
1266}
1267
1268////////////////////////////////////////
1269// //
1270// SMT COMMIT POLICY MAINTAINED HERE //
1271// //
1272////////////////////////////////////////
1273template <class Impl>
1274int
1275DefaultCommit<Impl>::getCommittingThread()
1276{
1277 if (numThreads > 1) {
1278 switch (commitPolicy) {
1279
1280 case Aggressive:
1281 //If Policy is Aggressive, commit will call
1282 //this function multiple times per
1283 //cycle
1284 return oldestReady();
1285
1286 case RoundRobin:
1287 return roundRobin();
1288
1289 case OldestReady:
1290 return oldestReady();
1291
1292 default:
1293 return -1;
1294 }
1295 } else {
1296 assert(!activeThreads->empty());
1297 int tid = activeThreads->front();
1298
1299 if (commitStatus[tid] == Running ||
1300 commitStatus[tid] == Idle ||
1301 commitStatus[tid] == FetchTrapPending) {
1302 return tid;
1303 } else {
1304 return -1;
1305 }
1306 }
1307}
1308
1309template<class Impl>
1310int
1311DefaultCommit<Impl>::roundRobin()
1312{
1313 std::list<unsigned>::iterator pri_iter = priority_list.begin();
1314 std::list<unsigned>::iterator end = priority_list.end();
1315
1316 while (pri_iter != end) {
1317 unsigned tid = *pri_iter;
1318
1319 if (commitStatus[tid] == Running ||
1320 commitStatus[tid] == Idle ||
1321 commitStatus[tid] == FetchTrapPending) {
1322
1323 if (rob->isHeadReady(tid)) {
1324 priority_list.erase(pri_iter);
1325 priority_list.push_back(tid);
1326
1327 return tid;
1328 }
1329 }
1330
1331 pri_iter++;
1332 }
1333
1334 return -1;
1335}
1336
1337template<class Impl>
1338int
1339DefaultCommit<Impl>::oldestReady()
1340{
1341 unsigned oldest = 0;
1342 bool first = true;
1343
1344 std::list<unsigned>::iterator threads = activeThreads->begin();
1345 std::list<unsigned>::iterator end = activeThreads->end();
1346
1347 while (threads != end) {
1348 unsigned tid = *threads++;
1349
1350 if (!rob->isEmpty(tid) &&
1351 (commitStatus[tid] == Running ||
1352 commitStatus[tid] == Idle ||
1353 commitStatus[tid] == FetchTrapPending)) {
1354
1355 if (rob->isHeadReady(tid)) {
1356
1357 DynInstPtr head_inst = rob->readHeadInst(tid);
1358
1359 if (first) {
1360 oldest = tid;
1361 first = false;
1362 } else if (head_inst->seqNum < oldest) {
1363 oldest = tid;
1364 }
1365 }
1366 }
1367 }
1368
1369 if (!first) {
1370 return oldest;
1371 } else {
1372 return -1;
1373 }
1374}
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