1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
35#include <algorithm>
36#include <string>
37
38#include "arch/utility.hh"
39#include "base/loader/symtab.hh"
40#include "base/timebuf.hh"
41#include "cpu/exetrace.hh"
42#include "cpu/o3/commit.hh"
43#include "cpu/o3/thread_state.hh"
44
45#if USE_CHECKER
46#include "cpu/checker/cpu.hh"
47#endif
48
49template <class Impl>
50DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
51 unsigned _tid)
52 : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
53{
54 this->setFlags(Event::AutoDelete);
55}
56
57template <class Impl>
58void
59DefaultCommit<Impl>::TrapEvent::process()
60{
61 // This will get reset by commit if it was switched out at the
62 // time of this event processing.
63 commit->trapSquash[tid] = true;
64}
65
66template <class Impl>
67const char *
68DefaultCommit<Impl>::TrapEvent::description()
69{
70 return "Trap event";
71}
72
73template <class Impl>
74DefaultCommit<Impl>::DefaultCommit(Params *params)
75 : squashCounter(0),
76 iewToCommitDelay(params->iewToCommitDelay),
77 commitToIEWDelay(params->commitToIEWDelay),
78 renameToROBDelay(params->renameToROBDelay),
79 fetchToCommitDelay(params->commitToFetchDelay),
80 renameWidth(params->renameWidth),
81 commitWidth(params->commitWidth),
82 numThreads(params->numberOfThreads),
83 drainPending(false),
84 switchedOut(false),
85 trapLatency(params->trapLatency)
86{
87 _status = Active;
88 _nextStatus = Inactive;
89 std::string policy = params->smtCommitPolicy;
90
91 //Convert string to lowercase
92 std::transform(policy.begin(), policy.end(), policy.begin(),
93 (int(*)(int)) tolower);
94
95 //Assign commit policy
96 if (policy == "aggressive"){
97 commitPolicy = Aggressive;
98
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
35#include <algorithm>
36#include <string>
37
38#include "arch/utility.hh"
39#include "base/loader/symtab.hh"
40#include "base/timebuf.hh"
41#include "cpu/exetrace.hh"
42#include "cpu/o3/commit.hh"
43#include "cpu/o3/thread_state.hh"
44
45#if USE_CHECKER
46#include "cpu/checker/cpu.hh"
47#endif
48
49template <class Impl>
50DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
51 unsigned _tid)
52 : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
53{
54 this->setFlags(Event::AutoDelete);
55}
56
57template <class Impl>
58void
59DefaultCommit<Impl>::TrapEvent::process()
60{
61 // This will get reset by commit if it was switched out at the
62 // time of this event processing.
63 commit->trapSquash[tid] = true;
64}
65
66template <class Impl>
67const char *
68DefaultCommit<Impl>::TrapEvent::description()
69{
70 return "Trap event";
71}
72
73template <class Impl>
74DefaultCommit<Impl>::DefaultCommit(Params *params)
75 : squashCounter(0),
76 iewToCommitDelay(params->iewToCommitDelay),
77 commitToIEWDelay(params->commitToIEWDelay),
78 renameToROBDelay(params->renameToROBDelay),
79 fetchToCommitDelay(params->commitToFetchDelay),
80 renameWidth(params->renameWidth),
81 commitWidth(params->commitWidth),
82 numThreads(params->numberOfThreads),
83 drainPending(false),
84 switchedOut(false),
85 trapLatency(params->trapLatency)
86{
87 _status = Active;
88 _nextStatus = Inactive;
89 std::string policy = params->smtCommitPolicy;
90
91 //Convert string to lowercase
92 std::transform(policy.begin(), policy.end(), policy.begin(),
93 (int(*)(int)) tolower);
94
95 //Assign commit policy
96 if (policy == "aggressive"){
97 commitPolicy = Aggressive;
98
|
327 rob = rob_ptr;
328}
329
330template <class Impl>
331void
332DefaultCommit<Impl>::initStage()
333{
334 rob->setActiveThreads(activeThreads);
335 rob->resetEntries();
336
337 // Broadcast the number of free entries.
338 for (int i=0; i < numThreads; i++) {
339 toIEW->commitInfo[i].usedROB = true;
340 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
341 toIEW->commitInfo[i].emptyROB = true;
342 }
343
344 cpu->activityThisCycle();
345}
346
347template <class Impl>
348bool
349DefaultCommit<Impl>::drain()
350{
351 drainPending = true;
352
353 return false;
354}
355
356template <class Impl>
357void
358DefaultCommit<Impl>::switchOut()
359{
360 switchedOut = true;
361 drainPending = false;
362 rob->switchOut();
363}
364
365template <class Impl>
366void
367DefaultCommit<Impl>::resume()
368{
369 drainPending = false;
370}
371
372template <class Impl>
373void
374DefaultCommit<Impl>::takeOverFrom()
375{
376 switchedOut = false;
377 _status = Active;
378 _nextStatus = Inactive;
379 for (int i=0; i < numThreads; i++) {
380 commitStatus[i] = Idle;
381 changedROBNumEntries[i] = false;
382 trapSquash[i] = false;
383 tcSquash[i] = false;
384 }
385 squashCounter = 0;
386 rob->takeOverFrom();
387}
388
389template <class Impl>
390void
391DefaultCommit<Impl>::updateStatus()
392{
393 // reset ROB changed variable
394 std::list<unsigned>::iterator threads = activeThreads->begin();
395 std::list<unsigned>::iterator end = activeThreads->end();
396
397 while (threads != end) {
398 unsigned tid = *threads++;
399
400 changedROBNumEntries[tid] = false;
401
402 // Also check if any of the threads has a trap pending
403 if (commitStatus[tid] == TrapPending ||
404 commitStatus[tid] == FetchTrapPending) {
405 _nextStatus = Active;
406 }
407 }
408
409 if (_nextStatus == Inactive && _status == Active) {
410 DPRINTF(Activity, "Deactivating stage.\n");
411 cpu->deactivateStage(O3CPU::CommitIdx);
412 } else if (_nextStatus == Active && _status == Inactive) {
413 DPRINTF(Activity, "Activating stage.\n");
414 cpu->activateStage(O3CPU::CommitIdx);
415 }
416
417 _status = _nextStatus;
418}
419
420template <class Impl>
421void
422DefaultCommit<Impl>::setNextStatus()
423{
424 int squashes = 0;
425
426 std::list<unsigned>::iterator threads = activeThreads->begin();
427 std::list<unsigned>::iterator end = activeThreads->end();
428
429 while (threads != end) {
430 unsigned tid = *threads++;
431
432 if (commitStatus[tid] == ROBSquashing) {
433 squashes++;
434 }
435 }
436
437 squashCounter = squashes;
438
439 // If commit is currently squashing, then it will have activity for the
440 // next cycle. Set its next status as active.
441 if (squashCounter) {
442 _nextStatus = Active;
443 }
444}
445
446template <class Impl>
447bool
448DefaultCommit<Impl>::changedROBEntries()
449{
450 std::list<unsigned>::iterator threads = activeThreads->begin();
451 std::list<unsigned>::iterator end = activeThreads->end();
452
453 while (threads != end) {
454 unsigned tid = *threads++;
455
456 if (changedROBNumEntries[tid]) {
457 return true;
458 }
459 }
460
461 return false;
462}
463
464template <class Impl>
465unsigned
466DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
467{
468 return rob->numFreeEntries(tid);
469}
470
471template <class Impl>
472void
473DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
474{
475 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
476
477 TrapEvent *trap = new TrapEvent(this, tid);
478
479 trap->schedule(curTick + trapLatency);
480 trapInFlight[tid] = true;
481}
482
483template <class Impl>
484void
485DefaultCommit<Impl>::generateTCEvent(unsigned tid)
486{
487 assert(!trapInFlight[tid]);
488 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
489
490 tcSquash[tid] = true;
491}
492
493template <class Impl>
494void
495DefaultCommit<Impl>::squashAll(unsigned tid)
496{
497 // If we want to include the squashing instruction in the squash,
498 // then use one older sequence number.
499 // Hopefully this doesn't mess things up. Basically I want to squash
500 // all instructions of this thread.
501 InstSeqNum squashed_inst = rob->isEmpty() ?
502 0 : rob->readHeadInst(tid)->seqNum - 1;
503
504 // All younger instructions will be squashed. Set the sequence
505 // number as the youngest instruction in the ROB (0 in this case.
506 // Hopefully nothing breaks.)
507 youngestSeqNum[tid] = 0;
508
509 rob->squash(squashed_inst, tid);
510 changedROBNumEntries[tid] = true;
511
512 // Send back the sequence number of the squashed instruction.
513 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
514
515 // Send back the squash signal to tell stages that they should
516 // squash.
517 toIEW->commitInfo[tid].squash = true;
518
519 // Send back the rob squashing signal so other stages know that
520 // the ROB is in the process of squashing.
521 toIEW->commitInfo[tid].robSquashing = true;
522
523 toIEW->commitInfo[tid].branchMispredict = false;
524
525 toIEW->commitInfo[tid].nextPC = PC[tid];
526 toIEW->commitInfo[tid].nextNPC = nextPC[tid];
527}
528
529template <class Impl>
530void
531DefaultCommit<Impl>::squashFromTrap(unsigned tid)
532{
533 squashAll(tid);
534
535 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
536
537 thread[tid]->trapPending = false;
538 thread[tid]->inSyscall = false;
539 trapInFlight[tid] = false;
540
541 trapSquash[tid] = false;
542
543 commitStatus[tid] = ROBSquashing;
544 cpu->activityThisCycle();
545}
546
547template <class Impl>
548void
549DefaultCommit<Impl>::squashFromTC(unsigned tid)
550{
551 squashAll(tid);
552
553 DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
554
555 thread[tid]->inSyscall = false;
556 assert(!thread[tid]->trapPending);
557
558 commitStatus[tid] = ROBSquashing;
559 cpu->activityThisCycle();
560
561 tcSquash[tid] = false;
562}
563
564template <class Impl>
565void
566DefaultCommit<Impl>::tick()
567{
568 wroteToTimeBuffer = false;
569 _nextStatus = Inactive;
570
571 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
572 cpu->signalDrained();
573 drainPending = false;
574 return;
575 }
576
577 if (activeThreads->empty())
578 return;
579
580 std::list<unsigned>::iterator threads = activeThreads->begin();
581 std::list<unsigned>::iterator end = activeThreads->end();
582
583 // Check if any of the threads are done squashing. Change the
584 // status if they are done.
585 while (threads != end) {
586 unsigned tid = *threads++;
587
588 // Clear the bit saying if the thread has committed stores
589 // this cycle.
590 committedStores[tid] = false;
591
592 if (commitStatus[tid] == ROBSquashing) {
593
594 if (rob->isDoneSquashing(tid)) {
595 commitStatus[tid] = Running;
596 } else {
597 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
598 " insts this cycle.\n", tid);
599 rob->doSquash(tid);
600 toIEW->commitInfo[tid].robSquashing = true;
601 wroteToTimeBuffer = true;
602 }
603 }
604 }
605
606 commit();
607
608 markCompletedInsts();
609
610 threads = activeThreads->begin();
611
612 while (threads != end) {
613 unsigned tid = *threads++;
614
615 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
616 // The ROB has more instructions it can commit. Its next status
617 // will be active.
618 _nextStatus = Active;
619
620 DynInstPtr inst = rob->readHeadInst(tid);
621
622 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
623 " ROB and ready to commit\n",
624 tid, inst->seqNum, inst->readPC());
625
626 } else if (!rob->isEmpty(tid)) {
627 DynInstPtr inst = rob->readHeadInst(tid);
628
629 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
630 "%#x is head of ROB and not ready\n",
631 tid, inst->seqNum, inst->readPC());
632 }
633
634 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
635 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
636 }
637
638
639 if (wroteToTimeBuffer) {
640 DPRINTF(Activity, "Activity This Cycle.\n");
641 cpu->activityThisCycle();
642 }
643
644 updateStatus();
645}
646
647#if FULL_SYSTEM
648template <class Impl>
649void
650DefaultCommit<Impl>::handleInterrupt()
651{
652 if (interrupt != NoFault) {
653 // Wait until the ROB is empty and all stores have drained in
654 // order to enter the interrupt.
655 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
656 // Squash or record that I need to squash this cycle if
657 // an interrupt needed to be handled.
658 DPRINTF(Commit, "Interrupt detected.\n");
659
660 Fault new_interrupt = cpu->getInterrupts();
661 assert(new_interrupt != NoFault);
662
663 // Clear the interrupt now that it's going to be handled
664 toIEW->commitInfo[0].clearInterrupt = true;
665
666 assert(!thread[0]->inSyscall);
667 thread[0]->inSyscall = true;
668
669 // CPU will handle interrupt.
670 cpu->processInterrupts(interrupt);
671
672 thread[0]->inSyscall = false;
673
674 commitStatus[0] = TrapPending;
675
676 // Generate trap squash event.
677 generateTrapEvent(0);
678
679 interrupt = NoFault;
680 } else {
681 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
682 }
683 } else if (commitStatus[0] != TrapPending &&
684 cpu->check_interrupts(cpu->tcBase(0)) &&
685 !trapSquash[0] &&
686 !tcSquash[0]) {
687 // Process interrupts if interrupts are enabled, not in PAL
688 // mode, and no other traps or external squashes are currently
689 // pending.
690 // @todo: Allow other threads to handle interrupts.
691
692 // Get any interrupt that happened
693 interrupt = cpu->getInterrupts();
694
695 if (interrupt != NoFault) {
696 // Tell fetch that there is an interrupt pending. This
697 // will make fetch wait until it sees a non PAL-mode PC,
698 // at which point it stops fetching instructions.
699 toIEW->commitInfo[0].interruptPending = true;
700 }
701 }
702}
703#endif // FULL_SYSTEM
704
705template <class Impl>
706void
707DefaultCommit<Impl>::commit()
708{
709
710#if FULL_SYSTEM
711 // Check for any interrupt, and start processing it. Or if we
712 // have an outstanding interrupt and are at a point when it is
713 // valid to take an interrupt, process it.
714 if (cpu->check_interrupts(cpu->tcBase(0))) {
715 handleInterrupt();
716 }
717#endif // FULL_SYSTEM
718
719 ////////////////////////////////////
720 // Check for any possible squashes, handle them first
721 ////////////////////////////////////
722 std::list<unsigned>::iterator threads = activeThreads->begin();
723 std::list<unsigned>::iterator end = activeThreads->end();
724
725 while (threads != end) {
726 unsigned tid = *threads++;
727
728 // Not sure which one takes priority. I think if we have
729 // both, that's a bad sign.
730 if (trapSquash[tid] == true) {
731 assert(!tcSquash[tid]);
732 squashFromTrap(tid);
733 } else if (tcSquash[tid] == true) {
734 assert(commitStatus[tid] != TrapPending);
735 squashFromTC(tid);
736 }
737
738 // Squashed sequence number must be older than youngest valid
739 // instruction in the ROB. This prevents squashes from younger
740 // instructions overriding squashes from older instructions.
741 if (fromIEW->squash[tid] &&
742 commitStatus[tid] != TrapPending &&
743 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
744
745 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
746 tid,
747 fromIEW->mispredPC[tid],
748 fromIEW->squashedSeqNum[tid]);
749
750 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
751 tid,
752 fromIEW->nextPC[tid]);
753
754 commitStatus[tid] = ROBSquashing;
755
756 // If we want to include the squashing instruction in the squash,
757 // then use one older sequence number.
758 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
759
760#if ISA_HAS_DELAY_SLOT
761 InstSeqNum bdelay_done_seq_num = squashed_inst;
762 bool squash_bdelay_slot = fromIEW->squashDelaySlot[tid];
763 bool branchMispredict = fromIEW->branchMispredict[tid];
764
765 // Squashing/not squashing the branch delay slot only makes
766 // sense when you're squashing from a branch, ie from a branch
767 // mispredict.
768 if (branchMispredict && !squash_bdelay_slot) {
769 bdelay_done_seq_num++;
770 }
771#endif
772
773 if (fromIEW->includeSquashInst[tid] == true) {
774 squashed_inst--;
775#if ISA_HAS_DELAY_SLOT
776 bdelay_done_seq_num--;
777#endif
778 }
779
780 // All younger instructions will be squashed. Set the sequence
781 // number as the youngest instruction in the ROB.
782 youngestSeqNum[tid] = squashed_inst;
783
784#if ISA_HAS_DELAY_SLOT
785 rob->squash(bdelay_done_seq_num, tid);
786 toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot;
787 toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num;
788#else
789 rob->squash(squashed_inst, tid);
790 toIEW->commitInfo[tid].squashDelaySlot = true;
791#endif
792 changedROBNumEntries[tid] = true;
793
794 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
795
796 toIEW->commitInfo[tid].squash = true;
797
798 // Send back the rob squashing signal so other stages know that
799 // the ROB is in the process of squashing.
800 toIEW->commitInfo[tid].robSquashing = true;
801
802 toIEW->commitInfo[tid].branchMispredict =
803 fromIEW->branchMispredict[tid];
804
805 toIEW->commitInfo[tid].branchTaken =
806 fromIEW->branchTaken[tid];
807
808 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
809 toIEW->commitInfo[tid].nextNPC = fromIEW->nextNPC[tid];
810
811 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
812
813 if (toIEW->commitInfo[tid].branchMispredict) {
814 ++branchMispredicts;
815 }
816 }
817
818 }
819
820 setNextStatus();
821
822 if (squashCounter != numThreads) {
823 // If we're not currently squashing, then get instructions.
824 getInsts();
825
826 // Try to commit any instructions.
827 commitInsts();
828 } else {
829#if ISA_HAS_DELAY_SLOT
830 skidInsert();
831#endif
832 }
833
834 //Check for any activity
835 threads = activeThreads->begin();
836
837 while (threads != end) {
838 unsigned tid = *threads++;
839
840 if (changedROBNumEntries[tid]) {
841 toIEW->commitInfo[tid].usedROB = true;
842 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
843
844 wroteToTimeBuffer = true;
845 changedROBNumEntries[tid] = false;
846 if (rob->isEmpty(tid))
847 checkEmptyROB[tid] = true;
848 }
849
850 // ROB is only considered "empty" for previous stages if: a)
851 // ROB is empty, b) there are no outstanding stores, c) IEW
852 // stage has received any information regarding stores that
853 // committed.
854 // c) is checked by making sure to not consider the ROB empty
855 // on the same cycle as when stores have been committed.
856 // @todo: Make this handle multi-cycle communication between
857 // commit and IEW.
858 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
859 !iewStage->hasStoresToWB() && !committedStores[tid]) {
860 checkEmptyROB[tid] = false;
861 toIEW->commitInfo[tid].usedROB = true;
862 toIEW->commitInfo[tid].emptyROB = true;
863 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
864 wroteToTimeBuffer = true;
865 }
866
867 }
868}
869
870template <class Impl>
871void
872DefaultCommit<Impl>::commitInsts()
873{
874 ////////////////////////////////////
875 // Handle commit
876 // Note that commit will be handled prior to putting new
877 // instructions in the ROB so that the ROB only tries to commit
878 // instructions it has in this current cycle, and not instructions
879 // it is writing in during this cycle. Can't commit and squash
880 // things at the same time...
881 ////////////////////////////////////
882
883 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
884
885 unsigned num_committed = 0;
886
887 DynInstPtr head_inst;
888
889 // Commit as many instructions as possible until the commit bandwidth
890 // limit is reached, or it becomes impossible to commit any more.
891 while (num_committed < commitWidth) {
892 int commit_thread = getCommittingThread();
893
894 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
895 break;
896
897 head_inst = rob->readHeadInst(commit_thread);
898
899 int tid = head_inst->threadNumber;
900
901 assert(tid == commit_thread);
902
903 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
904 head_inst->seqNum, tid);
905
906 // If the head instruction is squashed, it is ready to retire
907 // (be removed from the ROB) at any time.
908 if (head_inst->isSquashed()) {
909
910 DPRINTF(Commit, "Retiring squashed instruction from "
911 "ROB.\n");
912
913 rob->retireHead(commit_thread);
914
915 ++commitSquashedInsts;
916
917 // Record that the number of ROB entries has changed.
918 changedROBNumEntries[tid] = true;
919 } else {
920 PC[tid] = head_inst->readPC();
921 nextPC[tid] = head_inst->readNextPC();
922 nextNPC[tid] = head_inst->readNextNPC();
923
924 // Increment the total number of non-speculative instructions
925 // executed.
926 // Hack for now: it really shouldn't happen until after the
927 // commit is deemed to be successful, but this count is needed
928 // for syscalls.
929 thread[tid]->funcExeInst++;
930
931 // Try to commit the head instruction.
932 bool commit_success = commitHead(head_inst, num_committed);
933
934 if (commit_success) {
935 ++num_committed;
936
937 changedROBNumEntries[tid] = true;
938
939 // Set the doneSeqNum to the youngest committed instruction.
940 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
941
942 ++commitCommittedInsts;
943
944 // To match the old model, don't count nops and instruction
945 // prefetches towards the total commit count.
946 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
947 cpu->instDone(tid);
948 }
949
950 PC[tid] = nextPC[tid];
951#if ISA_HAS_DELAY_SLOT
952 nextPC[tid] = nextNPC[tid];
953 nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
954#else
955 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
956#endif
957
958#if FULL_SYSTEM
959 int count = 0;
960 Addr oldpc;
961 do {
962 // Debug statement. Checks to make sure we're not
963 // currently updating state while handling PC events.
964 if (count == 0)
965 assert(!thread[tid]->inSyscall &&
966 !thread[tid]->trapPending);
967 oldpc = PC[tid];
968 cpu->system->pcEventQueue.service(
969 thread[tid]->getTC());
970 count++;
971 } while (oldpc != PC[tid]);
972 if (count > 1) {
973 DPRINTF(Commit, "PC skip function event, stopping commit\n");
974 break;
975 }
976#endif
977 } else {
978 DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
979 "[tid:%i] [sn:%i].\n",
980 head_inst->readPC(), tid ,head_inst->seqNum);
981 break;
982 }
983 }
984 }
985
986 DPRINTF(CommitRate, "%i\n", num_committed);
987 numCommittedDist.sample(num_committed);
988
989 if (num_committed == commitWidth) {
990 commitEligibleSamples++;
991 }
992}
993
994template <class Impl>
995bool
996DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
997{
998 assert(head_inst);
999
1000 int tid = head_inst->threadNumber;
1001
1002 // If the instruction is not executed yet, then it will need extra
1003 // handling. Signal backwards that it should be executed.
1004 if (!head_inst->isExecuted()) {
1005 // Keep this number correct. We have not yet actually executed
1006 // and committed this instruction.
1007 thread[tid]->funcExeInst--;
1008
1009 if (head_inst->isNonSpeculative() ||
1010 head_inst->isStoreConditional() ||
1011 head_inst->isMemBarrier() ||
1012 head_inst->isWriteBarrier()) {
1013
1014 DPRINTF(Commit, "Encountered a barrier or non-speculative "
1015 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
1016 head_inst->seqNum, head_inst->readPC());
1017
1018 if (inst_num > 0 || iewStage->hasStoresToWB()) {
1019 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1020 return false;
1021 }
1022
1023 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1024
1025 // Change the instruction so it won't try to commit again until
1026 // it is executed.
1027 head_inst->clearCanCommit();
1028
1029 ++commitNonSpecStalls;
1030
1031 return false;
1032 } else if (head_inst->isLoad()) {
1033 if (inst_num > 0 || iewStage->hasStoresToWB()) {
1034 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1035 return false;
1036 }
1037
1038 assert(head_inst->uncacheable());
1039 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
1040 head_inst->seqNum, head_inst->readPC());
1041
1042 // Send back the non-speculative instruction's sequence
1043 // number. Tell the lsq to re-execute the load.
1044 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1045 toIEW->commitInfo[tid].uncached = true;
1046 toIEW->commitInfo[tid].uncachedLoad = head_inst;
1047
1048 head_inst->clearCanCommit();
1049
1050 return false;
1051 } else {
1052 panic("Trying to commit un-executed instruction "
1053 "of unknown type!\n");
1054 }
1055 }
1056
1057 if (head_inst->isThreadSync()) {
1058 // Not handled for now.
1059 panic("Thread sync instructions are not handled yet.\n");
1060 }
1061
1062 // Check if the instruction caused a fault. If so, trap.
1063 Fault inst_fault = head_inst->getFault();
1064
1065 // Stores mark themselves as completed.
1066 if (!head_inst->isStore() && inst_fault == NoFault) {
1067 head_inst->setCompleted();
1068 }
1069
1070#if USE_CHECKER
1071 // Use checker prior to updating anything due to traps or PC
1072 // based events.
1073 if (cpu->checker) {
1074 cpu->checker->verify(head_inst);
1075 }
1076#endif
1077
1078 // DTB will sometimes need the machine instruction for when
1079 // faults happen. So we will set it here, prior to the DTB
1080 // possibly needing it for its fault.
1081 thread[tid]->setInst(
1082 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1083
1084 if (inst_fault != NoFault) {
1085 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1086 head_inst->seqNum, head_inst->readPC());
1087
1088 if (iewStage->hasStoresToWB() || inst_num > 0) {
1089 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1090 return false;
1091 }
1092
1093 head_inst->setCompleted();
1094
1095#if USE_CHECKER
1096 if (cpu->checker && head_inst->isStore()) {
1097 cpu->checker->verify(head_inst);
1098 }
1099#endif
1100
1101 assert(!thread[tid]->inSyscall);
1102
1103 // Mark that we're in state update mode so that the trap's
1104 // execution doesn't generate extra squashes.
1105 thread[tid]->inSyscall = true;
1106
1107 // Execute the trap. Although it's slightly unrealistic in
1108 // terms of timing (as it doesn't wait for the full timing of
1109 // the trap event to complete before updating state), it's
1110 // needed to update the state as soon as possible. This
1111 // prevents external agents from changing any specific state
1112 // that the trap need.
1113 cpu->trap(inst_fault, tid);
1114
1115 // Exit state update mode to avoid accidental updating.
1116 thread[tid]->inSyscall = false;
1117
1118 commitStatus[tid] = TrapPending;
1119
1120 if (head_inst->traceData) {
1121 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1122 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1123 head_inst->traceData->dump();
1124 delete head_inst->traceData;
1125 head_inst->traceData = NULL;
1126 }
1127
1128 // Generate trap squash event.
1129 generateTrapEvent(tid);
1130// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC());
1131 return false;
1132 }
1133
1134 updateComInstStats(head_inst);
1135
1136#if FULL_SYSTEM
1137 if (thread[tid]->profile) {
1138// bool usermode = TheISA::inUserMode(thread[tid]->getTC());
1139// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC();
1140 thread[tid]->profilePC = head_inst->readPC();
1141 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1142 head_inst->staticInst);
1143
1144 if (node)
1145 thread[tid]->profileNode = node;
1146 }
1147#endif
1148
1149 if (head_inst->traceData) {
1150 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1151 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1152 head_inst->traceData->dump();
1153 delete head_inst->traceData;
1154 head_inst->traceData = NULL;
1155 }
1156
1157 // Update the commit rename map
1158 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1159 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1160 head_inst->renamedDestRegIdx(i));
1161 }
1162
1163 if (head_inst->isCopy())
1164 panic("Should not commit any copy instructions!");
1165
1166 // Finally clear the head ROB entry.
1167 rob->retireHead(tid);
1168
1169 // If this was a store, record it for this cycle.
1170 if (head_inst->isStore())
1171 committedStores[tid] = true;
1172
1173 // Return true to indicate that we have committed an instruction.
1174 return true;
1175}
1176
1177template <class Impl>
1178void
1179DefaultCommit<Impl>::getInsts()
1180{
1181 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1182
1183#if ISA_HAS_DELAY_SLOT
1184 // Read any renamed instructions and place them into the ROB.
1185 int insts_to_process = std::min((int)renameWidth,
1186 (int)(fromRename->size + skidBuffer.size()));
1187 int rename_idx = 0;
1188
1189 DPRINTF(Commit, "%i insts available to process. Rename Insts:%i "
1190 "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size,
1191 skidBuffer.size());
1192#else
1193 // Read any renamed instructions and place them into the ROB.
1194 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1195#endif
1196
1197
1198 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1199 DynInstPtr inst;
1200
1201#if ISA_HAS_DELAY_SLOT
1202 // Get insts from skidBuffer or from Rename
1203 if (skidBuffer.size() > 0) {
1204 DPRINTF(Commit, "Grabbing skidbuffer inst.\n");
1205 inst = skidBuffer.front();
1206 skidBuffer.pop();
1207 } else {
1208 DPRINTF(Commit, "Grabbing rename inst.\n");
1209 inst = fromRename->insts[rename_idx++];
1210 }
1211#else
1212 inst = fromRename->insts[inst_num];
1213#endif
1214 int tid = inst->threadNumber;
1215
1216 if (!inst->isSquashed() &&
1217 commitStatus[tid] != ROBSquashing &&
1218 commitStatus[tid] != TrapPending) {
1219 changedROBNumEntries[tid] = true;
1220
1221 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1222 inst->readPC(), inst->seqNum, tid);
1223
1224 rob->insertInst(inst);
1225
1226 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1227
1228 youngestSeqNum[tid] = inst->seqNum;
1229 } else {
1230 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1231 "squashed, skipping.\n",
1232 inst->readPC(), inst->seqNum, tid);
1233 }
1234 }
1235
1236#if ISA_HAS_DELAY_SLOT
1237 if (rename_idx < fromRename->size) {
1238 DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n");
1239
1240 for (;
1241 rename_idx < fromRename->size;
1242 rename_idx++) {
1243 DynInstPtr inst = fromRename->insts[rename_idx];
1244
1245 if (!inst->isSquashed()) {
1246 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1247 "skidBuffer.\n", inst->readPC(), inst->seqNum,
1248 inst->threadNumber);
1249 skidBuffer.push(inst);
1250 } else {
1251 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1252 "squashed, skipping.\n",
1253 inst->readPC(), inst->seqNum, inst->threadNumber);
1254 }
1255 }
1256 }
1257#endif
1258
1259}
1260
1261template <class Impl>
1262void
1263DefaultCommit<Impl>::skidInsert()
1264{
1265 DPRINTF(Commit, "Attempting to any instructions from rename into "
1266 "skidBuffer.\n");
1267
1268 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1269 DynInstPtr inst = fromRename->insts[inst_num];
1270
1271 if (!inst->isSquashed()) {
1272 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1273 "skidBuffer.\n", inst->readPC(), inst->seqNum,
1274 inst->threadNumber);
1275 skidBuffer.push(inst);
1276 } else {
1277 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1278 "squashed, skipping.\n",
1279 inst->readPC(), inst->seqNum, inst->threadNumber);
1280 }
1281 }
1282}
1283
1284template <class Impl>
1285void
1286DefaultCommit<Impl>::markCompletedInsts()
1287{
1288 // Grab completed insts out of the IEW instruction queue, and mark
1289 // instructions completed within the ROB.
1290 for (int inst_num = 0;
1291 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1292 ++inst_num)
1293 {
1294 if (!fromIEW->insts[inst_num]->isSquashed()) {
1295 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1296 "within ROB.\n",
1297 fromIEW->insts[inst_num]->threadNumber,
1298 fromIEW->insts[inst_num]->readPC(),
1299 fromIEW->insts[inst_num]->seqNum);
1300
1301 // Mark the instruction as ready to commit.
1302 fromIEW->insts[inst_num]->setCanCommit();
1303 }
1304 }
1305}
1306
1307template <class Impl>
1308bool
1309DefaultCommit<Impl>::robDoneSquashing()
1310{
1311 std::list<unsigned>::iterator threads = activeThreads->begin();
1312 std::list<unsigned>::iterator end = activeThreads->end();
1313
1314 while (threads != end) {
1315 unsigned tid = *threads++;
1316
1317 if (!rob->isDoneSquashing(tid))
1318 return false;
1319 }
1320
1321 return true;
1322}
1323
1324template <class Impl>
1325void
1326DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1327{
1328 unsigned thread = inst->threadNumber;
1329
1330 //
1331 // Pick off the software prefetches
1332 //
1333#ifdef TARGET_ALPHA
1334 if (inst->isDataPrefetch()) {
1335 statComSwp[thread]++;
1336 } else {
1337 statComInst[thread]++;
1338 }
1339#else
1340 statComInst[thread]++;
1341#endif
1342
1343 //
1344 // Control Instructions
1345 //
1346 if (inst->isControl())
1347 statComBranches[thread]++;
1348
1349 //
1350 // Memory references
1351 //
1352 if (inst->isMemRef()) {
1353 statComRefs[thread]++;
1354
1355 if (inst->isLoad()) {
1356 statComLoads[thread]++;
1357 }
1358 }
1359
1360 if (inst->isMemBarrier()) {
1361 statComMembars[thread]++;
1362 }
1363}
1364
1365////////////////////////////////////////
1366// //
1367// SMT COMMIT POLICY MAINTAINED HERE //
1368// //
1369////////////////////////////////////////
1370template <class Impl>
1371int
1372DefaultCommit<Impl>::getCommittingThread()
1373{
1374 if (numThreads > 1) {
1375 switch (commitPolicy) {
1376
1377 case Aggressive:
1378 //If Policy is Aggressive, commit will call
1379 //this function multiple times per
1380 //cycle
1381 return oldestReady();
1382
1383 case RoundRobin:
1384 return roundRobin();
1385
1386 case OldestReady:
1387 return oldestReady();
1388
1389 default:
1390 return -1;
1391 }
1392 } else {
1393 assert(!activeThreads->empty());
1394 int tid = activeThreads->front();
1395
1396 if (commitStatus[tid] == Running ||
1397 commitStatus[tid] == Idle ||
1398 commitStatus[tid] == FetchTrapPending) {
1399 return tid;
1400 } else {
1401 return -1;
1402 }
1403 }
1404}
1405
1406template<class Impl>
1407int
1408DefaultCommit<Impl>::roundRobin()
1409{
1410 std::list<unsigned>::iterator pri_iter = priority_list.begin();
1411 std::list<unsigned>::iterator end = priority_list.end();
1412
1413 while (pri_iter != end) {
1414 unsigned tid = *pri_iter;
1415
1416 if (commitStatus[tid] == Running ||
1417 commitStatus[tid] == Idle ||
1418 commitStatus[tid] == FetchTrapPending) {
1419
1420 if (rob->isHeadReady(tid)) {
1421 priority_list.erase(pri_iter);
1422 priority_list.push_back(tid);
1423
1424 return tid;
1425 }
1426 }
1427
1428 pri_iter++;
1429 }
1430
1431 return -1;
1432}
1433
1434template<class Impl>
1435int
1436DefaultCommit<Impl>::oldestReady()
1437{
1438 unsigned oldest = 0;
1439 bool first = true;
1440
1441 std::list<unsigned>::iterator threads = activeThreads->begin();
1442 std::list<unsigned>::iterator end = activeThreads->end();
1443
1444 while (threads != end) {
1445 unsigned tid = *threads++;
1446
1447 if (!rob->isEmpty(tid) &&
1448 (commitStatus[tid] == Running ||
1449 commitStatus[tid] == Idle ||
1450 commitStatus[tid] == FetchTrapPending)) {
1451
1452 if (rob->isHeadReady(tid)) {
1453
1454 DynInstPtr head_inst = rob->readHeadInst(tid);
1455
1456 if (first) {
1457 oldest = tid;
1458 first = false;
1459 } else if (head_inst->seqNum < oldest) {
1460 oldest = tid;
1461 }
1462 }
1463 }
1464 }
1465
1466 if (!first) {
1467 return oldest;
1468 } else {
1469 return -1;
1470 }
1471}
| 319 rob = rob_ptr;
320}
321
322template <class Impl>
323void
324DefaultCommit<Impl>::initStage()
325{
326 rob->setActiveThreads(activeThreads);
327 rob->resetEntries();
328
329 // Broadcast the number of free entries.
330 for (int i=0; i < numThreads; i++) {
331 toIEW->commitInfo[i].usedROB = true;
332 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
333 toIEW->commitInfo[i].emptyROB = true;
334 }
335
336 cpu->activityThisCycle();
337}
338
339template <class Impl>
340bool
341DefaultCommit<Impl>::drain()
342{
343 drainPending = true;
344
345 return false;
346}
347
348template <class Impl>
349void
350DefaultCommit<Impl>::switchOut()
351{
352 switchedOut = true;
353 drainPending = false;
354 rob->switchOut();
355}
356
357template <class Impl>
358void
359DefaultCommit<Impl>::resume()
360{
361 drainPending = false;
362}
363
364template <class Impl>
365void
366DefaultCommit<Impl>::takeOverFrom()
367{
368 switchedOut = false;
369 _status = Active;
370 _nextStatus = Inactive;
371 for (int i=0; i < numThreads; i++) {
372 commitStatus[i] = Idle;
373 changedROBNumEntries[i] = false;
374 trapSquash[i] = false;
375 tcSquash[i] = false;
376 }
377 squashCounter = 0;
378 rob->takeOverFrom();
379}
380
381template <class Impl>
382void
383DefaultCommit<Impl>::updateStatus()
384{
385 // reset ROB changed variable
386 std::list<unsigned>::iterator threads = activeThreads->begin();
387 std::list<unsigned>::iterator end = activeThreads->end();
388
389 while (threads != end) {
390 unsigned tid = *threads++;
391
392 changedROBNumEntries[tid] = false;
393
394 // Also check if any of the threads has a trap pending
395 if (commitStatus[tid] == TrapPending ||
396 commitStatus[tid] == FetchTrapPending) {
397 _nextStatus = Active;
398 }
399 }
400
401 if (_nextStatus == Inactive && _status == Active) {
402 DPRINTF(Activity, "Deactivating stage.\n");
403 cpu->deactivateStage(O3CPU::CommitIdx);
404 } else if (_nextStatus == Active && _status == Inactive) {
405 DPRINTF(Activity, "Activating stage.\n");
406 cpu->activateStage(O3CPU::CommitIdx);
407 }
408
409 _status = _nextStatus;
410}
411
412template <class Impl>
413void
414DefaultCommit<Impl>::setNextStatus()
415{
416 int squashes = 0;
417
418 std::list<unsigned>::iterator threads = activeThreads->begin();
419 std::list<unsigned>::iterator end = activeThreads->end();
420
421 while (threads != end) {
422 unsigned tid = *threads++;
423
424 if (commitStatus[tid] == ROBSquashing) {
425 squashes++;
426 }
427 }
428
429 squashCounter = squashes;
430
431 // If commit is currently squashing, then it will have activity for the
432 // next cycle. Set its next status as active.
433 if (squashCounter) {
434 _nextStatus = Active;
435 }
436}
437
438template <class Impl>
439bool
440DefaultCommit<Impl>::changedROBEntries()
441{
442 std::list<unsigned>::iterator threads = activeThreads->begin();
443 std::list<unsigned>::iterator end = activeThreads->end();
444
445 while (threads != end) {
446 unsigned tid = *threads++;
447
448 if (changedROBNumEntries[tid]) {
449 return true;
450 }
451 }
452
453 return false;
454}
455
456template <class Impl>
457unsigned
458DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
459{
460 return rob->numFreeEntries(tid);
461}
462
463template <class Impl>
464void
465DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
466{
467 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
468
469 TrapEvent *trap = new TrapEvent(this, tid);
470
471 trap->schedule(curTick + trapLatency);
472 trapInFlight[tid] = true;
473}
474
475template <class Impl>
476void
477DefaultCommit<Impl>::generateTCEvent(unsigned tid)
478{
479 assert(!trapInFlight[tid]);
480 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
481
482 tcSquash[tid] = true;
483}
484
485template <class Impl>
486void
487DefaultCommit<Impl>::squashAll(unsigned tid)
488{
489 // If we want to include the squashing instruction in the squash,
490 // then use one older sequence number.
491 // Hopefully this doesn't mess things up. Basically I want to squash
492 // all instructions of this thread.
493 InstSeqNum squashed_inst = rob->isEmpty() ?
494 0 : rob->readHeadInst(tid)->seqNum - 1;
495
496 // All younger instructions will be squashed. Set the sequence
497 // number as the youngest instruction in the ROB (0 in this case.
498 // Hopefully nothing breaks.)
499 youngestSeqNum[tid] = 0;
500
501 rob->squash(squashed_inst, tid);
502 changedROBNumEntries[tid] = true;
503
504 // Send back the sequence number of the squashed instruction.
505 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
506
507 // Send back the squash signal to tell stages that they should
508 // squash.
509 toIEW->commitInfo[tid].squash = true;
510
511 // Send back the rob squashing signal so other stages know that
512 // the ROB is in the process of squashing.
513 toIEW->commitInfo[tid].robSquashing = true;
514
515 toIEW->commitInfo[tid].branchMispredict = false;
516
517 toIEW->commitInfo[tid].nextPC = PC[tid];
518 toIEW->commitInfo[tid].nextNPC = nextPC[tid];
519}
520
521template <class Impl>
522void
523DefaultCommit<Impl>::squashFromTrap(unsigned tid)
524{
525 squashAll(tid);
526
527 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
528
529 thread[tid]->trapPending = false;
530 thread[tid]->inSyscall = false;
531 trapInFlight[tid] = false;
532
533 trapSquash[tid] = false;
534
535 commitStatus[tid] = ROBSquashing;
536 cpu->activityThisCycle();
537}
538
539template <class Impl>
540void
541DefaultCommit<Impl>::squashFromTC(unsigned tid)
542{
543 squashAll(tid);
544
545 DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
546
547 thread[tid]->inSyscall = false;
548 assert(!thread[tid]->trapPending);
549
550 commitStatus[tid] = ROBSquashing;
551 cpu->activityThisCycle();
552
553 tcSquash[tid] = false;
554}
555
556template <class Impl>
557void
558DefaultCommit<Impl>::tick()
559{
560 wroteToTimeBuffer = false;
561 _nextStatus = Inactive;
562
563 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
564 cpu->signalDrained();
565 drainPending = false;
566 return;
567 }
568
569 if (activeThreads->empty())
570 return;
571
572 std::list<unsigned>::iterator threads = activeThreads->begin();
573 std::list<unsigned>::iterator end = activeThreads->end();
574
575 // Check if any of the threads are done squashing. Change the
576 // status if they are done.
577 while (threads != end) {
578 unsigned tid = *threads++;
579
580 // Clear the bit saying if the thread has committed stores
581 // this cycle.
582 committedStores[tid] = false;
583
584 if (commitStatus[tid] == ROBSquashing) {
585
586 if (rob->isDoneSquashing(tid)) {
587 commitStatus[tid] = Running;
588 } else {
589 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
590 " insts this cycle.\n", tid);
591 rob->doSquash(tid);
592 toIEW->commitInfo[tid].robSquashing = true;
593 wroteToTimeBuffer = true;
594 }
595 }
596 }
597
598 commit();
599
600 markCompletedInsts();
601
602 threads = activeThreads->begin();
603
604 while (threads != end) {
605 unsigned tid = *threads++;
606
607 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
608 // The ROB has more instructions it can commit. Its next status
609 // will be active.
610 _nextStatus = Active;
611
612 DynInstPtr inst = rob->readHeadInst(tid);
613
614 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
615 " ROB and ready to commit\n",
616 tid, inst->seqNum, inst->readPC());
617
618 } else if (!rob->isEmpty(tid)) {
619 DynInstPtr inst = rob->readHeadInst(tid);
620
621 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
622 "%#x is head of ROB and not ready\n",
623 tid, inst->seqNum, inst->readPC());
624 }
625
626 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
627 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
628 }
629
630
631 if (wroteToTimeBuffer) {
632 DPRINTF(Activity, "Activity This Cycle.\n");
633 cpu->activityThisCycle();
634 }
635
636 updateStatus();
637}
638
639#if FULL_SYSTEM
640template <class Impl>
641void
642DefaultCommit<Impl>::handleInterrupt()
643{
644 if (interrupt != NoFault) {
645 // Wait until the ROB is empty and all stores have drained in
646 // order to enter the interrupt.
647 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
648 // Squash or record that I need to squash this cycle if
649 // an interrupt needed to be handled.
650 DPRINTF(Commit, "Interrupt detected.\n");
651
652 Fault new_interrupt = cpu->getInterrupts();
653 assert(new_interrupt != NoFault);
654
655 // Clear the interrupt now that it's going to be handled
656 toIEW->commitInfo[0].clearInterrupt = true;
657
658 assert(!thread[0]->inSyscall);
659 thread[0]->inSyscall = true;
660
661 // CPU will handle interrupt.
662 cpu->processInterrupts(interrupt);
663
664 thread[0]->inSyscall = false;
665
666 commitStatus[0] = TrapPending;
667
668 // Generate trap squash event.
669 generateTrapEvent(0);
670
671 interrupt = NoFault;
672 } else {
673 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
674 }
675 } else if (commitStatus[0] != TrapPending &&
676 cpu->check_interrupts(cpu->tcBase(0)) &&
677 !trapSquash[0] &&
678 !tcSquash[0]) {
679 // Process interrupts if interrupts are enabled, not in PAL
680 // mode, and no other traps or external squashes are currently
681 // pending.
682 // @todo: Allow other threads to handle interrupts.
683
684 // Get any interrupt that happened
685 interrupt = cpu->getInterrupts();
686
687 if (interrupt != NoFault) {
688 // Tell fetch that there is an interrupt pending. This
689 // will make fetch wait until it sees a non PAL-mode PC,
690 // at which point it stops fetching instructions.
691 toIEW->commitInfo[0].interruptPending = true;
692 }
693 }
694}
695#endif // FULL_SYSTEM
696
697template <class Impl>
698void
699DefaultCommit<Impl>::commit()
700{
701
702#if FULL_SYSTEM
703 // Check for any interrupt, and start processing it. Or if we
704 // have an outstanding interrupt and are at a point when it is
705 // valid to take an interrupt, process it.
706 if (cpu->check_interrupts(cpu->tcBase(0))) {
707 handleInterrupt();
708 }
709#endif // FULL_SYSTEM
710
711 ////////////////////////////////////
712 // Check for any possible squashes, handle them first
713 ////////////////////////////////////
714 std::list<unsigned>::iterator threads = activeThreads->begin();
715 std::list<unsigned>::iterator end = activeThreads->end();
716
717 while (threads != end) {
718 unsigned tid = *threads++;
719
720 // Not sure which one takes priority. I think if we have
721 // both, that's a bad sign.
722 if (trapSquash[tid] == true) {
723 assert(!tcSquash[tid]);
724 squashFromTrap(tid);
725 } else if (tcSquash[tid] == true) {
726 assert(commitStatus[tid] != TrapPending);
727 squashFromTC(tid);
728 }
729
730 // Squashed sequence number must be older than youngest valid
731 // instruction in the ROB. This prevents squashes from younger
732 // instructions overriding squashes from older instructions.
733 if (fromIEW->squash[tid] &&
734 commitStatus[tid] != TrapPending &&
735 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
736
737 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
738 tid,
739 fromIEW->mispredPC[tid],
740 fromIEW->squashedSeqNum[tid]);
741
742 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
743 tid,
744 fromIEW->nextPC[tid]);
745
746 commitStatus[tid] = ROBSquashing;
747
748 // If we want to include the squashing instruction in the squash,
749 // then use one older sequence number.
750 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
751
752#if ISA_HAS_DELAY_SLOT
753 InstSeqNum bdelay_done_seq_num = squashed_inst;
754 bool squash_bdelay_slot = fromIEW->squashDelaySlot[tid];
755 bool branchMispredict = fromIEW->branchMispredict[tid];
756
757 // Squashing/not squashing the branch delay slot only makes
758 // sense when you're squashing from a branch, ie from a branch
759 // mispredict.
760 if (branchMispredict && !squash_bdelay_slot) {
761 bdelay_done_seq_num++;
762 }
763#endif
764
765 if (fromIEW->includeSquashInst[tid] == true) {
766 squashed_inst--;
767#if ISA_HAS_DELAY_SLOT
768 bdelay_done_seq_num--;
769#endif
770 }
771
772 // All younger instructions will be squashed. Set the sequence
773 // number as the youngest instruction in the ROB.
774 youngestSeqNum[tid] = squashed_inst;
775
776#if ISA_HAS_DELAY_SLOT
777 rob->squash(bdelay_done_seq_num, tid);
778 toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot;
779 toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num;
780#else
781 rob->squash(squashed_inst, tid);
782 toIEW->commitInfo[tid].squashDelaySlot = true;
783#endif
784 changedROBNumEntries[tid] = true;
785
786 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
787
788 toIEW->commitInfo[tid].squash = true;
789
790 // Send back the rob squashing signal so other stages know that
791 // the ROB is in the process of squashing.
792 toIEW->commitInfo[tid].robSquashing = true;
793
794 toIEW->commitInfo[tid].branchMispredict =
795 fromIEW->branchMispredict[tid];
796
797 toIEW->commitInfo[tid].branchTaken =
798 fromIEW->branchTaken[tid];
799
800 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
801 toIEW->commitInfo[tid].nextNPC = fromIEW->nextNPC[tid];
802
803 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
804
805 if (toIEW->commitInfo[tid].branchMispredict) {
806 ++branchMispredicts;
807 }
808 }
809
810 }
811
812 setNextStatus();
813
814 if (squashCounter != numThreads) {
815 // If we're not currently squashing, then get instructions.
816 getInsts();
817
818 // Try to commit any instructions.
819 commitInsts();
820 } else {
821#if ISA_HAS_DELAY_SLOT
822 skidInsert();
823#endif
824 }
825
826 //Check for any activity
827 threads = activeThreads->begin();
828
829 while (threads != end) {
830 unsigned tid = *threads++;
831
832 if (changedROBNumEntries[tid]) {
833 toIEW->commitInfo[tid].usedROB = true;
834 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
835
836 wroteToTimeBuffer = true;
837 changedROBNumEntries[tid] = false;
838 if (rob->isEmpty(tid))
839 checkEmptyROB[tid] = true;
840 }
841
842 // ROB is only considered "empty" for previous stages if: a)
843 // ROB is empty, b) there are no outstanding stores, c) IEW
844 // stage has received any information regarding stores that
845 // committed.
846 // c) is checked by making sure to not consider the ROB empty
847 // on the same cycle as when stores have been committed.
848 // @todo: Make this handle multi-cycle communication between
849 // commit and IEW.
850 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
851 !iewStage->hasStoresToWB() && !committedStores[tid]) {
852 checkEmptyROB[tid] = false;
853 toIEW->commitInfo[tid].usedROB = true;
854 toIEW->commitInfo[tid].emptyROB = true;
855 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
856 wroteToTimeBuffer = true;
857 }
858
859 }
860}
861
862template <class Impl>
863void
864DefaultCommit<Impl>::commitInsts()
865{
866 ////////////////////////////////////
867 // Handle commit
868 // Note that commit will be handled prior to putting new
869 // instructions in the ROB so that the ROB only tries to commit
870 // instructions it has in this current cycle, and not instructions
871 // it is writing in during this cycle. Can't commit and squash
872 // things at the same time...
873 ////////////////////////////////////
874
875 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
876
877 unsigned num_committed = 0;
878
879 DynInstPtr head_inst;
880
881 // Commit as many instructions as possible until the commit bandwidth
882 // limit is reached, or it becomes impossible to commit any more.
883 while (num_committed < commitWidth) {
884 int commit_thread = getCommittingThread();
885
886 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
887 break;
888
889 head_inst = rob->readHeadInst(commit_thread);
890
891 int tid = head_inst->threadNumber;
892
893 assert(tid == commit_thread);
894
895 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
896 head_inst->seqNum, tid);
897
898 // If the head instruction is squashed, it is ready to retire
899 // (be removed from the ROB) at any time.
900 if (head_inst->isSquashed()) {
901
902 DPRINTF(Commit, "Retiring squashed instruction from "
903 "ROB.\n");
904
905 rob->retireHead(commit_thread);
906
907 ++commitSquashedInsts;
908
909 // Record that the number of ROB entries has changed.
910 changedROBNumEntries[tid] = true;
911 } else {
912 PC[tid] = head_inst->readPC();
913 nextPC[tid] = head_inst->readNextPC();
914 nextNPC[tid] = head_inst->readNextNPC();
915
916 // Increment the total number of non-speculative instructions
917 // executed.
918 // Hack for now: it really shouldn't happen until after the
919 // commit is deemed to be successful, but this count is needed
920 // for syscalls.
921 thread[tid]->funcExeInst++;
922
923 // Try to commit the head instruction.
924 bool commit_success = commitHead(head_inst, num_committed);
925
926 if (commit_success) {
927 ++num_committed;
928
929 changedROBNumEntries[tid] = true;
930
931 // Set the doneSeqNum to the youngest committed instruction.
932 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
933
934 ++commitCommittedInsts;
935
936 // To match the old model, don't count nops and instruction
937 // prefetches towards the total commit count.
938 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
939 cpu->instDone(tid);
940 }
941
942 PC[tid] = nextPC[tid];
943#if ISA_HAS_DELAY_SLOT
944 nextPC[tid] = nextNPC[tid];
945 nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
946#else
947 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
948#endif
949
950#if FULL_SYSTEM
951 int count = 0;
952 Addr oldpc;
953 do {
954 // Debug statement. Checks to make sure we're not
955 // currently updating state while handling PC events.
956 if (count == 0)
957 assert(!thread[tid]->inSyscall &&
958 !thread[tid]->trapPending);
959 oldpc = PC[tid];
960 cpu->system->pcEventQueue.service(
961 thread[tid]->getTC());
962 count++;
963 } while (oldpc != PC[tid]);
964 if (count > 1) {
965 DPRINTF(Commit, "PC skip function event, stopping commit\n");
966 break;
967 }
968#endif
969 } else {
970 DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
971 "[tid:%i] [sn:%i].\n",
972 head_inst->readPC(), tid ,head_inst->seqNum);
973 break;
974 }
975 }
976 }
977
978 DPRINTF(CommitRate, "%i\n", num_committed);
979 numCommittedDist.sample(num_committed);
980
981 if (num_committed == commitWidth) {
982 commitEligibleSamples++;
983 }
984}
985
986template <class Impl>
987bool
988DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
989{
990 assert(head_inst);
991
992 int tid = head_inst->threadNumber;
993
994 // If the instruction is not executed yet, then it will need extra
995 // handling. Signal backwards that it should be executed.
996 if (!head_inst->isExecuted()) {
997 // Keep this number correct. We have not yet actually executed
998 // and committed this instruction.
999 thread[tid]->funcExeInst--;
1000
1001 if (head_inst->isNonSpeculative() ||
1002 head_inst->isStoreConditional() ||
1003 head_inst->isMemBarrier() ||
1004 head_inst->isWriteBarrier()) {
1005
1006 DPRINTF(Commit, "Encountered a barrier or non-speculative "
1007 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
1008 head_inst->seqNum, head_inst->readPC());
1009
1010 if (inst_num > 0 || iewStage->hasStoresToWB()) {
1011 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1012 return false;
1013 }
1014
1015 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1016
1017 // Change the instruction so it won't try to commit again until
1018 // it is executed.
1019 head_inst->clearCanCommit();
1020
1021 ++commitNonSpecStalls;
1022
1023 return false;
1024 } else if (head_inst->isLoad()) {
1025 if (inst_num > 0 || iewStage->hasStoresToWB()) {
1026 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1027 return false;
1028 }
1029
1030 assert(head_inst->uncacheable());
1031 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
1032 head_inst->seqNum, head_inst->readPC());
1033
1034 // Send back the non-speculative instruction's sequence
1035 // number. Tell the lsq to re-execute the load.
1036 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1037 toIEW->commitInfo[tid].uncached = true;
1038 toIEW->commitInfo[tid].uncachedLoad = head_inst;
1039
1040 head_inst->clearCanCommit();
1041
1042 return false;
1043 } else {
1044 panic("Trying to commit un-executed instruction "
1045 "of unknown type!\n");
1046 }
1047 }
1048
1049 if (head_inst->isThreadSync()) {
1050 // Not handled for now.
1051 panic("Thread sync instructions are not handled yet.\n");
1052 }
1053
1054 // Check if the instruction caused a fault. If so, trap.
1055 Fault inst_fault = head_inst->getFault();
1056
1057 // Stores mark themselves as completed.
1058 if (!head_inst->isStore() && inst_fault == NoFault) {
1059 head_inst->setCompleted();
1060 }
1061
1062#if USE_CHECKER
1063 // Use checker prior to updating anything due to traps or PC
1064 // based events.
1065 if (cpu->checker) {
1066 cpu->checker->verify(head_inst);
1067 }
1068#endif
1069
1070 // DTB will sometimes need the machine instruction for when
1071 // faults happen. So we will set it here, prior to the DTB
1072 // possibly needing it for its fault.
1073 thread[tid]->setInst(
1074 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1075
1076 if (inst_fault != NoFault) {
1077 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1078 head_inst->seqNum, head_inst->readPC());
1079
1080 if (iewStage->hasStoresToWB() || inst_num > 0) {
1081 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1082 return false;
1083 }
1084
1085 head_inst->setCompleted();
1086
1087#if USE_CHECKER
1088 if (cpu->checker && head_inst->isStore()) {
1089 cpu->checker->verify(head_inst);
1090 }
1091#endif
1092
1093 assert(!thread[tid]->inSyscall);
1094
1095 // Mark that we're in state update mode so that the trap's
1096 // execution doesn't generate extra squashes.
1097 thread[tid]->inSyscall = true;
1098
1099 // Execute the trap. Although it's slightly unrealistic in
1100 // terms of timing (as it doesn't wait for the full timing of
1101 // the trap event to complete before updating state), it's
1102 // needed to update the state as soon as possible. This
1103 // prevents external agents from changing any specific state
1104 // that the trap need.
1105 cpu->trap(inst_fault, tid);
1106
1107 // Exit state update mode to avoid accidental updating.
1108 thread[tid]->inSyscall = false;
1109
1110 commitStatus[tid] = TrapPending;
1111
1112 if (head_inst->traceData) {
1113 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1114 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1115 head_inst->traceData->dump();
1116 delete head_inst->traceData;
1117 head_inst->traceData = NULL;
1118 }
1119
1120 // Generate trap squash event.
1121 generateTrapEvent(tid);
1122// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC());
1123 return false;
1124 }
1125
1126 updateComInstStats(head_inst);
1127
1128#if FULL_SYSTEM
1129 if (thread[tid]->profile) {
1130// bool usermode = TheISA::inUserMode(thread[tid]->getTC());
1131// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC();
1132 thread[tid]->profilePC = head_inst->readPC();
1133 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1134 head_inst->staticInst);
1135
1136 if (node)
1137 thread[tid]->profileNode = node;
1138 }
1139#endif
1140
1141 if (head_inst->traceData) {
1142 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1143 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1144 head_inst->traceData->dump();
1145 delete head_inst->traceData;
1146 head_inst->traceData = NULL;
1147 }
1148
1149 // Update the commit rename map
1150 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1151 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1152 head_inst->renamedDestRegIdx(i));
1153 }
1154
1155 if (head_inst->isCopy())
1156 panic("Should not commit any copy instructions!");
1157
1158 // Finally clear the head ROB entry.
1159 rob->retireHead(tid);
1160
1161 // If this was a store, record it for this cycle.
1162 if (head_inst->isStore())
1163 committedStores[tid] = true;
1164
1165 // Return true to indicate that we have committed an instruction.
1166 return true;
1167}
1168
1169template <class Impl>
1170void
1171DefaultCommit<Impl>::getInsts()
1172{
1173 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1174
1175#if ISA_HAS_DELAY_SLOT
1176 // Read any renamed instructions and place them into the ROB.
1177 int insts_to_process = std::min((int)renameWidth,
1178 (int)(fromRename->size + skidBuffer.size()));
1179 int rename_idx = 0;
1180
1181 DPRINTF(Commit, "%i insts available to process. Rename Insts:%i "
1182 "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size,
1183 skidBuffer.size());
1184#else
1185 // Read any renamed instructions and place them into the ROB.
1186 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1187#endif
1188
1189
1190 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1191 DynInstPtr inst;
1192
1193#if ISA_HAS_DELAY_SLOT
1194 // Get insts from skidBuffer or from Rename
1195 if (skidBuffer.size() > 0) {
1196 DPRINTF(Commit, "Grabbing skidbuffer inst.\n");
1197 inst = skidBuffer.front();
1198 skidBuffer.pop();
1199 } else {
1200 DPRINTF(Commit, "Grabbing rename inst.\n");
1201 inst = fromRename->insts[rename_idx++];
1202 }
1203#else
1204 inst = fromRename->insts[inst_num];
1205#endif
1206 int tid = inst->threadNumber;
1207
1208 if (!inst->isSquashed() &&
1209 commitStatus[tid] != ROBSquashing &&
1210 commitStatus[tid] != TrapPending) {
1211 changedROBNumEntries[tid] = true;
1212
1213 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1214 inst->readPC(), inst->seqNum, tid);
1215
1216 rob->insertInst(inst);
1217
1218 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1219
1220 youngestSeqNum[tid] = inst->seqNum;
1221 } else {
1222 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1223 "squashed, skipping.\n",
1224 inst->readPC(), inst->seqNum, tid);
1225 }
1226 }
1227
1228#if ISA_HAS_DELAY_SLOT
1229 if (rename_idx < fromRename->size) {
1230 DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n");
1231
1232 for (;
1233 rename_idx < fromRename->size;
1234 rename_idx++) {
1235 DynInstPtr inst = fromRename->insts[rename_idx];
1236
1237 if (!inst->isSquashed()) {
1238 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1239 "skidBuffer.\n", inst->readPC(), inst->seqNum,
1240 inst->threadNumber);
1241 skidBuffer.push(inst);
1242 } else {
1243 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1244 "squashed, skipping.\n",
1245 inst->readPC(), inst->seqNum, inst->threadNumber);
1246 }
1247 }
1248 }
1249#endif
1250
1251}
1252
1253template <class Impl>
1254void
1255DefaultCommit<Impl>::skidInsert()
1256{
1257 DPRINTF(Commit, "Attempting to any instructions from rename into "
1258 "skidBuffer.\n");
1259
1260 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1261 DynInstPtr inst = fromRename->insts[inst_num];
1262
1263 if (!inst->isSquashed()) {
1264 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1265 "skidBuffer.\n", inst->readPC(), inst->seqNum,
1266 inst->threadNumber);
1267 skidBuffer.push(inst);
1268 } else {
1269 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1270 "squashed, skipping.\n",
1271 inst->readPC(), inst->seqNum, inst->threadNumber);
1272 }
1273 }
1274}
1275
1276template <class Impl>
1277void
1278DefaultCommit<Impl>::markCompletedInsts()
1279{
1280 // Grab completed insts out of the IEW instruction queue, and mark
1281 // instructions completed within the ROB.
1282 for (int inst_num = 0;
1283 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1284 ++inst_num)
1285 {
1286 if (!fromIEW->insts[inst_num]->isSquashed()) {
1287 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1288 "within ROB.\n",
1289 fromIEW->insts[inst_num]->threadNumber,
1290 fromIEW->insts[inst_num]->readPC(),
1291 fromIEW->insts[inst_num]->seqNum);
1292
1293 // Mark the instruction as ready to commit.
1294 fromIEW->insts[inst_num]->setCanCommit();
1295 }
1296 }
1297}
1298
1299template <class Impl>
1300bool
1301DefaultCommit<Impl>::robDoneSquashing()
1302{
1303 std::list<unsigned>::iterator threads = activeThreads->begin();
1304 std::list<unsigned>::iterator end = activeThreads->end();
1305
1306 while (threads != end) {
1307 unsigned tid = *threads++;
1308
1309 if (!rob->isDoneSquashing(tid))
1310 return false;
1311 }
1312
1313 return true;
1314}
1315
1316template <class Impl>
1317void
1318DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1319{
1320 unsigned thread = inst->threadNumber;
1321
1322 //
1323 // Pick off the software prefetches
1324 //
1325#ifdef TARGET_ALPHA
1326 if (inst->isDataPrefetch()) {
1327 statComSwp[thread]++;
1328 } else {
1329 statComInst[thread]++;
1330 }
1331#else
1332 statComInst[thread]++;
1333#endif
1334
1335 //
1336 // Control Instructions
1337 //
1338 if (inst->isControl())
1339 statComBranches[thread]++;
1340
1341 //
1342 // Memory references
1343 //
1344 if (inst->isMemRef()) {
1345 statComRefs[thread]++;
1346
1347 if (inst->isLoad()) {
1348 statComLoads[thread]++;
1349 }
1350 }
1351
1352 if (inst->isMemBarrier()) {
1353 statComMembars[thread]++;
1354 }
1355}
1356
1357////////////////////////////////////////
1358// //
1359// SMT COMMIT POLICY MAINTAINED HERE //
1360// //
1361////////////////////////////////////////
1362template <class Impl>
1363int
1364DefaultCommit<Impl>::getCommittingThread()
1365{
1366 if (numThreads > 1) {
1367 switch (commitPolicy) {
1368
1369 case Aggressive:
1370 //If Policy is Aggressive, commit will call
1371 //this function multiple times per
1372 //cycle
1373 return oldestReady();
1374
1375 case RoundRobin:
1376 return roundRobin();
1377
1378 case OldestReady:
1379 return oldestReady();
1380
1381 default:
1382 return -1;
1383 }
1384 } else {
1385 assert(!activeThreads->empty());
1386 int tid = activeThreads->front();
1387
1388 if (commitStatus[tid] == Running ||
1389 commitStatus[tid] == Idle ||
1390 commitStatus[tid] == FetchTrapPending) {
1391 return tid;
1392 } else {
1393 return -1;
1394 }
1395 }
1396}
1397
1398template<class Impl>
1399int
1400DefaultCommit<Impl>::roundRobin()
1401{
1402 std::list<unsigned>::iterator pri_iter = priority_list.begin();
1403 std::list<unsigned>::iterator end = priority_list.end();
1404
1405 while (pri_iter != end) {
1406 unsigned tid = *pri_iter;
1407
1408 if (commitStatus[tid] == Running ||
1409 commitStatus[tid] == Idle ||
1410 commitStatus[tid] == FetchTrapPending) {
1411
1412 if (rob->isHeadReady(tid)) {
1413 priority_list.erase(pri_iter);
1414 priority_list.push_back(tid);
1415
1416 return tid;
1417 }
1418 }
1419
1420 pri_iter++;
1421 }
1422
1423 return -1;
1424}
1425
1426template<class Impl>
1427int
1428DefaultCommit<Impl>::oldestReady()
1429{
1430 unsigned oldest = 0;
1431 bool first = true;
1432
1433 std::list<unsigned>::iterator threads = activeThreads->begin();
1434 std::list<unsigned>::iterator end = activeThreads->end();
1435
1436 while (threads != end) {
1437 unsigned tid = *threads++;
1438
1439 if (!rob->isEmpty(tid) &&
1440 (commitStatus[tid] == Running ||
1441 commitStatus[tid] == Idle ||
1442 commitStatus[tid] == FetchTrapPending)) {
1443
1444 if (rob->isHeadReady(tid)) {
1445
1446 DynInstPtr head_inst = rob->readHeadInst(tid);
1447
1448 if (first) {
1449 oldest = tid;
1450 first = false;
1451 } else if (head_inst->seqNum < oldest) {
1452 oldest = tid;
1453 }
1454 }
1455 }
1456 }
1457
1458 if (!first) {
1459 return oldest;
1460 } else {
1461 return -1;
1462 }
1463}
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