1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
35#include <algorithm>
36#include <string>
37
38#include "arch/utility.hh"
39#include "base/loader/symtab.hh"
40#include "base/timebuf.hh"
41#include "cpu/exetrace.hh"
42#include "cpu/o3/commit.hh"
43#include "cpu/o3/thread_state.hh"
44
45#if USE_CHECKER
46#include "cpu/checker/cpu.hh"
47#endif
48
49template <class Impl>
50DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
51 unsigned _tid)
52 : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
53{
54 this->setFlags(Event::AutoDelete);
55}
56
57template <class Impl>
58void
59DefaultCommit<Impl>::TrapEvent::process()
60{
61 // This will get reset by commit if it was switched out at the
62 // time of this event processing.
63 commit->trapSquash[tid] = true;
64}
65
66template <class Impl>
67const char *
68DefaultCommit<Impl>::TrapEvent::description()
69{
70 return "Trap event";
71}
72
73template <class Impl>
74DefaultCommit<Impl>::DefaultCommit(Params *params)
75 : squashCounter(0),
76 iewToCommitDelay(params->iewToCommitDelay),
77 commitToIEWDelay(params->commitToIEWDelay),
78 renameToROBDelay(params->renameToROBDelay),
79 fetchToCommitDelay(params->commitToFetchDelay),
80 renameWidth(params->renameWidth),
81 commitWidth(params->commitWidth),
82 numThreads(params->numberOfThreads),
83 drainPending(false),
84 switchedOut(false),
85 trapLatency(params->trapLatency)
86{
87 _status = Active;
88 _nextStatus = Inactive;
89 std::string policy = params->smtCommitPolicy;
90
91 //Convert string to lowercase
92 std::transform(policy.begin(), policy.end(), policy.begin(),
93 (int(*)(int)) tolower);
94
95 //Assign commit policy
96 if (policy == "aggressive"){
97 commitPolicy = Aggressive;
98
99 DPRINTF(Commit,"Commit Policy set to Aggressive.");
100 } else if (policy == "roundrobin"){
101 commitPolicy = RoundRobin;
102
103 //Set-Up Priority List
104 for (int tid=0; tid < numThreads; tid++) {
105 priority_list.push_back(tid);
106 }
107
108 DPRINTF(Commit,"Commit Policy set to Round Robin.");
109 } else if (policy == "oldestready"){
110 commitPolicy = OldestReady;
111
112 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
113 } else {
114 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
115 "RoundRobin,OldestReady}");
116 }
117
118 for (int i=0; i < numThreads; i++) {
119 commitStatus[i] = Idle;
120 changedROBNumEntries[i] = false;
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
35#include <algorithm>
36#include <string>
37
38#include "arch/utility.hh"
39#include "base/loader/symtab.hh"
40#include "base/timebuf.hh"
41#include "cpu/exetrace.hh"
42#include "cpu/o3/commit.hh"
43#include "cpu/o3/thread_state.hh"
44
45#if USE_CHECKER
46#include "cpu/checker/cpu.hh"
47#endif
48
49template <class Impl>
50DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
51 unsigned _tid)
52 : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
53{
54 this->setFlags(Event::AutoDelete);
55}
56
57template <class Impl>
58void
59DefaultCommit<Impl>::TrapEvent::process()
60{
61 // This will get reset by commit if it was switched out at the
62 // time of this event processing.
63 commit->trapSquash[tid] = true;
64}
65
66template <class Impl>
67const char *
68DefaultCommit<Impl>::TrapEvent::description()
69{
70 return "Trap event";
71}
72
73template <class Impl>
74DefaultCommit<Impl>::DefaultCommit(Params *params)
75 : squashCounter(0),
76 iewToCommitDelay(params->iewToCommitDelay),
77 commitToIEWDelay(params->commitToIEWDelay),
78 renameToROBDelay(params->renameToROBDelay),
79 fetchToCommitDelay(params->commitToFetchDelay),
80 renameWidth(params->renameWidth),
81 commitWidth(params->commitWidth),
82 numThreads(params->numberOfThreads),
83 drainPending(false),
84 switchedOut(false),
85 trapLatency(params->trapLatency)
86{
87 _status = Active;
88 _nextStatus = Inactive;
89 std::string policy = params->smtCommitPolicy;
90
91 //Convert string to lowercase
92 std::transform(policy.begin(), policy.end(), policy.begin(),
93 (int(*)(int)) tolower);
94
95 //Assign commit policy
96 if (policy == "aggressive"){
97 commitPolicy = Aggressive;
98
99 DPRINTF(Commit,"Commit Policy set to Aggressive.");
100 } else if (policy == "roundrobin"){
101 commitPolicy = RoundRobin;
102
103 //Set-Up Priority List
104 for (int tid=0; tid < numThreads; tid++) {
105 priority_list.push_back(tid);
106 }
107
108 DPRINTF(Commit,"Commit Policy set to Round Robin.");
109 } else if (policy == "oldestready"){
110 commitPolicy = OldestReady;
111
112 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
113 } else {
114 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
115 "RoundRobin,OldestReady}");
116 }
117
118 for (int i=0; i < numThreads; i++) {
119 commitStatus[i] = Idle;
120 changedROBNumEntries[i] = false;
|
121 checkEmptyROB[i] = false;
122 trapInFlight[i] = false;
123 committedStores[i] = false;
| |
124 trapSquash[i] = false;
125 tcSquash[i] = false;
126 PC[i] = nextPC[i] = nextNPC[i] = 0;
127 }
128#if FULL_SYSTEM
129 interrupt = NoFault;
130#endif
131}
132
133template <class Impl>
134std::string
135DefaultCommit<Impl>::name() const
136{
137 return cpu->name() + ".commit";
138}
139
140template <class Impl>
141void
142DefaultCommit<Impl>::regStats()
143{
144 using namespace Stats;
145 commitCommittedInsts
146 .name(name() + ".commitCommittedInsts")
147 .desc("The number of committed instructions")
148 .prereq(commitCommittedInsts);
149 commitSquashedInsts
150 .name(name() + ".commitSquashedInsts")
151 .desc("The number of squashed insts skipped by commit")
152 .prereq(commitSquashedInsts);
153 commitSquashEvents
154 .name(name() + ".commitSquashEvents")
155 .desc("The number of times commit is told to squash")
156 .prereq(commitSquashEvents);
157 commitNonSpecStalls
158 .name(name() + ".commitNonSpecStalls")
159 .desc("The number of times commit has been forced to stall to "
160 "communicate backwards")
161 .prereq(commitNonSpecStalls);
162 branchMispredicts
163 .name(name() + ".branchMispredicts")
164 .desc("The number of times a branch was mispredicted")
165 .prereq(branchMispredicts);
166 numCommittedDist
167 .init(0,commitWidth,1)
168 .name(name() + ".COM:committed_per_cycle")
169 .desc("Number of insts commited each cycle")
170 .flags(Stats::pdf)
171 ;
172
173 statComInst
174 .init(cpu->number_of_threads)
175 .name(name() + ".COM:count")
176 .desc("Number of instructions committed")
177 .flags(total)
178 ;
179
180 statComSwp
181 .init(cpu->number_of_threads)
182 .name(name() + ".COM:swp_count")
183 .desc("Number of s/w prefetches committed")
184 .flags(total)
185 ;
186
187 statComRefs
188 .init(cpu->number_of_threads)
189 .name(name() + ".COM:refs")
190 .desc("Number of memory references committed")
191 .flags(total)
192 ;
193
194 statComLoads
195 .init(cpu->number_of_threads)
196 .name(name() + ".COM:loads")
197 .desc("Number of loads committed")
198 .flags(total)
199 ;
200
201 statComMembars
202 .init(cpu->number_of_threads)
203 .name(name() + ".COM:membars")
204 .desc("Number of memory barriers committed")
205 .flags(total)
206 ;
207
208 statComBranches
209 .init(cpu->number_of_threads)
210 .name(name() + ".COM:branches")
211 .desc("Number of branches committed")
212 .flags(total)
213 ;
214
215 commitEligible
216 .init(cpu->number_of_threads)
217 .name(name() + ".COM:bw_limited")
218 .desc("number of insts not committed due to BW limits")
219 .flags(total)
220 ;
221
222 commitEligibleSamples
223 .name(name() + ".COM:bw_lim_events")
224 .desc("number cycles where commit BW limit reached")
225 ;
226}
227
228template <class Impl>
229void
230DefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr)
231{
232 DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
233 cpu = cpu_ptr;
234
235 // Commit must broadcast the number of free entries it has at the start of
236 // the simulation, so it starts as active.
237 cpu->activateStage(O3CPU::CommitIdx);
238
239 trapLatency = cpu->cycles(trapLatency);
240}
241
242template <class Impl>
243void
244DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
245{
246 thread = threads;
247}
248
249template <class Impl>
250void
251DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
252{
253 DPRINTF(Commit, "Commit: Setting time buffer pointer.\n");
254 timeBuffer = tb_ptr;
255
256 // Setup wire to send information back to IEW.
257 toIEW = timeBuffer->getWire(0);
258
259 // Setup wire to read data from IEW (for the ROB).
260 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
261}
262
263template <class Impl>
264void
265DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
266{
267 DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n");
268 fetchQueue = fq_ptr;
269
270 // Setup wire to get instructions from rename (for the ROB).
271 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
272}
273
274template <class Impl>
275void
276DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
277{
278 DPRINTF(Commit, "Commit: Setting rename queue pointer.\n");
279 renameQueue = rq_ptr;
280
281 // Setup wire to get instructions from rename (for the ROB).
282 fromRename = renameQueue->getWire(-renameToROBDelay);
283}
284
285template <class Impl>
286void
287DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
288{
289 DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n");
290 iewQueue = iq_ptr;
291
292 // Setup wire to get instructions from IEW.
293 fromIEW = iewQueue->getWire(-iewToCommitDelay);
294}
295
296template <class Impl>
297void
298DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
299{
300 iewStage = iew_stage;
301}
302
303template<class Impl>
304void
305DefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
306{
307 DPRINTF(Commit, "Commit: Setting active threads list pointer.\n");
308 activeThreads = at_ptr;
309}
310
311template <class Impl>
312void
313DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
314{
315 DPRINTF(Commit, "Setting rename map pointers.\n");
316
317 for (int i=0; i < numThreads; i++) {
318 renameMap[i] = &rm_ptr[i];
319 }
320}
321
322template <class Impl>
323void
324DefaultCommit<Impl>::setROB(ROB *rob_ptr)
325{
326 DPRINTF(Commit, "Commit: Setting ROB pointer.\n");
327 rob = rob_ptr;
328}
329
330template <class Impl>
331void
332DefaultCommit<Impl>::initStage()
333{
334 rob->setActiveThreads(activeThreads);
335 rob->resetEntries();
336
337 // Broadcast the number of free entries.
338 for (int i=0; i < numThreads; i++) {
339 toIEW->commitInfo[i].usedROB = true;
340 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
| 121 trapSquash[i] = false;
122 tcSquash[i] = false;
123 PC[i] = nextPC[i] = nextNPC[i] = 0;
124 }
125#if FULL_SYSTEM
126 interrupt = NoFault;
127#endif
128}
129
130template <class Impl>
131std::string
132DefaultCommit<Impl>::name() const
133{
134 return cpu->name() + ".commit";
135}
136
137template <class Impl>
138void
139DefaultCommit<Impl>::regStats()
140{
141 using namespace Stats;
142 commitCommittedInsts
143 .name(name() + ".commitCommittedInsts")
144 .desc("The number of committed instructions")
145 .prereq(commitCommittedInsts);
146 commitSquashedInsts
147 .name(name() + ".commitSquashedInsts")
148 .desc("The number of squashed insts skipped by commit")
149 .prereq(commitSquashedInsts);
150 commitSquashEvents
151 .name(name() + ".commitSquashEvents")
152 .desc("The number of times commit is told to squash")
153 .prereq(commitSquashEvents);
154 commitNonSpecStalls
155 .name(name() + ".commitNonSpecStalls")
156 .desc("The number of times commit has been forced to stall to "
157 "communicate backwards")
158 .prereq(commitNonSpecStalls);
159 branchMispredicts
160 .name(name() + ".branchMispredicts")
161 .desc("The number of times a branch was mispredicted")
162 .prereq(branchMispredicts);
163 numCommittedDist
164 .init(0,commitWidth,1)
165 .name(name() + ".COM:committed_per_cycle")
166 .desc("Number of insts commited each cycle")
167 .flags(Stats::pdf)
168 ;
169
170 statComInst
171 .init(cpu->number_of_threads)
172 .name(name() + ".COM:count")
173 .desc("Number of instructions committed")
174 .flags(total)
175 ;
176
177 statComSwp
178 .init(cpu->number_of_threads)
179 .name(name() + ".COM:swp_count")
180 .desc("Number of s/w prefetches committed")
181 .flags(total)
182 ;
183
184 statComRefs
185 .init(cpu->number_of_threads)
186 .name(name() + ".COM:refs")
187 .desc("Number of memory references committed")
188 .flags(total)
189 ;
190
191 statComLoads
192 .init(cpu->number_of_threads)
193 .name(name() + ".COM:loads")
194 .desc("Number of loads committed")
195 .flags(total)
196 ;
197
198 statComMembars
199 .init(cpu->number_of_threads)
200 .name(name() + ".COM:membars")
201 .desc("Number of memory barriers committed")
202 .flags(total)
203 ;
204
205 statComBranches
206 .init(cpu->number_of_threads)
207 .name(name() + ".COM:branches")
208 .desc("Number of branches committed")
209 .flags(total)
210 ;
211
212 commitEligible
213 .init(cpu->number_of_threads)
214 .name(name() + ".COM:bw_limited")
215 .desc("number of insts not committed due to BW limits")
216 .flags(total)
217 ;
218
219 commitEligibleSamples
220 .name(name() + ".COM:bw_lim_events")
221 .desc("number cycles where commit BW limit reached")
222 ;
223}
224
225template <class Impl>
226void
227DefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr)
228{
229 DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
230 cpu = cpu_ptr;
231
232 // Commit must broadcast the number of free entries it has at the start of
233 // the simulation, so it starts as active.
234 cpu->activateStage(O3CPU::CommitIdx);
235
236 trapLatency = cpu->cycles(trapLatency);
237}
238
239template <class Impl>
240void
241DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
242{
243 thread = threads;
244}
245
246template <class Impl>
247void
248DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
249{
250 DPRINTF(Commit, "Commit: Setting time buffer pointer.\n");
251 timeBuffer = tb_ptr;
252
253 // Setup wire to send information back to IEW.
254 toIEW = timeBuffer->getWire(0);
255
256 // Setup wire to read data from IEW (for the ROB).
257 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
258}
259
260template <class Impl>
261void
262DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
263{
264 DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n");
265 fetchQueue = fq_ptr;
266
267 // Setup wire to get instructions from rename (for the ROB).
268 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
269}
270
271template <class Impl>
272void
273DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
274{
275 DPRINTF(Commit, "Commit: Setting rename queue pointer.\n");
276 renameQueue = rq_ptr;
277
278 // Setup wire to get instructions from rename (for the ROB).
279 fromRename = renameQueue->getWire(-renameToROBDelay);
280}
281
282template <class Impl>
283void
284DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
285{
286 DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n");
287 iewQueue = iq_ptr;
288
289 // Setup wire to get instructions from IEW.
290 fromIEW = iewQueue->getWire(-iewToCommitDelay);
291}
292
293template <class Impl>
294void
295DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
296{
297 iewStage = iew_stage;
298}
299
300template<class Impl>
301void
302DefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
303{
304 DPRINTF(Commit, "Commit: Setting active threads list pointer.\n");
305 activeThreads = at_ptr;
306}
307
308template <class Impl>
309void
310DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
311{
312 DPRINTF(Commit, "Setting rename map pointers.\n");
313
314 for (int i=0; i < numThreads; i++) {
315 renameMap[i] = &rm_ptr[i];
316 }
317}
318
319template <class Impl>
320void
321DefaultCommit<Impl>::setROB(ROB *rob_ptr)
322{
323 DPRINTF(Commit, "Commit: Setting ROB pointer.\n");
324 rob = rob_ptr;
325}
326
327template <class Impl>
328void
329DefaultCommit<Impl>::initStage()
330{
331 rob->setActiveThreads(activeThreads);
332 rob->resetEntries();
333
334 // Broadcast the number of free entries.
335 for (int i=0; i < numThreads; i++) {
336 toIEW->commitInfo[i].usedROB = true;
337 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
|
341 toIEW->commitInfo[i].emptyROB = true;
| |
342 }
343
344 cpu->activityThisCycle();
345}
346
347template <class Impl>
348bool
349DefaultCommit<Impl>::drain()
350{
351 drainPending = true;
352
353 return false;
354}
355
356template <class Impl>
357void
358DefaultCommit<Impl>::switchOut()
359{
360 switchedOut = true;
361 drainPending = false;
362 rob->switchOut();
363}
364
365template <class Impl>
366void
367DefaultCommit<Impl>::resume()
368{
369 drainPending = false;
370}
371
372template <class Impl>
373void
374DefaultCommit<Impl>::takeOverFrom()
375{
376 switchedOut = false;
377 _status = Active;
378 _nextStatus = Inactive;
379 for (int i=0; i < numThreads; i++) {
380 commitStatus[i] = Idle;
381 changedROBNumEntries[i] = false;
382 trapSquash[i] = false;
383 tcSquash[i] = false;
384 }
385 squashCounter = 0;
386 rob->takeOverFrom();
387}
388
389template <class Impl>
390void
391DefaultCommit<Impl>::updateStatus()
392{
393 // reset ROB changed variable
394 std::list<unsigned>::iterator threads = activeThreads->begin();
395 std::list<unsigned>::iterator end = activeThreads->end();
396
397 while (threads != end) {
398 unsigned tid = *threads++;
399
400 changedROBNumEntries[tid] = false;
401
402 // Also check if any of the threads has a trap pending
403 if (commitStatus[tid] == TrapPending ||
404 commitStatus[tid] == FetchTrapPending) {
405 _nextStatus = Active;
406 }
407 }
408
409 if (_nextStatus == Inactive && _status == Active) {
410 DPRINTF(Activity, "Deactivating stage.\n");
411 cpu->deactivateStage(O3CPU::CommitIdx);
412 } else if (_nextStatus == Active && _status == Inactive) {
413 DPRINTF(Activity, "Activating stage.\n");
414 cpu->activateStage(O3CPU::CommitIdx);
415 }
416
417 _status = _nextStatus;
418}
419
420template <class Impl>
421void
422DefaultCommit<Impl>::setNextStatus()
423{
424 int squashes = 0;
425
426 std::list<unsigned>::iterator threads = activeThreads->begin();
427 std::list<unsigned>::iterator end = activeThreads->end();
428
429 while (threads != end) {
430 unsigned tid = *threads++;
431
432 if (commitStatus[tid] == ROBSquashing) {
433 squashes++;
434 }
435 }
436
437 squashCounter = squashes;
438
439 // If commit is currently squashing, then it will have activity for the
440 // next cycle. Set its next status as active.
441 if (squashCounter) {
442 _nextStatus = Active;
443 }
444}
445
446template <class Impl>
447bool
448DefaultCommit<Impl>::changedROBEntries()
449{
450 std::list<unsigned>::iterator threads = activeThreads->begin();
451 std::list<unsigned>::iterator end = activeThreads->end();
452
453 while (threads != end) {
454 unsigned tid = *threads++;
455
456 if (changedROBNumEntries[tid]) {
457 return true;
458 }
459 }
460
461 return false;
462}
463
464template <class Impl>
465unsigned
466DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
467{
468 return rob->numFreeEntries(tid);
469}
470
471template <class Impl>
472void
473DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
474{
475 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
476
477 TrapEvent *trap = new TrapEvent(this, tid);
478
479 trap->schedule(curTick + trapLatency);
| 338 }
339
340 cpu->activityThisCycle();
341}
342
343template <class Impl>
344bool
345DefaultCommit<Impl>::drain()
346{
347 drainPending = true;
348
349 return false;
350}
351
352template <class Impl>
353void
354DefaultCommit<Impl>::switchOut()
355{
356 switchedOut = true;
357 drainPending = false;
358 rob->switchOut();
359}
360
361template <class Impl>
362void
363DefaultCommit<Impl>::resume()
364{
365 drainPending = false;
366}
367
368template <class Impl>
369void
370DefaultCommit<Impl>::takeOverFrom()
371{
372 switchedOut = false;
373 _status = Active;
374 _nextStatus = Inactive;
375 for (int i=0; i < numThreads; i++) {
376 commitStatus[i] = Idle;
377 changedROBNumEntries[i] = false;
378 trapSquash[i] = false;
379 tcSquash[i] = false;
380 }
381 squashCounter = 0;
382 rob->takeOverFrom();
383}
384
385template <class Impl>
386void
387DefaultCommit<Impl>::updateStatus()
388{
389 // reset ROB changed variable
390 std::list<unsigned>::iterator threads = activeThreads->begin();
391 std::list<unsigned>::iterator end = activeThreads->end();
392
393 while (threads != end) {
394 unsigned tid = *threads++;
395
396 changedROBNumEntries[tid] = false;
397
398 // Also check if any of the threads has a trap pending
399 if (commitStatus[tid] == TrapPending ||
400 commitStatus[tid] == FetchTrapPending) {
401 _nextStatus = Active;
402 }
403 }
404
405 if (_nextStatus == Inactive && _status == Active) {
406 DPRINTF(Activity, "Deactivating stage.\n");
407 cpu->deactivateStage(O3CPU::CommitIdx);
408 } else if (_nextStatus == Active && _status == Inactive) {
409 DPRINTF(Activity, "Activating stage.\n");
410 cpu->activateStage(O3CPU::CommitIdx);
411 }
412
413 _status = _nextStatus;
414}
415
416template <class Impl>
417void
418DefaultCommit<Impl>::setNextStatus()
419{
420 int squashes = 0;
421
422 std::list<unsigned>::iterator threads = activeThreads->begin();
423 std::list<unsigned>::iterator end = activeThreads->end();
424
425 while (threads != end) {
426 unsigned tid = *threads++;
427
428 if (commitStatus[tid] == ROBSquashing) {
429 squashes++;
430 }
431 }
432
433 squashCounter = squashes;
434
435 // If commit is currently squashing, then it will have activity for the
436 // next cycle. Set its next status as active.
437 if (squashCounter) {
438 _nextStatus = Active;
439 }
440}
441
442template <class Impl>
443bool
444DefaultCommit<Impl>::changedROBEntries()
445{
446 std::list<unsigned>::iterator threads = activeThreads->begin();
447 std::list<unsigned>::iterator end = activeThreads->end();
448
449 while (threads != end) {
450 unsigned tid = *threads++;
451
452 if (changedROBNumEntries[tid]) {
453 return true;
454 }
455 }
456
457 return false;
458}
459
460template <class Impl>
461unsigned
462DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
463{
464 return rob->numFreeEntries(tid);
465}
466
467template <class Impl>
468void
469DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
470{
471 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
472
473 TrapEvent *trap = new TrapEvent(this, tid);
474
475 trap->schedule(curTick + trapLatency);
|
480 trapInFlight[tid] = true;
| 476
477 thread[tid]->trapPending = true;
|
481}
482
483template <class Impl>
484void
485DefaultCommit<Impl>::generateTCEvent(unsigned tid)
486{
| 478}
479
480template <class Impl>
481void
482DefaultCommit<Impl>::generateTCEvent(unsigned tid)
483{
|
487 assert(!trapInFlight[tid]);
| |
488 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
489
490 tcSquash[tid] = true;
491}
492
493template <class Impl>
494void
495DefaultCommit<Impl>::squashAll(unsigned tid)
496{
497 // If we want to include the squashing instruction in the squash,
498 // then use one older sequence number.
499 // Hopefully this doesn't mess things up. Basically I want to squash
500 // all instructions of this thread.
501 InstSeqNum squashed_inst = rob->isEmpty() ?
| 484 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
485
486 tcSquash[tid] = true;
487}
488
489template <class Impl>
490void
491DefaultCommit<Impl>::squashAll(unsigned tid)
492{
493 // If we want to include the squashing instruction in the squash,
494 // then use one older sequence number.
495 // Hopefully this doesn't mess things up. Basically I want to squash
496 // all instructions of this thread.
497 InstSeqNum squashed_inst = rob->isEmpty() ?
|
502 0 : rob->readHeadInst(tid)->seqNum - 1;
| 498 0 : rob->readHeadInst(tid)->seqNum - 1;;
|
503
504 // All younger instructions will be squashed. Set the sequence
505 // number as the youngest instruction in the ROB (0 in this case.
506 // Hopefully nothing breaks.)
507 youngestSeqNum[tid] = 0;
508
509 rob->squash(squashed_inst, tid);
510 changedROBNumEntries[tid] = true;
511
512 // Send back the sequence number of the squashed instruction.
513 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
514
515 // Send back the squash signal to tell stages that they should
516 // squash.
517 toIEW->commitInfo[tid].squash = true;
518
519 // Send back the rob squashing signal so other stages know that
520 // the ROB is in the process of squashing.
521 toIEW->commitInfo[tid].robSquashing = true;
522
523 toIEW->commitInfo[tid].branchMispredict = false;
524
525 toIEW->commitInfo[tid].nextPC = PC[tid];
526 toIEW->commitInfo[tid].nextNPC = nextPC[tid];
527}
528
529template <class Impl>
530void
531DefaultCommit<Impl>::squashFromTrap(unsigned tid)
532{
533 squashAll(tid);
534
535 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
536
537 thread[tid]->trapPending = false;
538 thread[tid]->inSyscall = false;
| 499
500 // All younger instructions will be squashed. Set the sequence
501 // number as the youngest instruction in the ROB (0 in this case.
502 // Hopefully nothing breaks.)
503 youngestSeqNum[tid] = 0;
504
505 rob->squash(squashed_inst, tid);
506 changedROBNumEntries[tid] = true;
507
508 // Send back the sequence number of the squashed instruction.
509 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
510
511 // Send back the squash signal to tell stages that they should
512 // squash.
513 toIEW->commitInfo[tid].squash = true;
514
515 // Send back the rob squashing signal so other stages know that
516 // the ROB is in the process of squashing.
517 toIEW->commitInfo[tid].robSquashing = true;
518
519 toIEW->commitInfo[tid].branchMispredict = false;
520
521 toIEW->commitInfo[tid].nextPC = PC[tid];
522 toIEW->commitInfo[tid].nextNPC = nextPC[tid];
523}
524
525template <class Impl>
526void
527DefaultCommit<Impl>::squashFromTrap(unsigned tid)
528{
529 squashAll(tid);
530
531 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
532
533 thread[tid]->trapPending = false;
534 thread[tid]->inSyscall = false;
|
539 trapInFlight[tid] = false;
| |
540
541 trapSquash[tid] = false;
542
543 commitStatus[tid] = ROBSquashing;
544 cpu->activityThisCycle();
545}
546
547template <class Impl>
548void
549DefaultCommit<Impl>::squashFromTC(unsigned tid)
550{
551 squashAll(tid);
552
553 DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
554
555 thread[tid]->inSyscall = false;
556 assert(!thread[tid]->trapPending);
557
558 commitStatus[tid] = ROBSquashing;
559 cpu->activityThisCycle();
560
561 tcSquash[tid] = false;
562}
563
564template <class Impl>
565void
566DefaultCommit<Impl>::tick()
567{
568 wroteToTimeBuffer = false;
569 _nextStatus = Inactive;
570
571 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
572 cpu->signalDrained();
573 drainPending = false;
574 return;
575 }
576
577 if (activeThreads->empty())
578 return;
579
580 std::list<unsigned>::iterator threads = activeThreads->begin();
581 std::list<unsigned>::iterator end = activeThreads->end();
582
583 // Check if any of the threads are done squashing. Change the
584 // status if they are done.
585 while (threads != end) {
586 unsigned tid = *threads++;
587
| 535
536 trapSquash[tid] = false;
537
538 commitStatus[tid] = ROBSquashing;
539 cpu->activityThisCycle();
540}
541
542template <class Impl>
543void
544DefaultCommit<Impl>::squashFromTC(unsigned tid)
545{
546 squashAll(tid);
547
548 DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
549
550 thread[tid]->inSyscall = false;
551 assert(!thread[tid]->trapPending);
552
553 commitStatus[tid] = ROBSquashing;
554 cpu->activityThisCycle();
555
556 tcSquash[tid] = false;
557}
558
559template <class Impl>
560void
561DefaultCommit<Impl>::tick()
562{
563 wroteToTimeBuffer = false;
564 _nextStatus = Inactive;
565
566 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
567 cpu->signalDrained();
568 drainPending = false;
569 return;
570 }
571
572 if (activeThreads->empty())
573 return;
574
575 std::list<unsigned>::iterator threads = activeThreads->begin();
576 std::list<unsigned>::iterator end = activeThreads->end();
577
578 // Check if any of the threads are done squashing. Change the
579 // status if they are done.
580 while (threads != end) {
581 unsigned tid = *threads++;
582
|
588 // Clear the bit saying if the thread has committed stores
589 // this cycle.
590 committedStores[tid] = false;
591
| |
592 if (commitStatus[tid] == ROBSquashing) {
593
594 if (rob->isDoneSquashing(tid)) {
595 commitStatus[tid] = Running;
596 } else {
597 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
598 " insts this cycle.\n", tid);
599 rob->doSquash(tid);
600 toIEW->commitInfo[tid].robSquashing = true;
601 wroteToTimeBuffer = true;
602 }
603 }
604 }
605
606 commit();
607
608 markCompletedInsts();
609
610 threads = activeThreads->begin();
611
612 while (threads != end) {
613 unsigned tid = *threads++;
614
615 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
616 // The ROB has more instructions it can commit. Its next status
617 // will be active.
618 _nextStatus = Active;
619
620 DynInstPtr inst = rob->readHeadInst(tid);
621
622 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
623 " ROB and ready to commit\n",
624 tid, inst->seqNum, inst->readPC());
625
626 } else if (!rob->isEmpty(tid)) {
627 DynInstPtr inst = rob->readHeadInst(tid);
628
629 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
630 "%#x is head of ROB and not ready\n",
631 tid, inst->seqNum, inst->readPC());
632 }
633
634 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
635 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
636 }
637
638
639 if (wroteToTimeBuffer) {
640 DPRINTF(Activity, "Activity This Cycle.\n");
641 cpu->activityThisCycle();
642 }
643
644 updateStatus();
645}
646
| 583 if (commitStatus[tid] == ROBSquashing) {
584
585 if (rob->isDoneSquashing(tid)) {
586 commitStatus[tid] = Running;
587 } else {
588 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
589 " insts this cycle.\n", tid);
590 rob->doSquash(tid);
591 toIEW->commitInfo[tid].robSquashing = true;
592 wroteToTimeBuffer = true;
593 }
594 }
595 }
596
597 commit();
598
599 markCompletedInsts();
600
601 threads = activeThreads->begin();
602
603 while (threads != end) {
604 unsigned tid = *threads++;
605
606 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
607 // The ROB has more instructions it can commit. Its next status
608 // will be active.
609 _nextStatus = Active;
610
611 DynInstPtr inst = rob->readHeadInst(tid);
612
613 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
614 " ROB and ready to commit\n",
615 tid, inst->seqNum, inst->readPC());
616
617 } else if (!rob->isEmpty(tid)) {
618 DynInstPtr inst = rob->readHeadInst(tid);
619
620 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
621 "%#x is head of ROB and not ready\n",
622 tid, inst->seqNum, inst->readPC());
623 }
624
625 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
626 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
627 }
628
629
630 if (wroteToTimeBuffer) {
631 DPRINTF(Activity, "Activity This Cycle.\n");
632 cpu->activityThisCycle();
633 }
634
635 updateStatus();
636}
637
|
647#if FULL_SYSTEM
| |
648template <class Impl>
649void
| 638template <class Impl>
639void
|
650DefaultCommit<Impl>::handleInterrupt()
| 640DefaultCommit<Impl>::commit()
|
651{
| 641{
|
| 642
643 //////////////////////////////////////
644 // Check for interrupts
645 //////////////////////////////////////
646
647#if FULL_SYSTEM
|
652 if (interrupt != NoFault) {
653 // Wait until the ROB is empty and all stores have drained in
654 // order to enter the interrupt.
655 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
656 // Squash or record that I need to squash this cycle if
657 // an interrupt needed to be handled.
658 DPRINTF(Commit, "Interrupt detected.\n");
659
| 648 if (interrupt != NoFault) {
649 // Wait until the ROB is empty and all stores have drained in
650 // order to enter the interrupt.
651 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
652 // Squash or record that I need to squash this cycle if
653 // an interrupt needed to be handled.
654 DPRINTF(Commit, "Interrupt detected.\n");
655
|
660 Fault new_interrupt = cpu->getInterrupts();
661 assert(new_interrupt == interrupt);
662
663 // Clear the interrupt now that it's going to be handled
664 toIEW->commitInfo[0].clearInterrupt = true;
665
| |
666 assert(!thread[0]->inSyscall);
667 thread[0]->inSyscall = true;
668
669 // CPU will handle interrupt.
670 cpu->processInterrupts(interrupt);
671
672 thread[0]->inSyscall = false;
673
674 commitStatus[0] = TrapPending;
675
676 // Generate trap squash event.
677 generateTrapEvent(0);
678
| 656 assert(!thread[0]->inSyscall);
657 thread[0]->inSyscall = true;
658
659 // CPU will handle interrupt.
660 cpu->processInterrupts(interrupt);
661
662 thread[0]->inSyscall = false;
663
664 commitStatus[0] = TrapPending;
665
666 // Generate trap squash event.
667 generateTrapEvent(0);
668
|
| 669 // Clear the interrupt now that it's been handled
670 toIEW->commitInfo[0].clearInterrupt = true;
|
679 interrupt = NoFault;
680 } else {
681 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
682 }
| 671 interrupt = NoFault;
672 } else {
673 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
674 }
|
683 } else if (commitStatus[0] != TrapPending &&
684 cpu->check_interrupts(cpu->tcBase(0)) &&
685 !trapSquash[0] &&
686 !tcSquash[0]) {
| 675 } else if (cpu->check_interrupts(cpu->tcBase(0)) &&
676 commitStatus[0] != TrapPending &&
677 !trapSquash[0] &&
678 !tcSquash[0]) {
|
687 // Process interrupts if interrupts are enabled, not in PAL
688 // mode, and no other traps or external squashes are currently
689 // pending.
690 // @todo: Allow other threads to handle interrupts.
691
692 // Get any interrupt that happened
693 interrupt = cpu->getInterrupts();
694
695 if (interrupt != NoFault) {
696 // Tell fetch that there is an interrupt pending. This
697 // will make fetch wait until it sees a non PAL-mode PC,
698 // at which point it stops fetching instructions.
699 toIEW->commitInfo[0].interruptPending = true;
700 }
701 }
| 679 // Process interrupts if interrupts are enabled, not in PAL
680 // mode, and no other traps or external squashes are currently
681 // pending.
682 // @todo: Allow other threads to handle interrupts.
683
684 // Get any interrupt that happened
685 interrupt = cpu->getInterrupts();
686
687 if (interrupt != NoFault) {
688 // Tell fetch that there is an interrupt pending. This
689 // will make fetch wait until it sees a non PAL-mode PC,
690 // at which point it stops fetching instructions.
691 toIEW->commitInfo[0].interruptPending = true;
692 }
693 }
|
702}
703#endif // FULL_SYSTEM
| |
704
| 694
|
705template <class Impl>
706void
707DefaultCommit<Impl>::commit()
708{
709
710#if FULL_SYSTEM
711 // Check for any interrupt, and start processing it. Or if we
712 // have an outstanding interrupt and are at a point when it is
713 // valid to take an interrupt, process it.
714 if (cpu->check_interrupts(cpu->tcBase(0))) {
715 handleInterrupt();
716 }
| |
717#endif // FULL_SYSTEM
718
719 ////////////////////////////////////
720 // Check for any possible squashes, handle them first
721 ////////////////////////////////////
722 std::list<unsigned>::iterator threads = activeThreads->begin();
723 std::list<unsigned>::iterator end = activeThreads->end();
724
725 while (threads != end) {
726 unsigned tid = *threads++;
727
728 // Not sure which one takes priority. I think if we have
729 // both, that's a bad sign.
730 if (trapSquash[tid] == true) {
731 assert(!tcSquash[tid]);
732 squashFromTrap(tid);
733 } else if (tcSquash[tid] == true) {
| 695#endif // FULL_SYSTEM
696
697 ////////////////////////////////////
698 // Check for any possible squashes, handle them first
699 ////////////////////////////////////
700 std::list<unsigned>::iterator threads = activeThreads->begin();
701 std::list<unsigned>::iterator end = activeThreads->end();
702
703 while (threads != end) {
704 unsigned tid = *threads++;
705
706 // Not sure which one takes priority. I think if we have
707 // both, that's a bad sign.
708 if (trapSquash[tid] == true) {
709 assert(!tcSquash[tid]);
710 squashFromTrap(tid);
711 } else if (tcSquash[tid] == true) {
|
734 assert(commitStatus[tid] != TrapPending);
| |
735 squashFromTC(tid);
736 }
737
738 // Squashed sequence number must be older than youngest valid
739 // instruction in the ROB. This prevents squashes from younger
740 // instructions overriding squashes from older instructions.
741 if (fromIEW->squash[tid] &&
742 commitStatus[tid] != TrapPending &&
743 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
744
745 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
746 tid,
747 fromIEW->mispredPC[tid],
748 fromIEW->squashedSeqNum[tid]);
749
750 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
751 tid,
752 fromIEW->nextPC[tid]);
753
754 commitStatus[tid] = ROBSquashing;
755
756 // If we want to include the squashing instruction in the squash,
757 // then use one older sequence number.
758 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
759
760#if ISA_HAS_DELAY_SLOT
761 InstSeqNum bdelay_done_seq_num = squashed_inst;
762 bool squash_bdelay_slot = fromIEW->squashDelaySlot[tid];
763 bool branchMispredict = fromIEW->branchMispredict[tid];
764
765 // Squashing/not squashing the branch delay slot only makes
766 // sense when you're squashing from a branch, ie from a branch
767 // mispredict.
768 if (branchMispredict && !squash_bdelay_slot) {
769 bdelay_done_seq_num++;
770 }
771#endif
772
773 if (fromIEW->includeSquashInst[tid] == true) {
774 squashed_inst--;
775#if ISA_HAS_DELAY_SLOT
776 bdelay_done_seq_num--;
777#endif
778 }
| 712 squashFromTC(tid);
713 }
714
715 // Squashed sequence number must be older than youngest valid
716 // instruction in the ROB. This prevents squashes from younger
717 // instructions overriding squashes from older instructions.
718 if (fromIEW->squash[tid] &&
719 commitStatus[tid] != TrapPending &&
720 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
721
722 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
723 tid,
724 fromIEW->mispredPC[tid],
725 fromIEW->squashedSeqNum[tid]);
726
727 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
728 tid,
729 fromIEW->nextPC[tid]);
730
731 commitStatus[tid] = ROBSquashing;
732
733 // If we want to include the squashing instruction in the squash,
734 // then use one older sequence number.
735 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
736
737#if ISA_HAS_DELAY_SLOT
738 InstSeqNum bdelay_done_seq_num = squashed_inst;
739 bool squash_bdelay_slot = fromIEW->squashDelaySlot[tid];
740 bool branchMispredict = fromIEW->branchMispredict[tid];
741
742 // Squashing/not squashing the branch delay slot only makes
743 // sense when you're squashing from a branch, ie from a branch
744 // mispredict.
745 if (branchMispredict && !squash_bdelay_slot) {
746 bdelay_done_seq_num++;
747 }
748#endif
749
750 if (fromIEW->includeSquashInst[tid] == true) {
751 squashed_inst--;
752#if ISA_HAS_DELAY_SLOT
753 bdelay_done_seq_num--;
754#endif
755 }
|
779
| |
780 // All younger instructions will be squashed. Set the sequence
781 // number as the youngest instruction in the ROB.
782 youngestSeqNum[tid] = squashed_inst;
783
784#if ISA_HAS_DELAY_SLOT
785 rob->squash(bdelay_done_seq_num, tid);
786 toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot;
787 toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num;
788#else
789 rob->squash(squashed_inst, tid);
790 toIEW->commitInfo[tid].squashDelaySlot = true;
791#endif
792 changedROBNumEntries[tid] = true;
793
794 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
795
796 toIEW->commitInfo[tid].squash = true;
797
798 // Send back the rob squashing signal so other stages know that
799 // the ROB is in the process of squashing.
800 toIEW->commitInfo[tid].robSquashing = true;
801
802 toIEW->commitInfo[tid].branchMispredict =
803 fromIEW->branchMispredict[tid];
804
805 toIEW->commitInfo[tid].branchTaken =
806 fromIEW->branchTaken[tid];
807
808 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
809 toIEW->commitInfo[tid].nextNPC = fromIEW->nextNPC[tid];
810
811 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
812
813 if (toIEW->commitInfo[tid].branchMispredict) {
814 ++branchMispredicts;
815 }
816 }
817
818 }
819
820 setNextStatus();
821
822 if (squashCounter != numThreads) {
823 // If we're not currently squashing, then get instructions.
824 getInsts();
825
826 // Try to commit any instructions.
827 commitInsts();
828 } else {
829#if ISA_HAS_DELAY_SLOT
830 skidInsert();
831#endif
832 }
833
834 //Check for any activity
835 threads = activeThreads->begin();
836
837 while (threads != end) {
838 unsigned tid = *threads++;
839
840 if (changedROBNumEntries[tid]) {
841 toIEW->commitInfo[tid].usedROB = true;
842 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
843
| 756 // All younger instructions will be squashed. Set the sequence
757 // number as the youngest instruction in the ROB.
758 youngestSeqNum[tid] = squashed_inst;
759
760#if ISA_HAS_DELAY_SLOT
761 rob->squash(bdelay_done_seq_num, tid);
762 toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot;
763 toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num;
764#else
765 rob->squash(squashed_inst, tid);
766 toIEW->commitInfo[tid].squashDelaySlot = true;
767#endif
768 changedROBNumEntries[tid] = true;
769
770 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
771
772 toIEW->commitInfo[tid].squash = true;
773
774 // Send back the rob squashing signal so other stages know that
775 // the ROB is in the process of squashing.
776 toIEW->commitInfo[tid].robSquashing = true;
777
778 toIEW->commitInfo[tid].branchMispredict =
779 fromIEW->branchMispredict[tid];
780
781 toIEW->commitInfo[tid].branchTaken =
782 fromIEW->branchTaken[tid];
783
784 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
785 toIEW->commitInfo[tid].nextNPC = fromIEW->nextNPC[tid];
786
787 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
788
789 if (toIEW->commitInfo[tid].branchMispredict) {
790 ++branchMispredicts;
791 }
792 }
793
794 }
795
796 setNextStatus();
797
798 if (squashCounter != numThreads) {
799 // If we're not currently squashing, then get instructions.
800 getInsts();
801
802 // Try to commit any instructions.
803 commitInsts();
804 } else {
805#if ISA_HAS_DELAY_SLOT
806 skidInsert();
807#endif
808 }
809
810 //Check for any activity
811 threads = activeThreads->begin();
812
813 while (threads != end) {
814 unsigned tid = *threads++;
815
816 if (changedROBNumEntries[tid]) {
817 toIEW->commitInfo[tid].usedROB = true;
818 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
819
|
| 820 if (rob->isEmpty(tid)) {
821 toIEW->commitInfo[tid].emptyROB = true;
822 }
823
|
844 wroteToTimeBuffer = true;
845 changedROBNumEntries[tid] = false;
| 824 wroteToTimeBuffer = true;
825 changedROBNumEntries[tid] = false;
|
846 if (rob->isEmpty(tid))
847 checkEmptyROB[tid] = true;
| |
848 }
| 826 }
|
849
850 // ROB is only considered "empty" for previous stages if: a)
851 // ROB is empty, b) there are no outstanding stores, c) IEW
852 // stage has received any information regarding stores that
853 // committed.
854 // c) is checked by making sure to not consider the ROB empty
855 // on the same cycle as when stores have been committed.
856 // @todo: Make this handle multi-cycle communication between
857 // commit and IEW.
858 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
859 !iewStage->hasStoresToWB() && !committedStores[tid]) {
860 checkEmptyROB[tid] = false;
861 toIEW->commitInfo[tid].usedROB = true;
862 toIEW->commitInfo[tid].emptyROB = true;
863 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
864 wroteToTimeBuffer = true;
865 }
866
| |
867 }
868}
869
870template <class Impl>
871void
872DefaultCommit<Impl>::commitInsts()
873{
874 ////////////////////////////////////
875 // Handle commit
876 // Note that commit will be handled prior to putting new
877 // instructions in the ROB so that the ROB only tries to commit
878 // instructions it has in this current cycle, and not instructions
879 // it is writing in during this cycle. Can't commit and squash
880 // things at the same time...
881 ////////////////////////////////////
882
883 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
884
885 unsigned num_committed = 0;
886
887 DynInstPtr head_inst;
888
889 // Commit as many instructions as possible until the commit bandwidth
890 // limit is reached, or it becomes impossible to commit any more.
891 while (num_committed < commitWidth) {
892 int commit_thread = getCommittingThread();
893
894 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
895 break;
896
897 head_inst = rob->readHeadInst(commit_thread);
898
899 int tid = head_inst->threadNumber;
900
901 assert(tid == commit_thread);
902
903 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
904 head_inst->seqNum, tid);
905
906 // If the head instruction is squashed, it is ready to retire
907 // (be removed from the ROB) at any time.
908 if (head_inst->isSquashed()) {
909
910 DPRINTF(Commit, "Retiring squashed instruction from "
911 "ROB.\n");
912
913 rob->retireHead(commit_thread);
914
915 ++commitSquashedInsts;
916
917 // Record that the number of ROB entries has changed.
918 changedROBNumEntries[tid] = true;
919 } else {
920 PC[tid] = head_inst->readPC();
921 nextPC[tid] = head_inst->readNextPC();
922 nextNPC[tid] = head_inst->readNextNPC();
923
924 // Increment the total number of non-speculative instructions
925 // executed.
926 // Hack for now: it really shouldn't happen until after the
927 // commit is deemed to be successful, but this count is needed
928 // for syscalls.
929 thread[tid]->funcExeInst++;
930
931 // Try to commit the head instruction.
932 bool commit_success = commitHead(head_inst, num_committed);
933
934 if (commit_success) {
935 ++num_committed;
936
937 changedROBNumEntries[tid] = true;
938
939 // Set the doneSeqNum to the youngest committed instruction.
940 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
941
942 ++commitCommittedInsts;
943
944 // To match the old model, don't count nops and instruction
945 // prefetches towards the total commit count.
946 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
947 cpu->instDone(tid);
948 }
949
950 PC[tid] = nextPC[tid];
951#if ISA_HAS_DELAY_SLOT
952 nextPC[tid] = nextNPC[tid];
953 nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
954#else
955 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
956#endif
957
958#if FULL_SYSTEM
959 int count = 0;
960 Addr oldpc;
961 do {
962 // Debug statement. Checks to make sure we're not
963 // currently updating state while handling PC events.
964 if (count == 0)
965 assert(!thread[tid]->inSyscall &&
966 !thread[tid]->trapPending);
967 oldpc = PC[tid];
968 cpu->system->pcEventQueue.service(
969 thread[tid]->getTC());
970 count++;
971 } while (oldpc != PC[tid]);
972 if (count > 1) {
973 DPRINTF(Commit, "PC skip function event, stopping commit\n");
974 break;
975 }
976#endif
977 } else {
978 DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
979 "[tid:%i] [sn:%i].\n",
980 head_inst->readPC(), tid ,head_inst->seqNum);
981 break;
982 }
983 }
984 }
985
986 DPRINTF(CommitRate, "%i\n", num_committed);
987 numCommittedDist.sample(num_committed);
988
989 if (num_committed == commitWidth) {
990 commitEligibleSamples++;
991 }
992}
993
994template <class Impl>
995bool
996DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
997{
998 assert(head_inst);
999
1000 int tid = head_inst->threadNumber;
1001
1002 // If the instruction is not executed yet, then it will need extra
1003 // handling. Signal backwards that it should be executed.
1004 if (!head_inst->isExecuted()) {
1005 // Keep this number correct. We have not yet actually executed
1006 // and committed this instruction.
1007 thread[tid]->funcExeInst--;
1008
| 827 }
828}
829
830template <class Impl>
831void
832DefaultCommit<Impl>::commitInsts()
833{
834 ////////////////////////////////////
835 // Handle commit
836 // Note that commit will be handled prior to putting new
837 // instructions in the ROB so that the ROB only tries to commit
838 // instructions it has in this current cycle, and not instructions
839 // it is writing in during this cycle. Can't commit and squash
840 // things at the same time...
841 ////////////////////////////////////
842
843 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
844
845 unsigned num_committed = 0;
846
847 DynInstPtr head_inst;
848
849 // Commit as many instructions as possible until the commit bandwidth
850 // limit is reached, or it becomes impossible to commit any more.
851 while (num_committed < commitWidth) {
852 int commit_thread = getCommittingThread();
853
854 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
855 break;
856
857 head_inst = rob->readHeadInst(commit_thread);
858
859 int tid = head_inst->threadNumber;
860
861 assert(tid == commit_thread);
862
863 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
864 head_inst->seqNum, tid);
865
866 // If the head instruction is squashed, it is ready to retire
867 // (be removed from the ROB) at any time.
868 if (head_inst->isSquashed()) {
869
870 DPRINTF(Commit, "Retiring squashed instruction from "
871 "ROB.\n");
872
873 rob->retireHead(commit_thread);
874
875 ++commitSquashedInsts;
876
877 // Record that the number of ROB entries has changed.
878 changedROBNumEntries[tid] = true;
879 } else {
880 PC[tid] = head_inst->readPC();
881 nextPC[tid] = head_inst->readNextPC();
882 nextNPC[tid] = head_inst->readNextNPC();
883
884 // Increment the total number of non-speculative instructions
885 // executed.
886 // Hack for now: it really shouldn't happen until after the
887 // commit is deemed to be successful, but this count is needed
888 // for syscalls.
889 thread[tid]->funcExeInst++;
890
891 // Try to commit the head instruction.
892 bool commit_success = commitHead(head_inst, num_committed);
893
894 if (commit_success) {
895 ++num_committed;
896
897 changedROBNumEntries[tid] = true;
898
899 // Set the doneSeqNum to the youngest committed instruction.
900 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
901
902 ++commitCommittedInsts;
903
904 // To match the old model, don't count nops and instruction
905 // prefetches towards the total commit count.
906 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
907 cpu->instDone(tid);
908 }
909
910 PC[tid] = nextPC[tid];
911#if ISA_HAS_DELAY_SLOT
912 nextPC[tid] = nextNPC[tid];
913 nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
914#else
915 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
916#endif
917
918#if FULL_SYSTEM
919 int count = 0;
920 Addr oldpc;
921 do {
922 // Debug statement. Checks to make sure we're not
923 // currently updating state while handling PC events.
924 if (count == 0)
925 assert(!thread[tid]->inSyscall &&
926 !thread[tid]->trapPending);
927 oldpc = PC[tid];
928 cpu->system->pcEventQueue.service(
929 thread[tid]->getTC());
930 count++;
931 } while (oldpc != PC[tid]);
932 if (count > 1) {
933 DPRINTF(Commit, "PC skip function event, stopping commit\n");
934 break;
935 }
936#endif
937 } else {
938 DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
939 "[tid:%i] [sn:%i].\n",
940 head_inst->readPC(), tid ,head_inst->seqNum);
941 break;
942 }
943 }
944 }
945
946 DPRINTF(CommitRate, "%i\n", num_committed);
947 numCommittedDist.sample(num_committed);
948
949 if (num_committed == commitWidth) {
950 commitEligibleSamples++;
951 }
952}
953
954template <class Impl>
955bool
956DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
957{
958 assert(head_inst);
959
960 int tid = head_inst->threadNumber;
961
962 // If the instruction is not executed yet, then it will need extra
963 // handling. Signal backwards that it should be executed.
964 if (!head_inst->isExecuted()) {
965 // Keep this number correct. We have not yet actually executed
966 // and committed this instruction.
967 thread[tid]->funcExeInst--;
968
|
| 969 head_inst->setAtCommit();
970
|
1009 if (head_inst->isNonSpeculative() ||
1010 head_inst->isStoreConditional() ||
1011 head_inst->isMemBarrier() ||
1012 head_inst->isWriteBarrier()) {
1013
1014 DPRINTF(Commit, "Encountered a barrier or non-speculative "
1015 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
1016 head_inst->seqNum, head_inst->readPC());
1017
| 971 if (head_inst->isNonSpeculative() ||
972 head_inst->isStoreConditional() ||
973 head_inst->isMemBarrier() ||
974 head_inst->isWriteBarrier()) {
975
976 DPRINTF(Commit, "Encountered a barrier or non-speculative "
977 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
978 head_inst->seqNum, head_inst->readPC());
979
|
1018 if (inst_num > 0 || iewStage->hasStoresToWB()) {
| 980 // Hack to make sure syscalls/memory barriers/quiesces
981 // aren't executed until all stores write back their data.
982 // This direct communication shouldn't be used for
983 // anything other than this.
984 if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
985 head_inst->isQuiesce()) &&
986 iewStage->hasStoresToWB())
987 {
|
1019 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1020 return false;
| 988 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
989 return false;
|
| 990 } else if (inst_num > 0 || iewStage->hasStoresToWB()) {
991 DPRINTF(Commit, "Waiting to become head of commit.\n");
992 return false;
|
1021 }
1022
1023 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1024
1025 // Change the instruction so it won't try to commit again until
1026 // it is executed.
1027 head_inst->clearCanCommit();
1028
1029 ++commitNonSpecStalls;
1030
1031 return false;
1032 } else if (head_inst->isLoad()) {
| 993 }
994
995 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
996
997 // Change the instruction so it won't try to commit again until
998 // it is executed.
999 head_inst->clearCanCommit();
1000
1001 ++commitNonSpecStalls;
1002
1003 return false;
1004 } else if (head_inst->isLoad()) {
|
1033 if (inst_num > 0 || iewStage->hasStoresToWB()) {
1034 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1035 return false;
1036 }
1037
1038 assert(head_inst->uncacheable());
| |
1039 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
1040 head_inst->seqNum, head_inst->readPC());
1041
1042 // Send back the non-speculative instruction's sequence
1043 // number. Tell the lsq to re-execute the load.
1044 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1045 toIEW->commitInfo[tid].uncached = true;
1046 toIEW->commitInfo[tid].uncachedLoad = head_inst;
1047
1048 head_inst->clearCanCommit();
1049
1050 return false;
1051 } else {
1052 panic("Trying to commit un-executed instruction "
1053 "of unknown type!\n");
1054 }
1055 }
1056
1057 if (head_inst->isThreadSync()) {
1058 // Not handled for now.
1059 panic("Thread sync instructions are not handled yet.\n");
1060 }
1061
| 1005 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
1006 head_inst->seqNum, head_inst->readPC());
1007
1008 // Send back the non-speculative instruction's sequence
1009 // number. Tell the lsq to re-execute the load.
1010 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1011 toIEW->commitInfo[tid].uncached = true;
1012 toIEW->commitInfo[tid].uncachedLoad = head_inst;
1013
1014 head_inst->clearCanCommit();
1015
1016 return false;
1017 } else {
1018 panic("Trying to commit un-executed instruction "
1019 "of unknown type!\n");
1020 }
1021 }
1022
1023 if (head_inst->isThreadSync()) {
1024 // Not handled for now.
1025 panic("Thread sync instructions are not handled yet.\n");
1026 }
1027
|
1062 // Check if the instruction caused a fault. If so, trap.
1063 Fault inst_fault = head_inst->getFault();
1064
| |
1065 // Stores mark themselves as completed.
| 1028 // Stores mark themselves as completed.
|
1066 if (!head_inst->isStore() && inst_fault == NoFault) {
| 1029 if (!head_inst->isStore()) {
|
1067 head_inst->setCompleted();
1068 }
1069
1070#if USE_CHECKER
1071 // Use checker prior to updating anything due to traps or PC
1072 // based events.
1073 if (cpu->checker) {
1074 cpu->checker->verify(head_inst);
1075 }
1076#endif
1077
| 1030 head_inst->setCompleted();
1031 }
1032
1033#if USE_CHECKER
1034 // Use checker prior to updating anything due to traps or PC
1035 // based events.
1036 if (cpu->checker) {
1037 cpu->checker->verify(head_inst);
1038 }
1039#endif
1040
|
| 1041 // Check if the instruction caused a fault. If so, trap.
1042 Fault inst_fault = head_inst->getFault();
1043
|
1078 // DTB will sometimes need the machine instruction for when
1079 // faults happen. So we will set it here, prior to the DTB
1080 // possibly needing it for its fault.
1081 thread[tid]->setInst(
1082 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1083
1084 if (inst_fault != NoFault) {
| 1044 // DTB will sometimes need the machine instruction for when
1045 // faults happen. So we will set it here, prior to the DTB
1046 // possibly needing it for its fault.
1047 thread[tid]->setInst(
1048 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1049
1050 if (inst_fault != NoFault) {
|
| 1051 head_inst->setCompleted();
|
1085 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1086 head_inst->seqNum, head_inst->readPC());
1087
1088 if (iewStage->hasStoresToWB() || inst_num > 0) {
1089 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1090 return false;
1091 }
1092
| 1052 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1053 head_inst->seqNum, head_inst->readPC());
1054
1055 if (iewStage->hasStoresToWB() || inst_num > 0) {
1056 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1057 return false;
1058 }
1059
|
1093 head_inst->setCompleted();
1094
| |
1095#if USE_CHECKER
1096 if (cpu->checker && head_inst->isStore()) {
1097 cpu->checker->verify(head_inst);
1098 }
1099#endif
1100
1101 assert(!thread[tid]->inSyscall);
1102
1103 // Mark that we're in state update mode so that the trap's
1104 // execution doesn't generate extra squashes.
1105 thread[tid]->inSyscall = true;
1106
1107 // Execute the trap. Although it's slightly unrealistic in
1108 // terms of timing (as it doesn't wait for the full timing of
1109 // the trap event to complete before updating state), it's
1110 // needed to update the state as soon as possible. This
1111 // prevents external agents from changing any specific state
1112 // that the trap need.
1113 cpu->trap(inst_fault, tid);
1114
1115 // Exit state update mode to avoid accidental updating.
1116 thread[tid]->inSyscall = false;
1117
1118 commitStatus[tid] = TrapPending;
1119
| 1060#if USE_CHECKER
1061 if (cpu->checker && head_inst->isStore()) {
1062 cpu->checker->verify(head_inst);
1063 }
1064#endif
1065
1066 assert(!thread[tid]->inSyscall);
1067
1068 // Mark that we're in state update mode so that the trap's
1069 // execution doesn't generate extra squashes.
1070 thread[tid]->inSyscall = true;
1071
1072 // Execute the trap. Although it's slightly unrealistic in
1073 // terms of timing (as it doesn't wait for the full timing of
1074 // the trap event to complete before updating state), it's
1075 // needed to update the state as soon as possible. This
1076 // prevents external agents from changing any specific state
1077 // that the trap need.
1078 cpu->trap(inst_fault, tid);
1079
1080 // Exit state update mode to avoid accidental updating.
1081 thread[tid]->inSyscall = false;
1082
1083 commitStatus[tid] = TrapPending;
1084
|
1120 if (head_inst->traceData) {
1121 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1122 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1123 head_inst->traceData->finalize();
1124 head_inst->traceData = NULL;
1125 }
1126
| |
1127 // Generate trap squash event.
1128 generateTrapEvent(tid);
1129// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC());
1130 return false;
1131 }
1132
1133 updateComInstStats(head_inst);
1134
1135#if FULL_SYSTEM
1136 if (thread[tid]->profile) {
1137// bool usermode = TheISA::inUserMode(thread[tid]->getTC());
1138// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC();
1139 thread[tid]->profilePC = head_inst->readPC();
1140 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1141 head_inst->staticInst);
1142
1143 if (node)
1144 thread[tid]->profileNode = node;
1145 }
1146#endif
1147
1148 if (head_inst->traceData) {
1149 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1150 head_inst->traceData->setCPSeq(thread[tid]->numInst);
| 1085 // Generate trap squash event.
1086 generateTrapEvent(tid);
1087// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC());
1088 return false;
1089 }
1090
1091 updateComInstStats(head_inst);
1092
1093#if FULL_SYSTEM
1094 if (thread[tid]->profile) {
1095// bool usermode = TheISA::inUserMode(thread[tid]->getTC());
1096// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC();
1097 thread[tid]->profilePC = head_inst->readPC();
1098 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1099 head_inst->staticInst);
1100
1101 if (node)
1102 thread[tid]->profileNode = node;
1103 }
1104#endif
1105
1106 if (head_inst->traceData) {
1107 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1108 head_inst->traceData->setCPSeq(thread[tid]->numInst);
|
1151 head_inst->traceData->finalize();
| 1109 head_inst->traceData->dump();
1110 delete head_inst->traceData;
|
1152 head_inst->traceData = NULL;
1153 }
1154
1155 // Update the commit rename map
1156 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1157 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1158 head_inst->renamedDestRegIdx(i));
1159 }
1160
1161 if (head_inst->isCopy())
1162 panic("Should not commit any copy instructions!");
1163
1164 // Finally clear the head ROB entry.
1165 rob->retireHead(tid);
1166
| 1111 head_inst->traceData = NULL;
1112 }
1113
1114 // Update the commit rename map
1115 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1116 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1117 head_inst->renamedDestRegIdx(i));
1118 }
1119
1120 if (head_inst->isCopy())
1121 panic("Should not commit any copy instructions!");
1122
1123 // Finally clear the head ROB entry.
1124 rob->retireHead(tid);
1125
|
1167 // If this was a store, record it for this cycle.
1168 if (head_inst->isStore())
1169 committedStores[tid] = true;
1170
| |
1171 // Return true to indicate that we have committed an instruction.
1172 return true;
1173}
1174
1175template <class Impl>
1176void
1177DefaultCommit<Impl>::getInsts()
1178{
1179 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1180
1181#if ISA_HAS_DELAY_SLOT
1182 // Read any renamed instructions and place them into the ROB.
1183 int insts_to_process = std::min((int)renameWidth,
1184 (int)(fromRename->size + skidBuffer.size()));
1185 int rename_idx = 0;
1186
1187 DPRINTF(Commit, "%i insts available to process. Rename Insts:%i "
1188 "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size,
1189 skidBuffer.size());
1190#else
1191 // Read any renamed instructions and place them into the ROB.
1192 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1193#endif
1194
1195
1196 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1197 DynInstPtr inst;
1198
1199#if ISA_HAS_DELAY_SLOT
1200 // Get insts from skidBuffer or from Rename
1201 if (skidBuffer.size() > 0) {
1202 DPRINTF(Commit, "Grabbing skidbuffer inst.\n");
1203 inst = skidBuffer.front();
1204 skidBuffer.pop();
1205 } else {
1206 DPRINTF(Commit, "Grabbing rename inst.\n");
1207 inst = fromRename->insts[rename_idx++];
1208 }
1209#else
1210 inst = fromRename->insts[inst_num];
1211#endif
1212 int tid = inst->threadNumber;
1213
1214 if (!inst->isSquashed() &&
| 1126 // Return true to indicate that we have committed an instruction.
1127 return true;
1128}
1129
1130template <class Impl>
1131void
1132DefaultCommit<Impl>::getInsts()
1133{
1134 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1135
1136#if ISA_HAS_DELAY_SLOT
1137 // Read any renamed instructions and place them into the ROB.
1138 int insts_to_process = std::min((int)renameWidth,
1139 (int)(fromRename->size + skidBuffer.size()));
1140 int rename_idx = 0;
1141
1142 DPRINTF(Commit, "%i insts available to process. Rename Insts:%i "
1143 "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size,
1144 skidBuffer.size());
1145#else
1146 // Read any renamed instructions and place them into the ROB.
1147 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1148#endif
1149
1150
1151 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1152 DynInstPtr inst;
1153
1154#if ISA_HAS_DELAY_SLOT
1155 // Get insts from skidBuffer or from Rename
1156 if (skidBuffer.size() > 0) {
1157 DPRINTF(Commit, "Grabbing skidbuffer inst.\n");
1158 inst = skidBuffer.front();
1159 skidBuffer.pop();
1160 } else {
1161 DPRINTF(Commit, "Grabbing rename inst.\n");
1162 inst = fromRename->insts[rename_idx++];
1163 }
1164#else
1165 inst = fromRename->insts[inst_num];
1166#endif
1167 int tid = inst->threadNumber;
1168
1169 if (!inst->isSquashed() &&
|
1215 commitStatus[tid] != ROBSquashing &&
1216 commitStatus[tid] != TrapPending) {
| 1170 commitStatus[tid] != ROBSquashing) {
|
1217 changedROBNumEntries[tid] = true;
1218
1219 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1220 inst->readPC(), inst->seqNum, tid);
1221
1222 rob->insertInst(inst);
1223
1224 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1225
1226 youngestSeqNum[tid] = inst->seqNum;
1227 } else {
1228 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1229 "squashed, skipping.\n",
1230 inst->readPC(), inst->seqNum, tid);
1231 }
1232 }
1233
1234#if ISA_HAS_DELAY_SLOT
1235 if (rename_idx < fromRename->size) {
1236 DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n");
1237
1238 for (;
1239 rename_idx < fromRename->size;
1240 rename_idx++) {
1241 DynInstPtr inst = fromRename->insts[rename_idx];
1242
1243 if (!inst->isSquashed()) {
1244 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1245 "skidBuffer.\n", inst->readPC(), inst->seqNum,
1246 inst->threadNumber);
1247 skidBuffer.push(inst);
1248 } else {
1249 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1250 "squashed, skipping.\n",
1251 inst->readPC(), inst->seqNum, inst->threadNumber);
1252 }
1253 }
1254 }
1255#endif
1256
1257}
1258
1259template <class Impl>
1260void
1261DefaultCommit<Impl>::skidInsert()
1262{
1263 DPRINTF(Commit, "Attempting to any instructions from rename into "
1264 "skidBuffer.\n");
1265
1266 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1267 DynInstPtr inst = fromRename->insts[inst_num];
1268
1269 if (!inst->isSquashed()) {
1270 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1271 "skidBuffer.\n", inst->readPC(), inst->seqNum,
1272 inst->threadNumber);
1273 skidBuffer.push(inst);
1274 } else {
1275 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1276 "squashed, skipping.\n",
1277 inst->readPC(), inst->seqNum, inst->threadNumber);
1278 }
1279 }
1280}
1281
1282template <class Impl>
1283void
1284DefaultCommit<Impl>::markCompletedInsts()
1285{
1286 // Grab completed insts out of the IEW instruction queue, and mark
1287 // instructions completed within the ROB.
1288 for (int inst_num = 0;
1289 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1290 ++inst_num)
1291 {
1292 if (!fromIEW->insts[inst_num]->isSquashed()) {
1293 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1294 "within ROB.\n",
1295 fromIEW->insts[inst_num]->threadNumber,
1296 fromIEW->insts[inst_num]->readPC(),
1297 fromIEW->insts[inst_num]->seqNum);
1298
1299 // Mark the instruction as ready to commit.
1300 fromIEW->insts[inst_num]->setCanCommit();
1301 }
1302 }
1303}
1304
1305template <class Impl>
1306bool
1307DefaultCommit<Impl>::robDoneSquashing()
1308{
1309 std::list<unsigned>::iterator threads = activeThreads->begin();
1310 std::list<unsigned>::iterator end = activeThreads->end();
1311
1312 while (threads != end) {
1313 unsigned tid = *threads++;
1314
1315 if (!rob->isDoneSquashing(tid))
1316 return false;
1317 }
1318
1319 return true;
1320}
1321
1322template <class Impl>
1323void
1324DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1325{
1326 unsigned thread = inst->threadNumber;
1327
1328 //
1329 // Pick off the software prefetches
1330 //
1331#ifdef TARGET_ALPHA
1332 if (inst->isDataPrefetch()) {
1333 statComSwp[thread]++;
1334 } else {
1335 statComInst[thread]++;
1336 }
1337#else
1338 statComInst[thread]++;
1339#endif
1340
1341 //
1342 // Control Instructions
1343 //
1344 if (inst->isControl())
1345 statComBranches[thread]++;
1346
1347 //
1348 // Memory references
1349 //
1350 if (inst->isMemRef()) {
1351 statComRefs[thread]++;
1352
1353 if (inst->isLoad()) {
1354 statComLoads[thread]++;
1355 }
1356 }
1357
1358 if (inst->isMemBarrier()) {
1359 statComMembars[thread]++;
1360 }
1361}
1362
1363////////////////////////////////////////
1364// //
1365// SMT COMMIT POLICY MAINTAINED HERE //
1366// //
1367////////////////////////////////////////
1368template <class Impl>
1369int
1370DefaultCommit<Impl>::getCommittingThread()
1371{
1372 if (numThreads > 1) {
1373 switch (commitPolicy) {
1374
1375 case Aggressive:
1376 //If Policy is Aggressive, commit will call
1377 //this function multiple times per
1378 //cycle
1379 return oldestReady();
1380
1381 case RoundRobin:
1382 return roundRobin();
1383
1384 case OldestReady:
1385 return oldestReady();
1386
1387 default:
1388 return -1;
1389 }
1390 } else {
1391 assert(!activeThreads->empty());
1392 int tid = activeThreads->front();
1393
1394 if (commitStatus[tid] == Running ||
1395 commitStatus[tid] == Idle ||
1396 commitStatus[tid] == FetchTrapPending) {
1397 return tid;
1398 } else {
1399 return -1;
1400 }
1401 }
1402}
1403
1404template<class Impl>
1405int
1406DefaultCommit<Impl>::roundRobin()
1407{
1408 std::list<unsigned>::iterator pri_iter = priority_list.begin();
1409 std::list<unsigned>::iterator end = priority_list.end();
1410
1411 while (pri_iter != end) {
1412 unsigned tid = *pri_iter;
1413
1414 if (commitStatus[tid] == Running ||
1415 commitStatus[tid] == Idle ||
1416 commitStatus[tid] == FetchTrapPending) {
1417
1418 if (rob->isHeadReady(tid)) {
1419 priority_list.erase(pri_iter);
1420 priority_list.push_back(tid);
1421
1422 return tid;
1423 }
1424 }
1425
1426 pri_iter++;
1427 }
1428
1429 return -1;
1430}
1431
1432template<class Impl>
1433int
1434DefaultCommit<Impl>::oldestReady()
1435{
1436 unsigned oldest = 0;
1437 bool first = true;
1438
1439 std::list<unsigned>::iterator threads = activeThreads->begin();
1440 std::list<unsigned>::iterator end = activeThreads->end();
1441
1442 while (threads != end) {
1443 unsigned tid = *threads++;
1444
1445 if (!rob->isEmpty(tid) &&
1446 (commitStatus[tid] == Running ||
1447 commitStatus[tid] == Idle ||
1448 commitStatus[tid] == FetchTrapPending)) {
1449
1450 if (rob->isHeadReady(tid)) {
1451
1452 DynInstPtr head_inst = rob->readHeadInst(tid);
1453
1454 if (first) {
1455 oldest = tid;
1456 first = false;
1457 } else if (head_inst->seqNum < oldest) {
1458 oldest = tid;
1459 }
1460 }
1461 }
1462 }
1463
1464 if (!first) {
1465 return oldest;
1466 } else {
1467 return -1;
1468 }
1469}
| 1171 changedROBNumEntries[tid] = true;
1172
1173 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1174 inst->readPC(), inst->seqNum, tid);
1175
1176 rob->insertInst(inst);
1177
1178 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1179
1180 youngestSeqNum[tid] = inst->seqNum;
1181 } else {
1182 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1183 "squashed, skipping.\n",
1184 inst->readPC(), inst->seqNum, tid);
1185 }
1186 }
1187
1188#if ISA_HAS_DELAY_SLOT
1189 if (rename_idx < fromRename->size) {
1190 DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n");
1191
1192 for (;
1193 rename_idx < fromRename->size;
1194 rename_idx++) {
1195 DynInstPtr inst = fromRename->insts[rename_idx];
1196
1197 if (!inst->isSquashed()) {
1198 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1199 "skidBuffer.\n", inst->readPC(), inst->seqNum,
1200 inst->threadNumber);
1201 skidBuffer.push(inst);
1202 } else {
1203 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1204 "squashed, skipping.\n",
1205 inst->readPC(), inst->seqNum, inst->threadNumber);
1206 }
1207 }
1208 }
1209#endif
1210
1211}
1212
1213template <class Impl>
1214void
1215DefaultCommit<Impl>::skidInsert()
1216{
1217 DPRINTF(Commit, "Attempting to any instructions from rename into "
1218 "skidBuffer.\n");
1219
1220 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1221 DynInstPtr inst = fromRename->insts[inst_num];
1222
1223 if (!inst->isSquashed()) {
1224 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1225 "skidBuffer.\n", inst->readPC(), inst->seqNum,
1226 inst->threadNumber);
1227 skidBuffer.push(inst);
1228 } else {
1229 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1230 "squashed, skipping.\n",
1231 inst->readPC(), inst->seqNum, inst->threadNumber);
1232 }
1233 }
1234}
1235
1236template <class Impl>
1237void
1238DefaultCommit<Impl>::markCompletedInsts()
1239{
1240 // Grab completed insts out of the IEW instruction queue, and mark
1241 // instructions completed within the ROB.
1242 for (int inst_num = 0;
1243 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1244 ++inst_num)
1245 {
1246 if (!fromIEW->insts[inst_num]->isSquashed()) {
1247 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1248 "within ROB.\n",
1249 fromIEW->insts[inst_num]->threadNumber,
1250 fromIEW->insts[inst_num]->readPC(),
1251 fromIEW->insts[inst_num]->seqNum);
1252
1253 // Mark the instruction as ready to commit.
1254 fromIEW->insts[inst_num]->setCanCommit();
1255 }
1256 }
1257}
1258
1259template <class Impl>
1260bool
1261DefaultCommit<Impl>::robDoneSquashing()
1262{
1263 std::list<unsigned>::iterator threads = activeThreads->begin();
1264 std::list<unsigned>::iterator end = activeThreads->end();
1265
1266 while (threads != end) {
1267 unsigned tid = *threads++;
1268
1269 if (!rob->isDoneSquashing(tid))
1270 return false;
1271 }
1272
1273 return true;
1274}
1275
1276template <class Impl>
1277void
1278DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1279{
1280 unsigned thread = inst->threadNumber;
1281
1282 //
1283 // Pick off the software prefetches
1284 //
1285#ifdef TARGET_ALPHA
1286 if (inst->isDataPrefetch()) {
1287 statComSwp[thread]++;
1288 } else {
1289 statComInst[thread]++;
1290 }
1291#else
1292 statComInst[thread]++;
1293#endif
1294
1295 //
1296 // Control Instructions
1297 //
1298 if (inst->isControl())
1299 statComBranches[thread]++;
1300
1301 //
1302 // Memory references
1303 //
1304 if (inst->isMemRef()) {
1305 statComRefs[thread]++;
1306
1307 if (inst->isLoad()) {
1308 statComLoads[thread]++;
1309 }
1310 }
1311
1312 if (inst->isMemBarrier()) {
1313 statComMembars[thread]++;
1314 }
1315}
1316
1317////////////////////////////////////////
1318// //
1319// SMT COMMIT POLICY MAINTAINED HERE //
1320// //
1321////////////////////////////////////////
1322template <class Impl>
1323int
1324DefaultCommit<Impl>::getCommittingThread()
1325{
1326 if (numThreads > 1) {
1327 switch (commitPolicy) {
1328
1329 case Aggressive:
1330 //If Policy is Aggressive, commit will call
1331 //this function multiple times per
1332 //cycle
1333 return oldestReady();
1334
1335 case RoundRobin:
1336 return roundRobin();
1337
1338 case OldestReady:
1339 return oldestReady();
1340
1341 default:
1342 return -1;
1343 }
1344 } else {
1345 assert(!activeThreads->empty());
1346 int tid = activeThreads->front();
1347
1348 if (commitStatus[tid] == Running ||
1349 commitStatus[tid] == Idle ||
1350 commitStatus[tid] == FetchTrapPending) {
1351 return tid;
1352 } else {
1353 return -1;
1354 }
1355 }
1356}
1357
1358template<class Impl>
1359int
1360DefaultCommit<Impl>::roundRobin()
1361{
1362 std::list<unsigned>::iterator pri_iter = priority_list.begin();
1363 std::list<unsigned>::iterator end = priority_list.end();
1364
1365 while (pri_iter != end) {
1366 unsigned tid = *pri_iter;
1367
1368 if (commitStatus[tid] == Running ||
1369 commitStatus[tid] == Idle ||
1370 commitStatus[tid] == FetchTrapPending) {
1371
1372 if (rob->isHeadReady(tid)) {
1373 priority_list.erase(pri_iter);
1374 priority_list.push_back(tid);
1375
1376 return tid;
1377 }
1378 }
1379
1380 pri_iter++;
1381 }
1382
1383 return -1;
1384}
1385
1386template<class Impl>
1387int
1388DefaultCommit<Impl>::oldestReady()
1389{
1390 unsigned oldest = 0;
1391 bool first = true;
1392
1393 std::list<unsigned>::iterator threads = activeThreads->begin();
1394 std::list<unsigned>::iterator end = activeThreads->end();
1395
1396 while (threads != end) {
1397 unsigned tid = *threads++;
1398
1399 if (!rob->isEmpty(tid) &&
1400 (commitStatus[tid] == Running ||
1401 commitStatus[tid] == Idle ||
1402 commitStatus[tid] == FetchTrapPending)) {
1403
1404 if (rob->isHeadReady(tid)) {
1405
1406 DynInstPtr head_inst = rob->readHeadInst(tid);
1407
1408 if (first) {
1409 oldest = tid;
1410 first = false;
1411 } else if (head_inst->seqNum < oldest) {
1412 oldest = tid;
1413 }
1414 }
1415 }
1416 }
1417
1418 if (!first) {
1419 return oldest;
1420 } else {
1421 return -1;
1422 }
1423}
|