1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
35#include <algorithm>
36#include <string>
37
38#include "arch/utility.hh"
39#include "base/loader/symtab.hh"
40#include "base/timebuf.hh"
41#include "cpu/exetrace.hh"
42#include "cpu/o3/commit.hh"
43#include "cpu/o3/thread_state.hh"
44
45#if USE_CHECKER
46#include "cpu/checker/cpu.hh"
47#endif
48
49template <class Impl>
50DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
51 unsigned _tid)
52 : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
53{
54 this->setFlags(Event::AutoDelete);
55}
56
57template <class Impl>
58void
59DefaultCommit<Impl>::TrapEvent::process()
60{
61 // This will get reset by commit if it was switched out at the
62 // time of this event processing.
63 commit->trapSquash[tid] = true;
64}
65
66template <class Impl>
67const char *
68DefaultCommit<Impl>::TrapEvent::description()
69{
70 return "Trap event";
71}
72
73template <class Impl>
74DefaultCommit<Impl>::DefaultCommit(Params *params)
75 : squashCounter(0),
76 iewToCommitDelay(params->iewToCommitDelay),
77 commitToIEWDelay(params->commitToIEWDelay),
78 renameToROBDelay(params->renameToROBDelay),
79 fetchToCommitDelay(params->commitToFetchDelay),
80 renameWidth(params->renameWidth),
81 commitWidth(params->commitWidth),
82 numThreads(params->numberOfThreads),
83 drainPending(false),
84 switchedOut(false),
85 trapLatency(params->trapLatency)
86{
87 _status = Active;
88 _nextStatus = Inactive;
89 std::string policy = params->smtCommitPolicy;
90
91 //Convert string to lowercase
92 std::transform(policy.begin(), policy.end(), policy.begin(),
93 (int(*)(int)) tolower);
94
95 //Assign commit policy
96 if (policy == "aggressive"){
97 commitPolicy = Aggressive;
98
99 DPRINTF(Commit,"Commit Policy set to Aggressive.");
100 } else if (policy == "roundrobin"){
101 commitPolicy = RoundRobin;
102
103 //Set-Up Priority List
104 for (int tid=0; tid < numThreads; tid++) {
105 priority_list.push_back(tid);
106 }
107
108 DPRINTF(Commit,"Commit Policy set to Round Robin.");
109 } else if (policy == "oldestready"){
110 commitPolicy = OldestReady;
111
112 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
113 } else {
114 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
115 "RoundRobin,OldestReady}");
116 }
117
118 for (int i=0; i < numThreads; i++) {
119 commitStatus[i] = Idle;
120 changedROBNumEntries[i] = false;
121 trapSquash[i] = false;
122 tcSquash[i] = false;
123 PC[i] = nextPC[i] = nextNPC[i] = 0;
124 }
125#if FULL_SYSTEM
126 interrupt = NoFault;
127#endif
128}
129
130template <class Impl>
131std::string
132DefaultCommit<Impl>::name() const
133{
134 return cpu->name() + ".commit";
135}
136
137template <class Impl>
138void
139DefaultCommit<Impl>::regStats()
140{
141 using namespace Stats;
142 commitCommittedInsts
143 .name(name() + ".commitCommittedInsts")
144 .desc("The number of committed instructions")
145 .prereq(commitCommittedInsts);
146 commitSquashedInsts
147 .name(name() + ".commitSquashedInsts")
148 .desc("The number of squashed insts skipped by commit")
149 .prereq(commitSquashedInsts);
150 commitSquashEvents
151 .name(name() + ".commitSquashEvents")
152 .desc("The number of times commit is told to squash")
153 .prereq(commitSquashEvents);
154 commitNonSpecStalls
155 .name(name() + ".commitNonSpecStalls")
156 .desc("The number of times commit has been forced to stall to "
157 "communicate backwards")
158 .prereq(commitNonSpecStalls);
159 branchMispredicts
160 .name(name() + ".branchMispredicts")
161 .desc("The number of times a branch was mispredicted")
162 .prereq(branchMispredicts);
163 numCommittedDist
164 .init(0,commitWidth,1)
165 .name(name() + ".COM:committed_per_cycle")
166 .desc("Number of insts commited each cycle")
167 .flags(Stats::pdf)
168 ;
169
170 statComInst
171 .init(cpu->number_of_threads)
172 .name(name() + ".COM:count")
173 .desc("Number of instructions committed")
174 .flags(total)
175 ;
176
177 statComSwp
178 .init(cpu->number_of_threads)
179 .name(name() + ".COM:swp_count")
180 .desc("Number of s/w prefetches committed")
181 .flags(total)
182 ;
183
184 statComRefs
185 .init(cpu->number_of_threads)
186 .name(name() + ".COM:refs")
187 .desc("Number of memory references committed")
188 .flags(total)
189 ;
190
191 statComLoads
192 .init(cpu->number_of_threads)
193 .name(name() + ".COM:loads")
194 .desc("Number of loads committed")
195 .flags(total)
196 ;
197
198 statComMembars
199 .init(cpu->number_of_threads)
200 .name(name() + ".COM:membars")
201 .desc("Number of memory barriers committed")
202 .flags(total)
203 ;
204
205 statComBranches
206 .init(cpu->number_of_threads)
207 .name(name() + ".COM:branches")
208 .desc("Number of branches committed")
209 .flags(total)
210 ;
211
212 commitEligible
213 .init(cpu->number_of_threads)
214 .name(name() + ".COM:bw_limited")
215 .desc("number of insts not committed due to BW limits")
216 .flags(total)
217 ;
218
219 commitEligibleSamples
220 .name(name() + ".COM:bw_lim_events")
221 .desc("number cycles where commit BW limit reached")
222 ;
223}
224
225template <class Impl>
226void
227DefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr)
228{
229 DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
230 cpu = cpu_ptr;
231
232 // Commit must broadcast the number of free entries it has at the start of
233 // the simulation, so it starts as active.
234 cpu->activateStage(O3CPU::CommitIdx);
235
236 trapLatency = cpu->cycles(trapLatency);
237}
238
239template <class Impl>
240void
241DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
242{
243 thread = threads;
244}
245
246template <class Impl>
247void
248DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
249{
250 DPRINTF(Commit, "Commit: Setting time buffer pointer.\n");
251 timeBuffer = tb_ptr;
252
253 // Setup wire to send information back to IEW.
254 toIEW = timeBuffer->getWire(0);
255
256 // Setup wire to read data from IEW (for the ROB).
257 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
258}
259
260template <class Impl>
261void
262DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
263{
264 DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n");
265 fetchQueue = fq_ptr;
266
267 // Setup wire to get instructions from rename (for the ROB).
268 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
269}
270
271template <class Impl>
272void
273DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
274{
275 DPRINTF(Commit, "Commit: Setting rename queue pointer.\n");
276 renameQueue = rq_ptr;
277
278 // Setup wire to get instructions from rename (for the ROB).
279 fromRename = renameQueue->getWire(-renameToROBDelay);
280}
281
282template <class Impl>
283void
284DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
285{
286 DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n");
287 iewQueue = iq_ptr;
288
289 // Setup wire to get instructions from IEW.
290 fromIEW = iewQueue->getWire(-iewToCommitDelay);
291}
292
293template <class Impl>
294void
295DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
296{
297 iewStage = iew_stage;
298}
299
300template<class Impl>
301void
302DefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
303{
304 DPRINTF(Commit, "Commit: Setting active threads list pointer.\n");
305 activeThreads = at_ptr;
306}
307
308template <class Impl>
309void
310DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
311{
312 DPRINTF(Commit, "Setting rename map pointers.\n");
313
314 for (int i=0; i < numThreads; i++) {
315 renameMap[i] = &rm_ptr[i];
316 }
317}
318
319template <class Impl>
320void
321DefaultCommit<Impl>::setROB(ROB *rob_ptr)
322{
323 DPRINTF(Commit, "Commit: Setting ROB pointer.\n");
324 rob = rob_ptr;
325}
326
327template <class Impl>
328void
329DefaultCommit<Impl>::initStage()
330{
331 rob->setActiveThreads(activeThreads);
332 rob->resetEntries();
333
334 // Broadcast the number of free entries.
335 for (int i=0; i < numThreads; i++) {
336 toIEW->commitInfo[i].usedROB = true;
337 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
338 }
339
340 cpu->activityThisCycle();
341}
342
343template <class Impl>
344bool
345DefaultCommit<Impl>::drain()
346{
347 drainPending = true;
348
349 return false;
350}
351
352template <class Impl>
353void
354DefaultCommit<Impl>::switchOut()
355{
356 switchedOut = true;
357 drainPending = false;
358 rob->switchOut();
359}
360
361template <class Impl>
362void
363DefaultCommit<Impl>::resume()
364{
365 drainPending = false;
366}
367
368template <class Impl>
369void
370DefaultCommit<Impl>::takeOverFrom()
371{
372 switchedOut = false;
373 _status = Active;
374 _nextStatus = Inactive;
375 for (int i=0; i < numThreads; i++) {
376 commitStatus[i] = Idle;
377 changedROBNumEntries[i] = false;
378 trapSquash[i] = false;
379 tcSquash[i] = false;
380 }
381 squashCounter = 0;
382 rob->takeOverFrom();
383}
384
385template <class Impl>
386void
387DefaultCommit<Impl>::updateStatus()
388{
389 // reset ROB changed variable
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
35#include <algorithm>
36#include <string>
37
38#include "arch/utility.hh"
39#include "base/loader/symtab.hh"
40#include "base/timebuf.hh"
41#include "cpu/exetrace.hh"
42#include "cpu/o3/commit.hh"
43#include "cpu/o3/thread_state.hh"
44
45#if USE_CHECKER
46#include "cpu/checker/cpu.hh"
47#endif
48
49template <class Impl>
50DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
51 unsigned _tid)
52 : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
53{
54 this->setFlags(Event::AutoDelete);
55}
56
57template <class Impl>
58void
59DefaultCommit<Impl>::TrapEvent::process()
60{
61 // This will get reset by commit if it was switched out at the
62 // time of this event processing.
63 commit->trapSquash[tid] = true;
64}
65
66template <class Impl>
67const char *
68DefaultCommit<Impl>::TrapEvent::description()
69{
70 return "Trap event";
71}
72
73template <class Impl>
74DefaultCommit<Impl>::DefaultCommit(Params *params)
75 : squashCounter(0),
76 iewToCommitDelay(params->iewToCommitDelay),
77 commitToIEWDelay(params->commitToIEWDelay),
78 renameToROBDelay(params->renameToROBDelay),
79 fetchToCommitDelay(params->commitToFetchDelay),
80 renameWidth(params->renameWidth),
81 commitWidth(params->commitWidth),
82 numThreads(params->numberOfThreads),
83 drainPending(false),
84 switchedOut(false),
85 trapLatency(params->trapLatency)
86{
87 _status = Active;
88 _nextStatus = Inactive;
89 std::string policy = params->smtCommitPolicy;
90
91 //Convert string to lowercase
92 std::transform(policy.begin(), policy.end(), policy.begin(),
93 (int(*)(int)) tolower);
94
95 //Assign commit policy
96 if (policy == "aggressive"){
97 commitPolicy = Aggressive;
98
99 DPRINTF(Commit,"Commit Policy set to Aggressive.");
100 } else if (policy == "roundrobin"){
101 commitPolicy = RoundRobin;
102
103 //Set-Up Priority List
104 for (int tid=0; tid < numThreads; tid++) {
105 priority_list.push_back(tid);
106 }
107
108 DPRINTF(Commit,"Commit Policy set to Round Robin.");
109 } else if (policy == "oldestready"){
110 commitPolicy = OldestReady;
111
112 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
113 } else {
114 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
115 "RoundRobin,OldestReady}");
116 }
117
118 for (int i=0; i < numThreads; i++) {
119 commitStatus[i] = Idle;
120 changedROBNumEntries[i] = false;
121 trapSquash[i] = false;
122 tcSquash[i] = false;
123 PC[i] = nextPC[i] = nextNPC[i] = 0;
124 }
125#if FULL_SYSTEM
126 interrupt = NoFault;
127#endif
128}
129
130template <class Impl>
131std::string
132DefaultCommit<Impl>::name() const
133{
134 return cpu->name() + ".commit";
135}
136
137template <class Impl>
138void
139DefaultCommit<Impl>::regStats()
140{
141 using namespace Stats;
142 commitCommittedInsts
143 .name(name() + ".commitCommittedInsts")
144 .desc("The number of committed instructions")
145 .prereq(commitCommittedInsts);
146 commitSquashedInsts
147 .name(name() + ".commitSquashedInsts")
148 .desc("The number of squashed insts skipped by commit")
149 .prereq(commitSquashedInsts);
150 commitSquashEvents
151 .name(name() + ".commitSquashEvents")
152 .desc("The number of times commit is told to squash")
153 .prereq(commitSquashEvents);
154 commitNonSpecStalls
155 .name(name() + ".commitNonSpecStalls")
156 .desc("The number of times commit has been forced to stall to "
157 "communicate backwards")
158 .prereq(commitNonSpecStalls);
159 branchMispredicts
160 .name(name() + ".branchMispredicts")
161 .desc("The number of times a branch was mispredicted")
162 .prereq(branchMispredicts);
163 numCommittedDist
164 .init(0,commitWidth,1)
165 .name(name() + ".COM:committed_per_cycle")
166 .desc("Number of insts commited each cycle")
167 .flags(Stats::pdf)
168 ;
169
170 statComInst
171 .init(cpu->number_of_threads)
172 .name(name() + ".COM:count")
173 .desc("Number of instructions committed")
174 .flags(total)
175 ;
176
177 statComSwp
178 .init(cpu->number_of_threads)
179 .name(name() + ".COM:swp_count")
180 .desc("Number of s/w prefetches committed")
181 .flags(total)
182 ;
183
184 statComRefs
185 .init(cpu->number_of_threads)
186 .name(name() + ".COM:refs")
187 .desc("Number of memory references committed")
188 .flags(total)
189 ;
190
191 statComLoads
192 .init(cpu->number_of_threads)
193 .name(name() + ".COM:loads")
194 .desc("Number of loads committed")
195 .flags(total)
196 ;
197
198 statComMembars
199 .init(cpu->number_of_threads)
200 .name(name() + ".COM:membars")
201 .desc("Number of memory barriers committed")
202 .flags(total)
203 ;
204
205 statComBranches
206 .init(cpu->number_of_threads)
207 .name(name() + ".COM:branches")
208 .desc("Number of branches committed")
209 .flags(total)
210 ;
211
212 commitEligible
213 .init(cpu->number_of_threads)
214 .name(name() + ".COM:bw_limited")
215 .desc("number of insts not committed due to BW limits")
216 .flags(total)
217 ;
218
219 commitEligibleSamples
220 .name(name() + ".COM:bw_lim_events")
221 .desc("number cycles where commit BW limit reached")
222 ;
223}
224
225template <class Impl>
226void
227DefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr)
228{
229 DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
230 cpu = cpu_ptr;
231
232 // Commit must broadcast the number of free entries it has at the start of
233 // the simulation, so it starts as active.
234 cpu->activateStage(O3CPU::CommitIdx);
235
236 trapLatency = cpu->cycles(trapLatency);
237}
238
239template <class Impl>
240void
241DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
242{
243 thread = threads;
244}
245
246template <class Impl>
247void
248DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
249{
250 DPRINTF(Commit, "Commit: Setting time buffer pointer.\n");
251 timeBuffer = tb_ptr;
252
253 // Setup wire to send information back to IEW.
254 toIEW = timeBuffer->getWire(0);
255
256 // Setup wire to read data from IEW (for the ROB).
257 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
258}
259
260template <class Impl>
261void
262DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
263{
264 DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n");
265 fetchQueue = fq_ptr;
266
267 // Setup wire to get instructions from rename (for the ROB).
268 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
269}
270
271template <class Impl>
272void
273DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
274{
275 DPRINTF(Commit, "Commit: Setting rename queue pointer.\n");
276 renameQueue = rq_ptr;
277
278 // Setup wire to get instructions from rename (for the ROB).
279 fromRename = renameQueue->getWire(-renameToROBDelay);
280}
281
282template <class Impl>
283void
284DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
285{
286 DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n");
287 iewQueue = iq_ptr;
288
289 // Setup wire to get instructions from IEW.
290 fromIEW = iewQueue->getWire(-iewToCommitDelay);
291}
292
293template <class Impl>
294void
295DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
296{
297 iewStage = iew_stage;
298}
299
300template<class Impl>
301void
302DefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
303{
304 DPRINTF(Commit, "Commit: Setting active threads list pointer.\n");
305 activeThreads = at_ptr;
306}
307
308template <class Impl>
309void
310DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
311{
312 DPRINTF(Commit, "Setting rename map pointers.\n");
313
314 for (int i=0; i < numThreads; i++) {
315 renameMap[i] = &rm_ptr[i];
316 }
317}
318
319template <class Impl>
320void
321DefaultCommit<Impl>::setROB(ROB *rob_ptr)
322{
323 DPRINTF(Commit, "Commit: Setting ROB pointer.\n");
324 rob = rob_ptr;
325}
326
327template <class Impl>
328void
329DefaultCommit<Impl>::initStage()
330{
331 rob->setActiveThreads(activeThreads);
332 rob->resetEntries();
333
334 // Broadcast the number of free entries.
335 for (int i=0; i < numThreads; i++) {
336 toIEW->commitInfo[i].usedROB = true;
337 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
338 }
339
340 cpu->activityThisCycle();
341}
342
343template <class Impl>
344bool
345DefaultCommit<Impl>::drain()
346{
347 drainPending = true;
348
349 return false;
350}
351
352template <class Impl>
353void
354DefaultCommit<Impl>::switchOut()
355{
356 switchedOut = true;
357 drainPending = false;
358 rob->switchOut();
359}
360
361template <class Impl>
362void
363DefaultCommit<Impl>::resume()
364{
365 drainPending = false;
366}
367
368template <class Impl>
369void
370DefaultCommit<Impl>::takeOverFrom()
371{
372 switchedOut = false;
373 _status = Active;
374 _nextStatus = Inactive;
375 for (int i=0; i < numThreads; i++) {
376 commitStatus[i] = Idle;
377 changedROBNumEntries[i] = false;
378 trapSquash[i] = false;
379 tcSquash[i] = false;
380 }
381 squashCounter = 0;
382 rob->takeOverFrom();
383}
384
385template <class Impl>
386void
387DefaultCommit<Impl>::updateStatus()
388{
389 // reset ROB changed variable
|
390 std::list<unsigned>::iterator threads = (*activeThreads).begin();
391 while (threads != (*activeThreads).end()) {
| 390 std::list<unsigned>::iterator threads = activeThreads->begin();
391 std::list<unsigned>::iterator end = activeThreads->end();
392
393 while (threads != end) {
|
392 unsigned tid = *threads++;
| 394 unsigned tid = *threads++;
|
| 395
|
393 changedROBNumEntries[tid] = false;
394
395 // Also check if any of the threads has a trap pending
396 if (commitStatus[tid] == TrapPending ||
397 commitStatus[tid] == FetchTrapPending) {
398 _nextStatus = Active;
399 }
400 }
401
402 if (_nextStatus == Inactive && _status == Active) {
403 DPRINTF(Activity, "Deactivating stage.\n");
404 cpu->deactivateStage(O3CPU::CommitIdx);
405 } else if (_nextStatus == Active && _status == Inactive) {
406 DPRINTF(Activity, "Activating stage.\n");
407 cpu->activateStage(O3CPU::CommitIdx);
408 }
409
410 _status = _nextStatus;
411}
412
413template <class Impl>
414void
415DefaultCommit<Impl>::setNextStatus()
416{
417 int squashes = 0;
418
| 396 changedROBNumEntries[tid] = false;
397
398 // Also check if any of the threads has a trap pending
399 if (commitStatus[tid] == TrapPending ||
400 commitStatus[tid] == FetchTrapPending) {
401 _nextStatus = Active;
402 }
403 }
404
405 if (_nextStatus == Inactive && _status == Active) {
406 DPRINTF(Activity, "Deactivating stage.\n");
407 cpu->deactivateStage(O3CPU::CommitIdx);
408 } else if (_nextStatus == Active && _status == Inactive) {
409 DPRINTF(Activity, "Activating stage.\n");
410 cpu->activateStage(O3CPU::CommitIdx);
411 }
412
413 _status = _nextStatus;
414}
415
416template <class Impl>
417void
418DefaultCommit<Impl>::setNextStatus()
419{
420 int squashes = 0;
421
|
419 std::list<unsigned>::iterator threads = (*activeThreads).begin();
| 422 std::list<unsigned>::iterator threads = activeThreads->begin();
423 std::list<unsigned>::iterator end = activeThreads->end();
|
420
| 424
|
421 while (threads != (*activeThreads).end()) {
| 425 while (threads != end) {
|
422 unsigned tid = *threads++;
423
424 if (commitStatus[tid] == ROBSquashing) {
425 squashes++;
426 }
427 }
428
429 squashCounter = squashes;
430
431 // If commit is currently squashing, then it will have activity for the
432 // next cycle. Set its next status as active.
433 if (squashCounter) {
434 _nextStatus = Active;
435 }
436}
437
438template <class Impl>
439bool
440DefaultCommit<Impl>::changedROBEntries()
441{
| 426 unsigned tid = *threads++;
427
428 if (commitStatus[tid] == ROBSquashing) {
429 squashes++;
430 }
431 }
432
433 squashCounter = squashes;
434
435 // If commit is currently squashing, then it will have activity for the
436 // next cycle. Set its next status as active.
437 if (squashCounter) {
438 _nextStatus = Active;
439 }
440}
441
442template <class Impl>
443bool
444DefaultCommit<Impl>::changedROBEntries()
445{
|
442 std::list<unsigned>::iterator threads = (*activeThreads).begin();
| 446 std::list<unsigned>::iterator threads = activeThreads->begin();
447 std::list<unsigned>::iterator end = activeThreads->end();
|
443
| 448
|
444 while (threads != (*activeThreads).end()) {
| 449 while (threads != end) {
|
445 unsigned tid = *threads++;
446
447 if (changedROBNumEntries[tid]) {
448 return true;
449 }
450 }
451
452 return false;
453}
454
455template <class Impl>
456unsigned
457DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
458{
459 return rob->numFreeEntries(tid);
460}
461
462template <class Impl>
463void
464DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
465{
466 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
467
468 TrapEvent *trap = new TrapEvent(this, tid);
469
470 trap->schedule(curTick + trapLatency);
471
472 thread[tid]->trapPending = true;
473}
474
475template <class Impl>
476void
477DefaultCommit<Impl>::generateTCEvent(unsigned tid)
478{
479 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
480
481 tcSquash[tid] = true;
482}
483
484template <class Impl>
485void
486DefaultCommit<Impl>::squashAll(unsigned tid)
487{
488 // If we want to include the squashing instruction in the squash,
489 // then use one older sequence number.
490 // Hopefully this doesn't mess things up. Basically I want to squash
491 // all instructions of this thread.
492 InstSeqNum squashed_inst = rob->isEmpty() ?
493 0 : rob->readHeadInst(tid)->seqNum - 1;;
494
495 // All younger instructions will be squashed. Set the sequence
496 // number as the youngest instruction in the ROB (0 in this case.
497 // Hopefully nothing breaks.)
498 youngestSeqNum[tid] = 0;
499
500 rob->squash(squashed_inst, tid);
501 changedROBNumEntries[tid] = true;
502
503 // Send back the sequence number of the squashed instruction.
504 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
505
506 // Send back the squash signal to tell stages that they should
507 // squash.
508 toIEW->commitInfo[tid].squash = true;
509
510 // Send back the rob squashing signal so other stages know that
511 // the ROB is in the process of squashing.
512 toIEW->commitInfo[tid].robSquashing = true;
513
514 toIEW->commitInfo[tid].branchMispredict = false;
515
516 toIEW->commitInfo[tid].nextPC = PC[tid];
517 toIEW->commitInfo[tid].nextNPC = nextPC[tid];
518}
519
520template <class Impl>
521void
522DefaultCommit<Impl>::squashFromTrap(unsigned tid)
523{
524 squashAll(tid);
525
526 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
527
528 thread[tid]->trapPending = false;
529 thread[tid]->inSyscall = false;
530
531 trapSquash[tid] = false;
532
533 commitStatus[tid] = ROBSquashing;
534 cpu->activityThisCycle();
535}
536
537template <class Impl>
538void
539DefaultCommit<Impl>::squashFromTC(unsigned tid)
540{
541 squashAll(tid);
542
543 DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
544
545 thread[tid]->inSyscall = false;
546 assert(!thread[tid]->trapPending);
547
548 commitStatus[tid] = ROBSquashing;
549 cpu->activityThisCycle();
550
551 tcSquash[tid] = false;
552}
553
554template <class Impl>
555void
556DefaultCommit<Impl>::tick()
557{
558 wroteToTimeBuffer = false;
559 _nextStatus = Inactive;
560
561 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
562 cpu->signalDrained();
563 drainPending = false;
564 return;
565 }
566
| 450 unsigned tid = *threads++;
451
452 if (changedROBNumEntries[tid]) {
453 return true;
454 }
455 }
456
457 return false;
458}
459
460template <class Impl>
461unsigned
462DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
463{
464 return rob->numFreeEntries(tid);
465}
466
467template <class Impl>
468void
469DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
470{
471 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
472
473 TrapEvent *trap = new TrapEvent(this, tid);
474
475 trap->schedule(curTick + trapLatency);
476
477 thread[tid]->trapPending = true;
478}
479
480template <class Impl>
481void
482DefaultCommit<Impl>::generateTCEvent(unsigned tid)
483{
484 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
485
486 tcSquash[tid] = true;
487}
488
489template <class Impl>
490void
491DefaultCommit<Impl>::squashAll(unsigned tid)
492{
493 // If we want to include the squashing instruction in the squash,
494 // then use one older sequence number.
495 // Hopefully this doesn't mess things up. Basically I want to squash
496 // all instructions of this thread.
497 InstSeqNum squashed_inst = rob->isEmpty() ?
498 0 : rob->readHeadInst(tid)->seqNum - 1;;
499
500 // All younger instructions will be squashed. Set the sequence
501 // number as the youngest instruction in the ROB (0 in this case.
502 // Hopefully nothing breaks.)
503 youngestSeqNum[tid] = 0;
504
505 rob->squash(squashed_inst, tid);
506 changedROBNumEntries[tid] = true;
507
508 // Send back the sequence number of the squashed instruction.
509 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
510
511 // Send back the squash signal to tell stages that they should
512 // squash.
513 toIEW->commitInfo[tid].squash = true;
514
515 // Send back the rob squashing signal so other stages know that
516 // the ROB is in the process of squashing.
517 toIEW->commitInfo[tid].robSquashing = true;
518
519 toIEW->commitInfo[tid].branchMispredict = false;
520
521 toIEW->commitInfo[tid].nextPC = PC[tid];
522 toIEW->commitInfo[tid].nextNPC = nextPC[tid];
523}
524
525template <class Impl>
526void
527DefaultCommit<Impl>::squashFromTrap(unsigned tid)
528{
529 squashAll(tid);
530
531 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
532
533 thread[tid]->trapPending = false;
534 thread[tid]->inSyscall = false;
535
536 trapSquash[tid] = false;
537
538 commitStatus[tid] = ROBSquashing;
539 cpu->activityThisCycle();
540}
541
542template <class Impl>
543void
544DefaultCommit<Impl>::squashFromTC(unsigned tid)
545{
546 squashAll(tid);
547
548 DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
549
550 thread[tid]->inSyscall = false;
551 assert(!thread[tid]->trapPending);
552
553 commitStatus[tid] = ROBSquashing;
554 cpu->activityThisCycle();
555
556 tcSquash[tid] = false;
557}
558
559template <class Impl>
560void
561DefaultCommit<Impl>::tick()
562{
563 wroteToTimeBuffer = false;
564 _nextStatus = Inactive;
565
566 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
567 cpu->signalDrained();
568 drainPending = false;
569 return;
570 }
571
|
567 if ((*activeThreads).size() <= 0)
| 572 if (activeThreads->empty())
|
568 return;
569
| 573 return;
574
|
570 std::list<unsigned>::iterator threads = (*activeThreads).begin();
| 575 std::list<unsigned>::iterator threads = activeThreads->begin();
576 std::list<unsigned>::iterator end = activeThreads->end();
|
571
572 // Check if any of the threads are done squashing. Change the
573 // status if they are done.
| 577
578 // Check if any of the threads are done squashing. Change the
579 // status if they are done.
|
574 while (threads != (*activeThreads).end()) {
| 580 while (threads != end) {
|
575 unsigned tid = *threads++;
576
577 if (commitStatus[tid] == ROBSquashing) {
578
579 if (rob->isDoneSquashing(tid)) {
580 commitStatus[tid] = Running;
581 } else {
582 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
583 " insts this cycle.\n", tid);
584 rob->doSquash(tid);
585 toIEW->commitInfo[tid].robSquashing = true;
586 wroteToTimeBuffer = true;
587 }
588 }
589 }
590
591 commit();
592
593 markCompletedInsts();
594
| 581 unsigned tid = *threads++;
582
583 if (commitStatus[tid] == ROBSquashing) {
584
585 if (rob->isDoneSquashing(tid)) {
586 commitStatus[tid] = Running;
587 } else {
588 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
589 " insts this cycle.\n", tid);
590 rob->doSquash(tid);
591 toIEW->commitInfo[tid].robSquashing = true;
592 wroteToTimeBuffer = true;
593 }
594 }
595 }
596
597 commit();
598
599 markCompletedInsts();
600
|
595 threads = (*activeThreads).begin();
| 601 threads = activeThreads->begin();
|
596
| 602
|
597 while (threads != (*activeThreads).end()) {
| 603 while (threads != end) {
|
598 unsigned tid = *threads++;
599
600 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
601 // The ROB has more instructions it can commit. Its next status
602 // will be active.
603 _nextStatus = Active;
604
605 DynInstPtr inst = rob->readHeadInst(tid);
606
607 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
608 " ROB and ready to commit\n",
609 tid, inst->seqNum, inst->readPC());
610
611 } else if (!rob->isEmpty(tid)) {
612 DynInstPtr inst = rob->readHeadInst(tid);
613
614 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
615 "%#x is head of ROB and not ready\n",
616 tid, inst->seqNum, inst->readPC());
617 }
618
619 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
620 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
621 }
622
623
624 if (wroteToTimeBuffer) {
625 DPRINTF(Activity, "Activity This Cycle.\n");
626 cpu->activityThisCycle();
627 }
628
629 updateStatus();
630}
631
632template <class Impl>
633void
634DefaultCommit<Impl>::commit()
635{
636
637 //////////////////////////////////////
638 // Check for interrupts
639 //////////////////////////////////////
640
641#if FULL_SYSTEM
642 if (interrupt != NoFault) {
643 // Wait until the ROB is empty and all stores have drained in
644 // order to enter the interrupt.
645 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
646 // Squash or record that I need to squash this cycle if
647 // an interrupt needed to be handled.
648 DPRINTF(Commit, "Interrupt detected.\n");
649
650 assert(!thread[0]->inSyscall);
651 thread[0]->inSyscall = true;
652
653 // CPU will handle interrupt.
654 cpu->processInterrupts(interrupt);
655
656 thread[0]->inSyscall = false;
657
658 commitStatus[0] = TrapPending;
659
660 // Generate trap squash event.
661 generateTrapEvent(0);
662
663 // Clear the interrupt now that it's been handled
664 toIEW->commitInfo[0].clearInterrupt = true;
665 interrupt = NoFault;
666 } else {
667 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
668 }
669 } else if (cpu->checkInterrupts &&
670 cpu->check_interrupts(cpu->tcBase(0)) &&
671 commitStatus[0] != TrapPending &&
672 !trapSquash[0] &&
673 !tcSquash[0]) {
674 // Process interrupts if interrupts are enabled, not in PAL
675 // mode, and no other traps or external squashes are currently
676 // pending.
677 // @todo: Allow other threads to handle interrupts.
678
679 // Get any interrupt that happened
680 interrupt = cpu->getInterrupts();
681
682 if (interrupt != NoFault) {
683 // Tell fetch that there is an interrupt pending. This
684 // will make fetch wait until it sees a non PAL-mode PC,
685 // at which point it stops fetching instructions.
686 toIEW->commitInfo[0].interruptPending = true;
687 }
688 }
689
690#endif // FULL_SYSTEM
691
692 ////////////////////////////////////
693 // Check for any possible squashes, handle them first
694 ////////////////////////////////////
| 604 unsigned tid = *threads++;
605
606 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
607 // The ROB has more instructions it can commit. Its next status
608 // will be active.
609 _nextStatus = Active;
610
611 DynInstPtr inst = rob->readHeadInst(tid);
612
613 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
614 " ROB and ready to commit\n",
615 tid, inst->seqNum, inst->readPC());
616
617 } else if (!rob->isEmpty(tid)) {
618 DynInstPtr inst = rob->readHeadInst(tid);
619
620 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
621 "%#x is head of ROB and not ready\n",
622 tid, inst->seqNum, inst->readPC());
623 }
624
625 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
626 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
627 }
628
629
630 if (wroteToTimeBuffer) {
631 DPRINTF(Activity, "Activity This Cycle.\n");
632 cpu->activityThisCycle();
633 }
634
635 updateStatus();
636}
637
638template <class Impl>
639void
640DefaultCommit<Impl>::commit()
641{
642
643 //////////////////////////////////////
644 // Check for interrupts
645 //////////////////////////////////////
646
647#if FULL_SYSTEM
648 if (interrupt != NoFault) {
649 // Wait until the ROB is empty and all stores have drained in
650 // order to enter the interrupt.
651 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
652 // Squash or record that I need to squash this cycle if
653 // an interrupt needed to be handled.
654 DPRINTF(Commit, "Interrupt detected.\n");
655
656 assert(!thread[0]->inSyscall);
657 thread[0]->inSyscall = true;
658
659 // CPU will handle interrupt.
660 cpu->processInterrupts(interrupt);
661
662 thread[0]->inSyscall = false;
663
664 commitStatus[0] = TrapPending;
665
666 // Generate trap squash event.
667 generateTrapEvent(0);
668
669 // Clear the interrupt now that it's been handled
670 toIEW->commitInfo[0].clearInterrupt = true;
671 interrupt = NoFault;
672 } else {
673 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
674 }
675 } else if (cpu->checkInterrupts &&
676 cpu->check_interrupts(cpu->tcBase(0)) &&
677 commitStatus[0] != TrapPending &&
678 !trapSquash[0] &&
679 !tcSquash[0]) {
680 // Process interrupts if interrupts are enabled, not in PAL
681 // mode, and no other traps or external squashes are currently
682 // pending.
683 // @todo: Allow other threads to handle interrupts.
684
685 // Get any interrupt that happened
686 interrupt = cpu->getInterrupts();
687
688 if (interrupt != NoFault) {
689 // Tell fetch that there is an interrupt pending. This
690 // will make fetch wait until it sees a non PAL-mode PC,
691 // at which point it stops fetching instructions.
692 toIEW->commitInfo[0].interruptPending = true;
693 }
694 }
695
696#endif // FULL_SYSTEM
697
698 ////////////////////////////////////
699 // Check for any possible squashes, handle them first
700 ////////////////////////////////////
|
695 std::list<unsigned>::iterator threads = (*activeThreads).begin();
| 701 std::list<unsigned>::iterator threads = activeThreads->begin();
702 std::list<unsigned>::iterator end = activeThreads->end();
|
696
| 703
|
697 while (threads != (*activeThreads).end()) {
| 704 while (threads != end) {
|
698 unsigned tid = *threads++;
699
700 // Not sure which one takes priority. I think if we have
701 // both, that's a bad sign.
702 if (trapSquash[tid] == true) {
703 assert(!tcSquash[tid]);
704 squashFromTrap(tid);
705 } else if (tcSquash[tid] == true) {
706 squashFromTC(tid);
707 }
708
709 // Squashed sequence number must be older than youngest valid
710 // instruction in the ROB. This prevents squashes from younger
711 // instructions overriding squashes from older instructions.
712 if (fromIEW->squash[tid] &&
713 commitStatus[tid] != TrapPending &&
714 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
715
716 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
717 tid,
718 fromIEW->mispredPC[tid],
719 fromIEW->squashedSeqNum[tid]);
720
721 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
722 tid,
723 fromIEW->nextPC[tid]);
724
725 commitStatus[tid] = ROBSquashing;
726
727 // If we want to include the squashing instruction in the squash,
728 // then use one older sequence number.
729 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
730
731#if ISA_HAS_DELAY_SLOT
732 InstSeqNum bdelay_done_seq_num = squashed_inst;
733 bool squash_bdelay_slot = fromIEW->squashDelaySlot[tid];
734 bool branchMispredict = fromIEW->branchMispredict[tid];
735
736 // Squashing/not squashing the branch delay slot only makes
737 // sense when you're squashing from a branch, ie from a branch
738 // mispredict.
739 if (branchMispredict && !squash_bdelay_slot) {
740 bdelay_done_seq_num++;
741 }
742#endif
743
744 if (fromIEW->includeSquashInst[tid] == true) {
745 squashed_inst--;
746#if ISA_HAS_DELAY_SLOT
747 bdelay_done_seq_num--;
748#endif
749 }
750 // All younger instructions will be squashed. Set the sequence
751 // number as the youngest instruction in the ROB.
752 youngestSeqNum[tid] = squashed_inst;
753
754#if ISA_HAS_DELAY_SLOT
755 rob->squash(bdelay_done_seq_num, tid);
756 toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot;
757 toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num;
758#else
759 rob->squash(squashed_inst, tid);
760 toIEW->commitInfo[tid].squashDelaySlot = true;
761#endif
762 changedROBNumEntries[tid] = true;
763
764 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
765
766 toIEW->commitInfo[tid].squash = true;
767
768 // Send back the rob squashing signal so other stages know that
769 // the ROB is in the process of squashing.
770 toIEW->commitInfo[tid].robSquashing = true;
771
772 toIEW->commitInfo[tid].branchMispredict =
773 fromIEW->branchMispredict[tid];
774
775 toIEW->commitInfo[tid].branchTaken =
776 fromIEW->branchTaken[tid];
777
778 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
779 toIEW->commitInfo[tid].nextNPC = fromIEW->nextNPC[tid];
780
781 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
782
783 if (toIEW->commitInfo[tid].branchMispredict) {
784 ++branchMispredicts;
785 }
786 }
787
788 }
789
790 setNextStatus();
791
792 if (squashCounter != numThreads) {
793 // If we're not currently squashing, then get instructions.
794 getInsts();
795
796 // Try to commit any instructions.
797 commitInsts();
798 } else {
799#if ISA_HAS_DELAY_SLOT
800 skidInsert();
801#endif
802 }
803
804 //Check for any activity
| 705 unsigned tid = *threads++;
706
707 // Not sure which one takes priority. I think if we have
708 // both, that's a bad sign.
709 if (trapSquash[tid] == true) {
710 assert(!tcSquash[tid]);
711 squashFromTrap(tid);
712 } else if (tcSquash[tid] == true) {
713 squashFromTC(tid);
714 }
715
716 // Squashed sequence number must be older than youngest valid
717 // instruction in the ROB. This prevents squashes from younger
718 // instructions overriding squashes from older instructions.
719 if (fromIEW->squash[tid] &&
720 commitStatus[tid] != TrapPending &&
721 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
722
723 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
724 tid,
725 fromIEW->mispredPC[tid],
726 fromIEW->squashedSeqNum[tid]);
727
728 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
729 tid,
730 fromIEW->nextPC[tid]);
731
732 commitStatus[tid] = ROBSquashing;
733
734 // If we want to include the squashing instruction in the squash,
735 // then use one older sequence number.
736 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
737
738#if ISA_HAS_DELAY_SLOT
739 InstSeqNum bdelay_done_seq_num = squashed_inst;
740 bool squash_bdelay_slot = fromIEW->squashDelaySlot[tid];
741 bool branchMispredict = fromIEW->branchMispredict[tid];
742
743 // Squashing/not squashing the branch delay slot only makes
744 // sense when you're squashing from a branch, ie from a branch
745 // mispredict.
746 if (branchMispredict && !squash_bdelay_slot) {
747 bdelay_done_seq_num++;
748 }
749#endif
750
751 if (fromIEW->includeSquashInst[tid] == true) {
752 squashed_inst--;
753#if ISA_HAS_DELAY_SLOT
754 bdelay_done_seq_num--;
755#endif
756 }
757 // All younger instructions will be squashed. Set the sequence
758 // number as the youngest instruction in the ROB.
759 youngestSeqNum[tid] = squashed_inst;
760
761#if ISA_HAS_DELAY_SLOT
762 rob->squash(bdelay_done_seq_num, tid);
763 toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot;
764 toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num;
765#else
766 rob->squash(squashed_inst, tid);
767 toIEW->commitInfo[tid].squashDelaySlot = true;
768#endif
769 changedROBNumEntries[tid] = true;
770
771 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
772
773 toIEW->commitInfo[tid].squash = true;
774
775 // Send back the rob squashing signal so other stages know that
776 // the ROB is in the process of squashing.
777 toIEW->commitInfo[tid].robSquashing = true;
778
779 toIEW->commitInfo[tid].branchMispredict =
780 fromIEW->branchMispredict[tid];
781
782 toIEW->commitInfo[tid].branchTaken =
783 fromIEW->branchTaken[tid];
784
785 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
786 toIEW->commitInfo[tid].nextNPC = fromIEW->nextNPC[tid];
787
788 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
789
790 if (toIEW->commitInfo[tid].branchMispredict) {
791 ++branchMispredicts;
792 }
793 }
794
795 }
796
797 setNextStatus();
798
799 if (squashCounter != numThreads) {
800 // If we're not currently squashing, then get instructions.
801 getInsts();
802
803 // Try to commit any instructions.
804 commitInsts();
805 } else {
806#if ISA_HAS_DELAY_SLOT
807 skidInsert();
808#endif
809 }
810
811 //Check for any activity
|
805 threads = (*activeThreads).begin();
| 812 threads = activeThreads->begin();
|
806
| 813
|
807 while (threads != (*activeThreads).end()) {
| 814 while (threads != end) {
|
808 unsigned tid = *threads++;
809
810 if (changedROBNumEntries[tid]) {
811 toIEW->commitInfo[tid].usedROB = true;
812 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
813
814 if (rob->isEmpty(tid)) {
815 toIEW->commitInfo[tid].emptyROB = true;
816 }
817
818 wroteToTimeBuffer = true;
819 changedROBNumEntries[tid] = false;
820 }
821 }
822}
823
824template <class Impl>
825void
826DefaultCommit<Impl>::commitInsts()
827{
828 ////////////////////////////////////
829 // Handle commit
830 // Note that commit will be handled prior to putting new
831 // instructions in the ROB so that the ROB only tries to commit
832 // instructions it has in this current cycle, and not instructions
833 // it is writing in during this cycle. Can't commit and squash
834 // things at the same time...
835 ////////////////////////////////////
836
837 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
838
839 unsigned num_committed = 0;
840
841 DynInstPtr head_inst;
842
843 // Commit as many instructions as possible until the commit bandwidth
844 // limit is reached, or it becomes impossible to commit any more.
845 while (num_committed < commitWidth) {
846 int commit_thread = getCommittingThread();
847
848 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
849 break;
850
851 head_inst = rob->readHeadInst(commit_thread);
852
853 int tid = head_inst->threadNumber;
854
855 assert(tid == commit_thread);
856
857 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
858 head_inst->seqNum, tid);
859
860 // If the head instruction is squashed, it is ready to retire
861 // (be removed from the ROB) at any time.
862 if (head_inst->isSquashed()) {
863
864 DPRINTF(Commit, "Retiring squashed instruction from "
865 "ROB.\n");
866
867 rob->retireHead(commit_thread);
868
869 ++commitSquashedInsts;
870
871 // Record that the number of ROB entries has changed.
872 changedROBNumEntries[tid] = true;
873 } else {
874 PC[tid] = head_inst->readPC();
875 nextPC[tid] = head_inst->readNextPC();
876 nextNPC[tid] = head_inst->readNextNPC();
877
878 // Increment the total number of non-speculative instructions
879 // executed.
880 // Hack for now: it really shouldn't happen until after the
881 // commit is deemed to be successful, but this count is needed
882 // for syscalls.
883 thread[tid]->funcExeInst++;
884
885 // Try to commit the head instruction.
886 bool commit_success = commitHead(head_inst, num_committed);
887
888 if (commit_success) {
889 ++num_committed;
890
891 changedROBNumEntries[tid] = true;
892
893 // Set the doneSeqNum to the youngest committed instruction.
894 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
895
896 ++commitCommittedInsts;
897
898 // To match the old model, don't count nops and instruction
899 // prefetches towards the total commit count.
900 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
901 cpu->instDone(tid);
902 }
903
904 PC[tid] = nextPC[tid];
905#if ISA_HAS_DELAY_SLOT
906 nextPC[tid] = nextNPC[tid];
907 nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
908#else
909 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
910#endif
911
912#if FULL_SYSTEM
913 int count = 0;
914 Addr oldpc;
915 do {
916 // Debug statement. Checks to make sure we're not
917 // currently updating state while handling PC events.
918 if (count == 0)
919 assert(!thread[tid]->inSyscall &&
920 !thread[tid]->trapPending);
921 oldpc = PC[tid];
922 cpu->system->pcEventQueue.service(
923 thread[tid]->getTC());
924 count++;
925 } while (oldpc != PC[tid]);
926 if (count > 1) {
927 DPRINTF(Commit, "PC skip function event, stopping commit\n");
928 break;
929 }
930#endif
931 } else {
932 DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
933 "[tid:%i] [sn:%i].\n",
934 head_inst->readPC(), tid ,head_inst->seqNum);
935 break;
936 }
937 }
938 }
939
940 DPRINTF(CommitRate, "%i\n", num_committed);
941 numCommittedDist.sample(num_committed);
942
943 if (num_committed == commitWidth) {
944 commitEligibleSamples++;
945 }
946}
947
948template <class Impl>
949bool
950DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
951{
952 assert(head_inst);
953
954 int tid = head_inst->threadNumber;
955
956 // If the instruction is not executed yet, then it will need extra
957 // handling. Signal backwards that it should be executed.
958 if (!head_inst->isExecuted()) {
959 // Keep this number correct. We have not yet actually executed
960 // and committed this instruction.
961 thread[tid]->funcExeInst--;
962
963 head_inst->setAtCommit();
964
965 if (head_inst->isNonSpeculative() ||
966 head_inst->isStoreConditional() ||
967 head_inst->isMemBarrier() ||
968 head_inst->isWriteBarrier()) {
969
970 DPRINTF(Commit, "Encountered a barrier or non-speculative "
971 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
972 head_inst->seqNum, head_inst->readPC());
973
| 815 unsigned tid = *threads++;
816
817 if (changedROBNumEntries[tid]) {
818 toIEW->commitInfo[tid].usedROB = true;
819 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
820
821 if (rob->isEmpty(tid)) {
822 toIEW->commitInfo[tid].emptyROB = true;
823 }
824
825 wroteToTimeBuffer = true;
826 changedROBNumEntries[tid] = false;
827 }
828 }
829}
830
831template <class Impl>
832void
833DefaultCommit<Impl>::commitInsts()
834{
835 ////////////////////////////////////
836 // Handle commit
837 // Note that commit will be handled prior to putting new
838 // instructions in the ROB so that the ROB only tries to commit
839 // instructions it has in this current cycle, and not instructions
840 // it is writing in during this cycle. Can't commit and squash
841 // things at the same time...
842 ////////////////////////////////////
843
844 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
845
846 unsigned num_committed = 0;
847
848 DynInstPtr head_inst;
849
850 // Commit as many instructions as possible until the commit bandwidth
851 // limit is reached, or it becomes impossible to commit any more.
852 while (num_committed < commitWidth) {
853 int commit_thread = getCommittingThread();
854
855 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
856 break;
857
858 head_inst = rob->readHeadInst(commit_thread);
859
860 int tid = head_inst->threadNumber;
861
862 assert(tid == commit_thread);
863
864 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
865 head_inst->seqNum, tid);
866
867 // If the head instruction is squashed, it is ready to retire
868 // (be removed from the ROB) at any time.
869 if (head_inst->isSquashed()) {
870
871 DPRINTF(Commit, "Retiring squashed instruction from "
872 "ROB.\n");
873
874 rob->retireHead(commit_thread);
875
876 ++commitSquashedInsts;
877
878 // Record that the number of ROB entries has changed.
879 changedROBNumEntries[tid] = true;
880 } else {
881 PC[tid] = head_inst->readPC();
882 nextPC[tid] = head_inst->readNextPC();
883 nextNPC[tid] = head_inst->readNextNPC();
884
885 // Increment the total number of non-speculative instructions
886 // executed.
887 // Hack for now: it really shouldn't happen until after the
888 // commit is deemed to be successful, but this count is needed
889 // for syscalls.
890 thread[tid]->funcExeInst++;
891
892 // Try to commit the head instruction.
893 bool commit_success = commitHead(head_inst, num_committed);
894
895 if (commit_success) {
896 ++num_committed;
897
898 changedROBNumEntries[tid] = true;
899
900 // Set the doneSeqNum to the youngest committed instruction.
901 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
902
903 ++commitCommittedInsts;
904
905 // To match the old model, don't count nops and instruction
906 // prefetches towards the total commit count.
907 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
908 cpu->instDone(tid);
909 }
910
911 PC[tid] = nextPC[tid];
912#if ISA_HAS_DELAY_SLOT
913 nextPC[tid] = nextNPC[tid];
914 nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
915#else
916 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
917#endif
918
919#if FULL_SYSTEM
920 int count = 0;
921 Addr oldpc;
922 do {
923 // Debug statement. Checks to make sure we're not
924 // currently updating state while handling PC events.
925 if (count == 0)
926 assert(!thread[tid]->inSyscall &&
927 !thread[tid]->trapPending);
928 oldpc = PC[tid];
929 cpu->system->pcEventQueue.service(
930 thread[tid]->getTC());
931 count++;
932 } while (oldpc != PC[tid]);
933 if (count > 1) {
934 DPRINTF(Commit, "PC skip function event, stopping commit\n");
935 break;
936 }
937#endif
938 } else {
939 DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
940 "[tid:%i] [sn:%i].\n",
941 head_inst->readPC(), tid ,head_inst->seqNum);
942 break;
943 }
944 }
945 }
946
947 DPRINTF(CommitRate, "%i\n", num_committed);
948 numCommittedDist.sample(num_committed);
949
950 if (num_committed == commitWidth) {
951 commitEligibleSamples++;
952 }
953}
954
955template <class Impl>
956bool
957DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
958{
959 assert(head_inst);
960
961 int tid = head_inst->threadNumber;
962
963 // If the instruction is not executed yet, then it will need extra
964 // handling. Signal backwards that it should be executed.
965 if (!head_inst->isExecuted()) {
966 // Keep this number correct. We have not yet actually executed
967 // and committed this instruction.
968 thread[tid]->funcExeInst--;
969
970 head_inst->setAtCommit();
971
972 if (head_inst->isNonSpeculative() ||
973 head_inst->isStoreConditional() ||
974 head_inst->isMemBarrier() ||
975 head_inst->isWriteBarrier()) {
976
977 DPRINTF(Commit, "Encountered a barrier or non-speculative "
978 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
979 head_inst->seqNum, head_inst->readPC());
980
|
974#if !FULL_SYSTEM
| |
975 // Hack to make sure syscalls/memory barriers/quiesces
976 // aren't executed until all stores write back their data.
977 // This direct communication shouldn't be used for
978 // anything other than this.
| 981 // Hack to make sure syscalls/memory barriers/quiesces
982 // aren't executed until all stores write back their data.
983 // This direct communication shouldn't be used for
984 // anything other than this.
|
979 if (inst_num > 0 || iewStage->hasStoresToWB())
980#else
| |
981 if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
982 head_inst->isQuiesce()) &&
983 iewStage->hasStoresToWB())
| 985 if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
986 head_inst->isQuiesce()) &&
987 iewStage->hasStoresToWB())
|
984#endif
| |
985 {
986 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
987 return false;
| 988 {
989 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
990 return false;
|
| 991 } else if (inst_num > 0 || iewStage->hasStoresToWB()) {
992 DPRINTF(Commit, "Waiting to become head of commit.\n");
993 return false;
|
988 }
989
990 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
991
992 // Change the instruction so it won't try to commit again until
993 // it is executed.
994 head_inst->clearCanCommit();
995
996 ++commitNonSpecStalls;
997
998 return false;
999 } else if (head_inst->isLoad()) {
1000 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
1001 head_inst->seqNum, head_inst->readPC());
1002
1003 // Send back the non-speculative instruction's sequence
1004 // number. Tell the lsq to re-execute the load.
1005 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1006 toIEW->commitInfo[tid].uncached = true;
1007 toIEW->commitInfo[tid].uncachedLoad = head_inst;
1008
1009 head_inst->clearCanCommit();
1010
1011 return false;
1012 } else {
1013 panic("Trying to commit un-executed instruction "
1014 "of unknown type!\n");
1015 }
1016 }
1017
1018 if (head_inst->isThreadSync()) {
1019 // Not handled for now.
1020 panic("Thread sync instructions are not handled yet.\n");
1021 }
1022
1023 // Stores mark themselves as completed.
1024 if (!head_inst->isStore()) {
1025 head_inst->setCompleted();
1026 }
1027
1028#if USE_CHECKER
1029 // Use checker prior to updating anything due to traps or PC
1030 // based events.
1031 if (cpu->checker) {
1032 cpu->checker->verify(head_inst);
1033 }
1034#endif
1035
1036 // Check if the instruction caused a fault. If so, trap.
1037 Fault inst_fault = head_inst->getFault();
1038
1039 // DTB will sometimes need the machine instruction for when
1040 // faults happen. So we will set it here, prior to the DTB
1041 // possibly needing it for its fault.
1042 thread[tid]->setInst(
1043 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1044
1045 if (inst_fault != NoFault) {
1046 head_inst->setCompleted();
1047 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1048 head_inst->seqNum, head_inst->readPC());
1049
1050 if (iewStage->hasStoresToWB() || inst_num > 0) {
1051 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1052 return false;
1053 }
1054
1055#if USE_CHECKER
1056 if (cpu->checker && head_inst->isStore()) {
1057 cpu->checker->verify(head_inst);
1058 }
1059#endif
1060
1061 assert(!thread[tid]->inSyscall);
1062
1063 // Mark that we're in state update mode so that the trap's
1064 // execution doesn't generate extra squashes.
1065 thread[tid]->inSyscall = true;
1066
1067 // Execute the trap. Although it's slightly unrealistic in
1068 // terms of timing (as it doesn't wait for the full timing of
1069 // the trap event to complete before updating state), it's
1070 // needed to update the state as soon as possible. This
1071 // prevents external agents from changing any specific state
1072 // that the trap need.
1073 cpu->trap(inst_fault, tid);
1074
1075 // Exit state update mode to avoid accidental updating.
1076 thread[tid]->inSyscall = false;
1077
1078 commitStatus[tid] = TrapPending;
1079
1080 // Generate trap squash event.
1081 generateTrapEvent(tid);
1082// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC());
1083 return false;
1084 }
1085
1086 updateComInstStats(head_inst);
1087
1088#if FULL_SYSTEM
1089 if (thread[tid]->profile) {
1090// bool usermode = TheISA::inUserMode(thread[tid]->getTC());
1091// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC();
1092 thread[tid]->profilePC = head_inst->readPC();
1093 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1094 head_inst->staticInst);
1095
1096 if (node)
1097 thread[tid]->profileNode = node;
1098 }
1099#endif
1100
1101 if (head_inst->traceData) {
1102 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1103 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1104 head_inst->traceData->finalize();
1105 head_inst->traceData = NULL;
1106 }
1107
1108 // Update the commit rename map
1109 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1110 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1111 head_inst->renamedDestRegIdx(i));
1112 }
1113
1114 if (head_inst->isCopy())
1115 panic("Should not commit any copy instructions!");
1116
1117 // Finally clear the head ROB entry.
1118 rob->retireHead(tid);
1119
1120 // Return true to indicate that we have committed an instruction.
1121 return true;
1122}
1123
1124template <class Impl>
1125void
1126DefaultCommit<Impl>::getInsts()
1127{
1128 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1129
1130#if ISA_HAS_DELAY_SLOT
1131 // Read any renamed instructions and place them into the ROB.
1132 int insts_to_process = std::min((int)renameWidth,
1133 (int)(fromRename->size + skidBuffer.size()));
1134 int rename_idx = 0;
1135
1136 DPRINTF(Commit, "%i insts available to process. Rename Insts:%i "
1137 "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size,
1138 skidBuffer.size());
1139#else
1140 // Read any renamed instructions and place them into the ROB.
1141 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1142#endif
1143
1144
1145 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1146 DynInstPtr inst;
1147
1148#if ISA_HAS_DELAY_SLOT
1149 // Get insts from skidBuffer or from Rename
1150 if (skidBuffer.size() > 0) {
1151 DPRINTF(Commit, "Grabbing skidbuffer inst.\n");
1152 inst = skidBuffer.front();
1153 skidBuffer.pop();
1154 } else {
1155 DPRINTF(Commit, "Grabbing rename inst.\n");
1156 inst = fromRename->insts[rename_idx++];
1157 }
1158#else
1159 inst = fromRename->insts[inst_num];
1160#endif
1161 int tid = inst->threadNumber;
1162
1163 if (!inst->isSquashed() &&
1164 commitStatus[tid] != ROBSquashing) {
1165 changedROBNumEntries[tid] = true;
1166
1167 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1168 inst->readPC(), inst->seqNum, tid);
1169
1170 rob->insertInst(inst);
1171
1172 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1173
1174 youngestSeqNum[tid] = inst->seqNum;
1175 } else {
1176 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1177 "squashed, skipping.\n",
1178 inst->readPC(), inst->seqNum, tid);
1179 }
1180 }
1181
1182#if ISA_HAS_DELAY_SLOT
1183 if (rename_idx < fromRename->size) {
1184 DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n");
1185
1186 for (;
1187 rename_idx < fromRename->size;
1188 rename_idx++) {
1189 DynInstPtr inst = fromRename->insts[rename_idx];
1190
1191 if (!inst->isSquashed()) {
1192 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1193 "skidBuffer.\n", inst->readPC(), inst->seqNum,
1194 inst->threadNumber);
1195 skidBuffer.push(inst);
1196 } else {
1197 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1198 "squashed, skipping.\n",
1199 inst->readPC(), inst->seqNum, inst->threadNumber);
1200 }
1201 }
1202 }
1203#endif
1204
1205}
1206
1207template <class Impl>
1208void
1209DefaultCommit<Impl>::skidInsert()
1210{
1211 DPRINTF(Commit, "Attempting to any instructions from rename into "
1212 "skidBuffer.\n");
1213
1214 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1215 DynInstPtr inst = fromRename->insts[inst_num];
1216
1217 if (!inst->isSquashed()) {
1218 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1219 "skidBuffer.\n", inst->readPC(), inst->seqNum,
1220 inst->threadNumber);
1221 skidBuffer.push(inst);
1222 } else {
1223 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1224 "squashed, skipping.\n",
1225 inst->readPC(), inst->seqNum, inst->threadNumber);
1226 }
1227 }
1228}
1229
1230template <class Impl>
1231void
1232DefaultCommit<Impl>::markCompletedInsts()
1233{
1234 // Grab completed insts out of the IEW instruction queue, and mark
1235 // instructions completed within the ROB.
1236 for (int inst_num = 0;
1237 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1238 ++inst_num)
1239 {
1240 if (!fromIEW->insts[inst_num]->isSquashed()) {
1241 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1242 "within ROB.\n",
1243 fromIEW->insts[inst_num]->threadNumber,
1244 fromIEW->insts[inst_num]->readPC(),
1245 fromIEW->insts[inst_num]->seqNum);
1246
1247 // Mark the instruction as ready to commit.
1248 fromIEW->insts[inst_num]->setCanCommit();
1249 }
1250 }
1251}
1252
1253template <class Impl>
1254bool
1255DefaultCommit<Impl>::robDoneSquashing()
1256{
| 994 }
995
996 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
997
998 // Change the instruction so it won't try to commit again until
999 // it is executed.
1000 head_inst->clearCanCommit();
1001
1002 ++commitNonSpecStalls;
1003
1004 return false;
1005 } else if (head_inst->isLoad()) {
1006 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
1007 head_inst->seqNum, head_inst->readPC());
1008
1009 // Send back the non-speculative instruction's sequence
1010 // number. Tell the lsq to re-execute the load.
1011 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1012 toIEW->commitInfo[tid].uncached = true;
1013 toIEW->commitInfo[tid].uncachedLoad = head_inst;
1014
1015 head_inst->clearCanCommit();
1016
1017 return false;
1018 } else {
1019 panic("Trying to commit un-executed instruction "
1020 "of unknown type!\n");
1021 }
1022 }
1023
1024 if (head_inst->isThreadSync()) {
1025 // Not handled for now.
1026 panic("Thread sync instructions are not handled yet.\n");
1027 }
1028
1029 // Stores mark themselves as completed.
1030 if (!head_inst->isStore()) {
1031 head_inst->setCompleted();
1032 }
1033
1034#if USE_CHECKER
1035 // Use checker prior to updating anything due to traps or PC
1036 // based events.
1037 if (cpu->checker) {
1038 cpu->checker->verify(head_inst);
1039 }
1040#endif
1041
1042 // Check if the instruction caused a fault. If so, trap.
1043 Fault inst_fault = head_inst->getFault();
1044
1045 // DTB will sometimes need the machine instruction for when
1046 // faults happen. So we will set it here, prior to the DTB
1047 // possibly needing it for its fault.
1048 thread[tid]->setInst(
1049 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1050
1051 if (inst_fault != NoFault) {
1052 head_inst->setCompleted();
1053 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1054 head_inst->seqNum, head_inst->readPC());
1055
1056 if (iewStage->hasStoresToWB() || inst_num > 0) {
1057 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1058 return false;
1059 }
1060
1061#if USE_CHECKER
1062 if (cpu->checker && head_inst->isStore()) {
1063 cpu->checker->verify(head_inst);
1064 }
1065#endif
1066
1067 assert(!thread[tid]->inSyscall);
1068
1069 // Mark that we're in state update mode so that the trap's
1070 // execution doesn't generate extra squashes.
1071 thread[tid]->inSyscall = true;
1072
1073 // Execute the trap. Although it's slightly unrealistic in
1074 // terms of timing (as it doesn't wait for the full timing of
1075 // the trap event to complete before updating state), it's
1076 // needed to update the state as soon as possible. This
1077 // prevents external agents from changing any specific state
1078 // that the trap need.
1079 cpu->trap(inst_fault, tid);
1080
1081 // Exit state update mode to avoid accidental updating.
1082 thread[tid]->inSyscall = false;
1083
1084 commitStatus[tid] = TrapPending;
1085
1086 // Generate trap squash event.
1087 generateTrapEvent(tid);
1088// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC());
1089 return false;
1090 }
1091
1092 updateComInstStats(head_inst);
1093
1094#if FULL_SYSTEM
1095 if (thread[tid]->profile) {
1096// bool usermode = TheISA::inUserMode(thread[tid]->getTC());
1097// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC();
1098 thread[tid]->profilePC = head_inst->readPC();
1099 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1100 head_inst->staticInst);
1101
1102 if (node)
1103 thread[tid]->profileNode = node;
1104 }
1105#endif
1106
1107 if (head_inst->traceData) {
1108 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1109 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1110 head_inst->traceData->finalize();
1111 head_inst->traceData = NULL;
1112 }
1113
1114 // Update the commit rename map
1115 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1116 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1117 head_inst->renamedDestRegIdx(i));
1118 }
1119
1120 if (head_inst->isCopy())
1121 panic("Should not commit any copy instructions!");
1122
1123 // Finally clear the head ROB entry.
1124 rob->retireHead(tid);
1125
1126 // Return true to indicate that we have committed an instruction.
1127 return true;
1128}
1129
1130template <class Impl>
1131void
1132DefaultCommit<Impl>::getInsts()
1133{
1134 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1135
1136#if ISA_HAS_DELAY_SLOT
1137 // Read any renamed instructions and place them into the ROB.
1138 int insts_to_process = std::min((int)renameWidth,
1139 (int)(fromRename->size + skidBuffer.size()));
1140 int rename_idx = 0;
1141
1142 DPRINTF(Commit, "%i insts available to process. Rename Insts:%i "
1143 "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size,
1144 skidBuffer.size());
1145#else
1146 // Read any renamed instructions and place them into the ROB.
1147 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1148#endif
1149
1150
1151 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1152 DynInstPtr inst;
1153
1154#if ISA_HAS_DELAY_SLOT
1155 // Get insts from skidBuffer or from Rename
1156 if (skidBuffer.size() > 0) {
1157 DPRINTF(Commit, "Grabbing skidbuffer inst.\n");
1158 inst = skidBuffer.front();
1159 skidBuffer.pop();
1160 } else {
1161 DPRINTF(Commit, "Grabbing rename inst.\n");
1162 inst = fromRename->insts[rename_idx++];
1163 }
1164#else
1165 inst = fromRename->insts[inst_num];
1166#endif
1167 int tid = inst->threadNumber;
1168
1169 if (!inst->isSquashed() &&
1170 commitStatus[tid] != ROBSquashing) {
1171 changedROBNumEntries[tid] = true;
1172
1173 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1174 inst->readPC(), inst->seqNum, tid);
1175
1176 rob->insertInst(inst);
1177
1178 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1179
1180 youngestSeqNum[tid] = inst->seqNum;
1181 } else {
1182 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1183 "squashed, skipping.\n",
1184 inst->readPC(), inst->seqNum, tid);
1185 }
1186 }
1187
1188#if ISA_HAS_DELAY_SLOT
1189 if (rename_idx < fromRename->size) {
1190 DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n");
1191
1192 for (;
1193 rename_idx < fromRename->size;
1194 rename_idx++) {
1195 DynInstPtr inst = fromRename->insts[rename_idx];
1196
1197 if (!inst->isSquashed()) {
1198 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1199 "skidBuffer.\n", inst->readPC(), inst->seqNum,
1200 inst->threadNumber);
1201 skidBuffer.push(inst);
1202 } else {
1203 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1204 "squashed, skipping.\n",
1205 inst->readPC(), inst->seqNum, inst->threadNumber);
1206 }
1207 }
1208 }
1209#endif
1210
1211}
1212
1213template <class Impl>
1214void
1215DefaultCommit<Impl>::skidInsert()
1216{
1217 DPRINTF(Commit, "Attempting to any instructions from rename into "
1218 "skidBuffer.\n");
1219
1220 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1221 DynInstPtr inst = fromRename->insts[inst_num];
1222
1223 if (!inst->isSquashed()) {
1224 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1225 "skidBuffer.\n", inst->readPC(), inst->seqNum,
1226 inst->threadNumber);
1227 skidBuffer.push(inst);
1228 } else {
1229 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1230 "squashed, skipping.\n",
1231 inst->readPC(), inst->seqNum, inst->threadNumber);
1232 }
1233 }
1234}
1235
1236template <class Impl>
1237void
1238DefaultCommit<Impl>::markCompletedInsts()
1239{
1240 // Grab completed insts out of the IEW instruction queue, and mark
1241 // instructions completed within the ROB.
1242 for (int inst_num = 0;
1243 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1244 ++inst_num)
1245 {
1246 if (!fromIEW->insts[inst_num]->isSquashed()) {
1247 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1248 "within ROB.\n",
1249 fromIEW->insts[inst_num]->threadNumber,
1250 fromIEW->insts[inst_num]->readPC(),
1251 fromIEW->insts[inst_num]->seqNum);
1252
1253 // Mark the instruction as ready to commit.
1254 fromIEW->insts[inst_num]->setCanCommit();
1255 }
1256 }
1257}
1258
1259template <class Impl>
1260bool
1261DefaultCommit<Impl>::robDoneSquashing()
1262{
|
1257 std::list<unsigned>::iterator threads = (*activeThreads).begin();
| 1263 std::list<unsigned>::iterator threads = activeThreads->begin();
1264 std::list<unsigned>::iterator end = activeThreads->end();
|
1258
| 1265
|
1259 while (threads != (*activeThreads).end()) {
| 1266 while (threads != end) {
|
1260 unsigned tid = *threads++;
1261
1262 if (!rob->isDoneSquashing(tid))
1263 return false;
1264 }
1265
1266 return true;
1267}
1268
1269template <class Impl>
1270void
1271DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1272{
1273 unsigned thread = inst->threadNumber;
1274
1275 //
1276 // Pick off the software prefetches
1277 //
1278#ifdef TARGET_ALPHA
1279 if (inst->isDataPrefetch()) {
1280 statComSwp[thread]++;
1281 } else {
1282 statComInst[thread]++;
1283 }
1284#else
1285 statComInst[thread]++;
1286#endif
1287
1288 //
1289 // Control Instructions
1290 //
1291 if (inst->isControl())
1292 statComBranches[thread]++;
1293
1294 //
1295 // Memory references
1296 //
1297 if (inst->isMemRef()) {
1298 statComRefs[thread]++;
1299
1300 if (inst->isLoad()) {
1301 statComLoads[thread]++;
1302 }
1303 }
1304
1305 if (inst->isMemBarrier()) {
1306 statComMembars[thread]++;
1307 }
1308}
1309
1310////////////////////////////////////////
1311// //
1312// SMT COMMIT POLICY MAINTAINED HERE //
1313// //
1314////////////////////////////////////////
1315template <class Impl>
1316int
1317DefaultCommit<Impl>::getCommittingThread()
1318{
1319 if (numThreads > 1) {
1320 switch (commitPolicy) {
1321
1322 case Aggressive:
1323 //If Policy is Aggressive, commit will call
1324 //this function multiple times per
1325 //cycle
1326 return oldestReady();
1327
1328 case RoundRobin:
1329 return roundRobin();
1330
1331 case OldestReady:
1332 return oldestReady();
1333
1334 default:
1335 return -1;
1336 }
1337 } else {
| 1267 unsigned tid = *threads++;
1268
1269 if (!rob->isDoneSquashing(tid))
1270 return false;
1271 }
1272
1273 return true;
1274}
1275
1276template <class Impl>
1277void
1278DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1279{
1280 unsigned thread = inst->threadNumber;
1281
1282 //
1283 // Pick off the software prefetches
1284 //
1285#ifdef TARGET_ALPHA
1286 if (inst->isDataPrefetch()) {
1287 statComSwp[thread]++;
1288 } else {
1289 statComInst[thread]++;
1290 }
1291#else
1292 statComInst[thread]++;
1293#endif
1294
1295 //
1296 // Control Instructions
1297 //
1298 if (inst->isControl())
1299 statComBranches[thread]++;
1300
1301 //
1302 // Memory references
1303 //
1304 if (inst->isMemRef()) {
1305 statComRefs[thread]++;
1306
1307 if (inst->isLoad()) {
1308 statComLoads[thread]++;
1309 }
1310 }
1311
1312 if (inst->isMemBarrier()) {
1313 statComMembars[thread]++;
1314 }
1315}
1316
1317////////////////////////////////////////
1318// //
1319// SMT COMMIT POLICY MAINTAINED HERE //
1320// //
1321////////////////////////////////////////
1322template <class Impl>
1323int
1324DefaultCommit<Impl>::getCommittingThread()
1325{
1326 if (numThreads > 1) {
1327 switch (commitPolicy) {
1328
1329 case Aggressive:
1330 //If Policy is Aggressive, commit will call
1331 //this function multiple times per
1332 //cycle
1333 return oldestReady();
1334
1335 case RoundRobin:
1336 return roundRobin();
1337
1338 case OldestReady:
1339 return oldestReady();
1340
1341 default:
1342 return -1;
1343 }
1344 } else {
|
1338 int tid = (*activeThreads).front();
| 1345 assert(!activeThreads->empty());
1346 int tid = activeThreads->front();
|
1339
1340 if (commitStatus[tid] == Running ||
1341 commitStatus[tid] == Idle ||
1342 commitStatus[tid] == FetchTrapPending) {
1343 return tid;
1344 } else {
1345 return -1;
1346 }
1347 }
1348}
1349
1350template<class Impl>
1351int
1352DefaultCommit<Impl>::roundRobin()
1353{
1354 std::list<unsigned>::iterator pri_iter = priority_list.begin();
1355 std::list<unsigned>::iterator end = priority_list.end();
1356
1357 while (pri_iter != end) {
1358 unsigned tid = *pri_iter;
1359
1360 if (commitStatus[tid] == Running ||
1361 commitStatus[tid] == Idle ||
1362 commitStatus[tid] == FetchTrapPending) {
1363
1364 if (rob->isHeadReady(tid)) {
1365 priority_list.erase(pri_iter);
1366 priority_list.push_back(tid);
1367
1368 return tid;
1369 }
1370 }
1371
1372 pri_iter++;
1373 }
1374
1375 return -1;
1376}
1377
1378template<class Impl>
1379int
1380DefaultCommit<Impl>::oldestReady()
1381{
1382 unsigned oldest = 0;
1383 bool first = true;
1384
| 1347
1348 if (commitStatus[tid] == Running ||
1349 commitStatus[tid] == Idle ||
1350 commitStatus[tid] == FetchTrapPending) {
1351 return tid;
1352 } else {
1353 return -1;
1354 }
1355 }
1356}
1357
1358template<class Impl>
1359int
1360DefaultCommit<Impl>::roundRobin()
1361{
1362 std::list<unsigned>::iterator pri_iter = priority_list.begin();
1363 std::list<unsigned>::iterator end = priority_list.end();
1364
1365 while (pri_iter != end) {
1366 unsigned tid = *pri_iter;
1367
1368 if (commitStatus[tid] == Running ||
1369 commitStatus[tid] == Idle ||
1370 commitStatus[tid] == FetchTrapPending) {
1371
1372 if (rob->isHeadReady(tid)) {
1373 priority_list.erase(pri_iter);
1374 priority_list.push_back(tid);
1375
1376 return tid;
1377 }
1378 }
1379
1380 pri_iter++;
1381 }
1382
1383 return -1;
1384}
1385
1386template<class Impl>
1387int
1388DefaultCommit<Impl>::oldestReady()
1389{
1390 unsigned oldest = 0;
1391 bool first = true;
1392
|
1385 std::list<unsigned>::iterator threads = (*activeThreads).begin();
| 1393 std::list<unsigned>::iterator threads = activeThreads->begin();
1394 std::list<unsigned>::iterator end = activeThreads->end();
|
1386
| 1395
|
1387 while (threads != (*activeThreads).end()) {
| 1396 while (threads != end) {
|
1388 unsigned tid = *threads++;
1389
1390 if (!rob->isEmpty(tid) &&
1391 (commitStatus[tid] == Running ||
1392 commitStatus[tid] == Idle ||
1393 commitStatus[tid] == FetchTrapPending)) {
1394
1395 if (rob->isHeadReady(tid)) {
1396
1397 DynInstPtr head_inst = rob->readHeadInst(tid);
1398
1399 if (first) {
1400 oldest = tid;
1401 first = false;
1402 } else if (head_inst->seqNum < oldest) {
1403 oldest = tid;
1404 }
1405 }
1406 }
1407 }
1408
1409 if (!first) {
1410 return oldest;
1411 } else {
1412 return -1;
1413 }
1414}
| 1397 unsigned tid = *threads++;
1398
1399 if (!rob->isEmpty(tid) &&
1400 (commitStatus[tid] == Running ||
1401 commitStatus[tid] == Idle ||
1402 commitStatus[tid] == FetchTrapPending)) {
1403
1404 if (rob->isHeadReady(tid)) {
1405
1406 DynInstPtr head_inst = rob->readHeadInst(tid);
1407
1408 if (first) {
1409 oldest = tid;
1410 first = false;
1411 } else if (head_inst->seqNum < oldest) {
1412 oldest = tid;
1413 }
1414 }
1415 }
1416 }
1417
1418 if (!first) {
1419 return oldest;
1420 } else {
1421 return -1;
1422 }
1423}
|