1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
35#include <algorithm>
36#include <string>
37
38#include "arch/utility.hh"
39#include "base/loader/symtab.hh"
40#include "base/timebuf.hh"
41#include "cpu/exetrace.hh"
42#include "cpu/o3/commit.hh"
43#include "cpu/o3/thread_state.hh"
44
45#if USE_CHECKER
46#include "cpu/checker/cpu.hh"
47#endif
48
49template <class Impl>
50DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
51 unsigned _tid)
52 : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
53{
54 this->setFlags(Event::AutoDelete);
55}
56
57template <class Impl>
58void
59DefaultCommit<Impl>::TrapEvent::process()
60{
61 // This will get reset by commit if it was switched out at the
62 // time of this event processing.
63 commit->trapSquash[tid] = true;
64}
65
66template <class Impl>
67const char *
68DefaultCommit<Impl>::TrapEvent::description()
69{
70 return "Trap event";
71}
72
73template <class Impl>
74DefaultCommit<Impl>::DefaultCommit(Params *params)
75 : squashCounter(0),
76 iewToCommitDelay(params->iewToCommitDelay),
77 commitToIEWDelay(params->commitToIEWDelay),
78 renameToROBDelay(params->renameToROBDelay),
79 fetchToCommitDelay(params->commitToFetchDelay),
80 renameWidth(params->renameWidth),
81 commitWidth(params->commitWidth),
82 numThreads(params->numberOfThreads),
83 drainPending(false),
84 switchedOut(false),
85 trapLatency(params->trapLatency)
86{
87 _status = Active;
88 _nextStatus = Inactive;
89 std::string policy = params->smtCommitPolicy;
90
91 //Convert string to lowercase
92 std::transform(policy.begin(), policy.end(), policy.begin(),
93 (int(*)(int)) tolower);
94
95 //Assign commit policy
96 if (policy == "aggressive"){
97 commitPolicy = Aggressive;
98
99 DPRINTF(Commit,"Commit Policy set to Aggressive.");
100 } else if (policy == "roundrobin"){
101 commitPolicy = RoundRobin;
102
103 //Set-Up Priority List
104 for (int tid=0; tid < numThreads; tid++) {
105 priority_list.push_back(tid);
106 }
107
108 DPRINTF(Commit,"Commit Policy set to Round Robin.");
109 } else if (policy == "oldestready"){
110 commitPolicy = OldestReady;
111
112 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
113 } else {
114 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
115 "RoundRobin,OldestReady}");
116 }
117
118 for (int i=0; i < numThreads; i++) {
119 commitStatus[i] = Idle;
120 changedROBNumEntries[i] = false;
121 trapSquash[i] = false;
122 tcSquash[i] = false;
123 PC[i] = nextPC[i] = nextNPC[i] = 0;
124 }
125#if FULL_SYSTEM
126 interrupt = NoFault;
127#endif
128}
129
130template <class Impl>
131std::string
132DefaultCommit<Impl>::name() const
133{
134 return cpu->name() + ".commit";
135}
136
137template <class Impl>
138void
139DefaultCommit<Impl>::regStats()
140{
141 using namespace Stats;
142 commitCommittedInsts
143 .name(name() + ".commitCommittedInsts")
144 .desc("The number of committed instructions")
145 .prereq(commitCommittedInsts);
146 commitSquashedInsts
147 .name(name() + ".commitSquashedInsts")
148 .desc("The number of squashed insts skipped by commit")
149 .prereq(commitSquashedInsts);
150 commitSquashEvents
151 .name(name() + ".commitSquashEvents")
152 .desc("The number of times commit is told to squash")
153 .prereq(commitSquashEvents);
154 commitNonSpecStalls
155 .name(name() + ".commitNonSpecStalls")
156 .desc("The number of times commit has been forced to stall to "
157 "communicate backwards")
158 .prereq(commitNonSpecStalls);
159 branchMispredicts
160 .name(name() + ".branchMispredicts")
161 .desc("The number of times a branch was mispredicted")
162 .prereq(branchMispredicts);
163 numCommittedDist
164 .init(0,commitWidth,1)
165 .name(name() + ".COM:committed_per_cycle")
166 .desc("Number of insts commited each cycle")
167 .flags(Stats::pdf)
168 ;
169
170 statComInst
171 .init(cpu->number_of_threads)
172 .name(name() + ".COM:count")
173 .desc("Number of instructions committed")
174 .flags(total)
175 ;
176
177 statComSwp
178 .init(cpu->number_of_threads)
179 .name(name() + ".COM:swp_count")
180 .desc("Number of s/w prefetches committed")
181 .flags(total)
182 ;
183
184 statComRefs
185 .init(cpu->number_of_threads)
186 .name(name() + ".COM:refs")
187 .desc("Number of memory references committed")
188 .flags(total)
189 ;
190
191 statComLoads
192 .init(cpu->number_of_threads)
193 .name(name() + ".COM:loads")
194 .desc("Number of loads committed")
195 .flags(total)
196 ;
197
198 statComMembars
199 .init(cpu->number_of_threads)
200 .name(name() + ".COM:membars")
201 .desc("Number of memory barriers committed")
202 .flags(total)
203 ;
204
205 statComBranches
206 .init(cpu->number_of_threads)
207 .name(name() + ".COM:branches")
208 .desc("Number of branches committed")
209 .flags(total)
210 ;
211
212 commitEligible
213 .init(cpu->number_of_threads)
214 .name(name() + ".COM:bw_limited")
215 .desc("number of insts not committed due to BW limits")
216 .flags(total)
217 ;
218
219 commitEligibleSamples
220 .name(name() + ".COM:bw_lim_events")
221 .desc("number cycles where commit BW limit reached")
222 ;
223}
224
225template <class Impl>
226void
227DefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr)
228{
229 DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
230 cpu = cpu_ptr;
231
232 // Commit must broadcast the number of free entries it has at the start of
233 // the simulation, so it starts as active.
234 cpu->activateStage(O3CPU::CommitIdx);
235
236 trapLatency = cpu->cycles(trapLatency);
237}
238
239template <class Impl>
240void
241DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
242{
243 thread = threads;
244}
245
246template <class Impl>
247void
248DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
249{
250 DPRINTF(Commit, "Commit: Setting time buffer pointer.\n");
251 timeBuffer = tb_ptr;
252
253 // Setup wire to send information back to IEW.
254 toIEW = timeBuffer->getWire(0);
255
256 // Setup wire to read data from IEW (for the ROB).
257 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
258}
259
260template <class Impl>
261void
262DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
263{
264 DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n");
265 fetchQueue = fq_ptr;
266
267 // Setup wire to get instructions from rename (for the ROB).
268 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
269}
270
271template <class Impl>
272void
273DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
274{
275 DPRINTF(Commit, "Commit: Setting rename queue pointer.\n");
276 renameQueue = rq_ptr;
277
278 // Setup wire to get instructions from rename (for the ROB).
279 fromRename = renameQueue->getWire(-renameToROBDelay);
280}
281
282template <class Impl>
283void
284DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
285{
286 DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n");
287 iewQueue = iq_ptr;
288
289 // Setup wire to get instructions from IEW.
290 fromIEW = iewQueue->getWire(-iewToCommitDelay);
291}
292
293template <class Impl>
294void
295DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
296{
297 iewStage = iew_stage;
298}
299
300template<class Impl>
301void
302DefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
303{
304 DPRINTF(Commit, "Commit: Setting active threads list pointer.\n");
305 activeThreads = at_ptr;
306}
307
308template <class Impl>
309void
310DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
311{
312 DPRINTF(Commit, "Setting rename map pointers.\n");
313
314 for (int i=0; i < numThreads; i++) {
315 renameMap[i] = &rm_ptr[i];
316 }
317}
318
319template <class Impl>
320void
321DefaultCommit<Impl>::setROB(ROB *rob_ptr)
322{
323 DPRINTF(Commit, "Commit: Setting ROB pointer.\n");
324 rob = rob_ptr;
325}
326
327template <class Impl>
328void
329DefaultCommit<Impl>::initStage()
330{
331 rob->setActiveThreads(activeThreads);
332 rob->resetEntries();
333
334 // Broadcast the number of free entries.
335 for (int i=0; i < numThreads; i++) {
336 toIEW->commitInfo[i].usedROB = true;
337 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
338 }
339
340 cpu->activityThisCycle();
341}
342
343template <class Impl>
344bool
345DefaultCommit<Impl>::drain()
346{
347 drainPending = true;
348
349 return false;
350}
351
352template <class Impl>
353void
354DefaultCommit<Impl>::switchOut()
355{
356 switchedOut = true;
357 drainPending = false;
358 rob->switchOut();
359}
360
361template <class Impl>
362void
363DefaultCommit<Impl>::resume()
364{
365 drainPending = false;
366}
367
368template <class Impl>
369void
370DefaultCommit<Impl>::takeOverFrom()
371{
372 switchedOut = false;
373 _status = Active;
374 _nextStatus = Inactive;
375 for (int i=0; i < numThreads; i++) {
376 commitStatus[i] = Idle;
377 changedROBNumEntries[i] = false;
378 trapSquash[i] = false;
379 tcSquash[i] = false;
380 }
381 squashCounter = 0;
382 rob->takeOverFrom();
383}
384
385template <class Impl>
386void
387DefaultCommit<Impl>::updateStatus()
388{
389 // reset ROB changed variable
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#include "config/full_system.hh"
33#include "config/use_checker.hh"
34
35#include <algorithm>
36#include <string>
37
38#include "arch/utility.hh"
39#include "base/loader/symtab.hh"
40#include "base/timebuf.hh"
41#include "cpu/exetrace.hh"
42#include "cpu/o3/commit.hh"
43#include "cpu/o3/thread_state.hh"
44
45#if USE_CHECKER
46#include "cpu/checker/cpu.hh"
47#endif
48
49template <class Impl>
50DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
51 unsigned _tid)
52 : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
53{
54 this->setFlags(Event::AutoDelete);
55}
56
57template <class Impl>
58void
59DefaultCommit<Impl>::TrapEvent::process()
60{
61 // This will get reset by commit if it was switched out at the
62 // time of this event processing.
63 commit->trapSquash[tid] = true;
64}
65
66template <class Impl>
67const char *
68DefaultCommit<Impl>::TrapEvent::description()
69{
70 return "Trap event";
71}
72
73template <class Impl>
74DefaultCommit<Impl>::DefaultCommit(Params *params)
75 : squashCounter(0),
76 iewToCommitDelay(params->iewToCommitDelay),
77 commitToIEWDelay(params->commitToIEWDelay),
78 renameToROBDelay(params->renameToROBDelay),
79 fetchToCommitDelay(params->commitToFetchDelay),
80 renameWidth(params->renameWidth),
81 commitWidth(params->commitWidth),
82 numThreads(params->numberOfThreads),
83 drainPending(false),
84 switchedOut(false),
85 trapLatency(params->trapLatency)
86{
87 _status = Active;
88 _nextStatus = Inactive;
89 std::string policy = params->smtCommitPolicy;
90
91 //Convert string to lowercase
92 std::transform(policy.begin(), policy.end(), policy.begin(),
93 (int(*)(int)) tolower);
94
95 //Assign commit policy
96 if (policy == "aggressive"){
97 commitPolicy = Aggressive;
98
99 DPRINTF(Commit,"Commit Policy set to Aggressive.");
100 } else if (policy == "roundrobin"){
101 commitPolicy = RoundRobin;
102
103 //Set-Up Priority List
104 for (int tid=0; tid < numThreads; tid++) {
105 priority_list.push_back(tid);
106 }
107
108 DPRINTF(Commit,"Commit Policy set to Round Robin.");
109 } else if (policy == "oldestready"){
110 commitPolicy = OldestReady;
111
112 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
113 } else {
114 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
115 "RoundRobin,OldestReady}");
116 }
117
118 for (int i=0; i < numThreads; i++) {
119 commitStatus[i] = Idle;
120 changedROBNumEntries[i] = false;
121 trapSquash[i] = false;
122 tcSquash[i] = false;
123 PC[i] = nextPC[i] = nextNPC[i] = 0;
124 }
125#if FULL_SYSTEM
126 interrupt = NoFault;
127#endif
128}
129
130template <class Impl>
131std::string
132DefaultCommit<Impl>::name() const
133{
134 return cpu->name() + ".commit";
135}
136
137template <class Impl>
138void
139DefaultCommit<Impl>::regStats()
140{
141 using namespace Stats;
142 commitCommittedInsts
143 .name(name() + ".commitCommittedInsts")
144 .desc("The number of committed instructions")
145 .prereq(commitCommittedInsts);
146 commitSquashedInsts
147 .name(name() + ".commitSquashedInsts")
148 .desc("The number of squashed insts skipped by commit")
149 .prereq(commitSquashedInsts);
150 commitSquashEvents
151 .name(name() + ".commitSquashEvents")
152 .desc("The number of times commit is told to squash")
153 .prereq(commitSquashEvents);
154 commitNonSpecStalls
155 .name(name() + ".commitNonSpecStalls")
156 .desc("The number of times commit has been forced to stall to "
157 "communicate backwards")
158 .prereq(commitNonSpecStalls);
159 branchMispredicts
160 .name(name() + ".branchMispredicts")
161 .desc("The number of times a branch was mispredicted")
162 .prereq(branchMispredicts);
163 numCommittedDist
164 .init(0,commitWidth,1)
165 .name(name() + ".COM:committed_per_cycle")
166 .desc("Number of insts commited each cycle")
167 .flags(Stats::pdf)
168 ;
169
170 statComInst
171 .init(cpu->number_of_threads)
172 .name(name() + ".COM:count")
173 .desc("Number of instructions committed")
174 .flags(total)
175 ;
176
177 statComSwp
178 .init(cpu->number_of_threads)
179 .name(name() + ".COM:swp_count")
180 .desc("Number of s/w prefetches committed")
181 .flags(total)
182 ;
183
184 statComRefs
185 .init(cpu->number_of_threads)
186 .name(name() + ".COM:refs")
187 .desc("Number of memory references committed")
188 .flags(total)
189 ;
190
191 statComLoads
192 .init(cpu->number_of_threads)
193 .name(name() + ".COM:loads")
194 .desc("Number of loads committed")
195 .flags(total)
196 ;
197
198 statComMembars
199 .init(cpu->number_of_threads)
200 .name(name() + ".COM:membars")
201 .desc("Number of memory barriers committed")
202 .flags(total)
203 ;
204
205 statComBranches
206 .init(cpu->number_of_threads)
207 .name(name() + ".COM:branches")
208 .desc("Number of branches committed")
209 .flags(total)
210 ;
211
212 commitEligible
213 .init(cpu->number_of_threads)
214 .name(name() + ".COM:bw_limited")
215 .desc("number of insts not committed due to BW limits")
216 .flags(total)
217 ;
218
219 commitEligibleSamples
220 .name(name() + ".COM:bw_lim_events")
221 .desc("number cycles where commit BW limit reached")
222 ;
223}
224
225template <class Impl>
226void
227DefaultCommit<Impl>::setCPU(O3CPU *cpu_ptr)
228{
229 DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
230 cpu = cpu_ptr;
231
232 // Commit must broadcast the number of free entries it has at the start of
233 // the simulation, so it starts as active.
234 cpu->activateStage(O3CPU::CommitIdx);
235
236 trapLatency = cpu->cycles(trapLatency);
237}
238
239template <class Impl>
240void
241DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
242{
243 thread = threads;
244}
245
246template <class Impl>
247void
248DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
249{
250 DPRINTF(Commit, "Commit: Setting time buffer pointer.\n");
251 timeBuffer = tb_ptr;
252
253 // Setup wire to send information back to IEW.
254 toIEW = timeBuffer->getWire(0);
255
256 // Setup wire to read data from IEW (for the ROB).
257 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
258}
259
260template <class Impl>
261void
262DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
263{
264 DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n");
265 fetchQueue = fq_ptr;
266
267 // Setup wire to get instructions from rename (for the ROB).
268 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
269}
270
271template <class Impl>
272void
273DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
274{
275 DPRINTF(Commit, "Commit: Setting rename queue pointer.\n");
276 renameQueue = rq_ptr;
277
278 // Setup wire to get instructions from rename (for the ROB).
279 fromRename = renameQueue->getWire(-renameToROBDelay);
280}
281
282template <class Impl>
283void
284DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
285{
286 DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n");
287 iewQueue = iq_ptr;
288
289 // Setup wire to get instructions from IEW.
290 fromIEW = iewQueue->getWire(-iewToCommitDelay);
291}
292
293template <class Impl>
294void
295DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
296{
297 iewStage = iew_stage;
298}
299
300template<class Impl>
301void
302DefaultCommit<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
303{
304 DPRINTF(Commit, "Commit: Setting active threads list pointer.\n");
305 activeThreads = at_ptr;
306}
307
308template <class Impl>
309void
310DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
311{
312 DPRINTF(Commit, "Setting rename map pointers.\n");
313
314 for (int i=0; i < numThreads; i++) {
315 renameMap[i] = &rm_ptr[i];
316 }
317}
318
319template <class Impl>
320void
321DefaultCommit<Impl>::setROB(ROB *rob_ptr)
322{
323 DPRINTF(Commit, "Commit: Setting ROB pointer.\n");
324 rob = rob_ptr;
325}
326
327template <class Impl>
328void
329DefaultCommit<Impl>::initStage()
330{
331 rob->setActiveThreads(activeThreads);
332 rob->resetEntries();
333
334 // Broadcast the number of free entries.
335 for (int i=0; i < numThreads; i++) {
336 toIEW->commitInfo[i].usedROB = true;
337 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
338 }
339
340 cpu->activityThisCycle();
341}
342
343template <class Impl>
344bool
345DefaultCommit<Impl>::drain()
346{
347 drainPending = true;
348
349 return false;
350}
351
352template <class Impl>
353void
354DefaultCommit<Impl>::switchOut()
355{
356 switchedOut = true;
357 drainPending = false;
358 rob->switchOut();
359}
360
361template <class Impl>
362void
363DefaultCommit<Impl>::resume()
364{
365 drainPending = false;
366}
367
368template <class Impl>
369void
370DefaultCommit<Impl>::takeOverFrom()
371{
372 switchedOut = false;
373 _status = Active;
374 _nextStatus = Inactive;
375 for (int i=0; i < numThreads; i++) {
376 commitStatus[i] = Idle;
377 changedROBNumEntries[i] = false;
378 trapSquash[i] = false;
379 tcSquash[i] = false;
380 }
381 squashCounter = 0;
382 rob->takeOverFrom();
383}
384
385template <class Impl>
386void
387DefaultCommit<Impl>::updateStatus()
388{
389 // reset ROB changed variable
|
390 std::list<unsigned>::iterator threads = activeThreads->begin();
391 std::list<unsigned>::iterator end = activeThreads->end();
392
393 while (threads != end) {
| 390 std::list<unsigned>::iterator threads = (*activeThreads).begin();
391 while (threads != (*activeThreads).end()) {
|
394 unsigned tid = *threads++;
| 392 unsigned tid = *threads++;
|
395
| |
396 changedROBNumEntries[tid] = false;
397
398 // Also check if any of the threads has a trap pending
399 if (commitStatus[tid] == TrapPending ||
400 commitStatus[tid] == FetchTrapPending) {
401 _nextStatus = Active;
402 }
403 }
404
405 if (_nextStatus == Inactive && _status == Active) {
406 DPRINTF(Activity, "Deactivating stage.\n");
407 cpu->deactivateStage(O3CPU::CommitIdx);
408 } else if (_nextStatus == Active && _status == Inactive) {
409 DPRINTF(Activity, "Activating stage.\n");
410 cpu->activateStage(O3CPU::CommitIdx);
411 }
412
413 _status = _nextStatus;
414}
415
416template <class Impl>
417void
418DefaultCommit<Impl>::setNextStatus()
419{
420 int squashes = 0;
421
| 393 changedROBNumEntries[tid] = false;
394
395 // Also check if any of the threads has a trap pending
396 if (commitStatus[tid] == TrapPending ||
397 commitStatus[tid] == FetchTrapPending) {
398 _nextStatus = Active;
399 }
400 }
401
402 if (_nextStatus == Inactive && _status == Active) {
403 DPRINTF(Activity, "Deactivating stage.\n");
404 cpu->deactivateStage(O3CPU::CommitIdx);
405 } else if (_nextStatus == Active && _status == Inactive) {
406 DPRINTF(Activity, "Activating stage.\n");
407 cpu->activateStage(O3CPU::CommitIdx);
408 }
409
410 _status = _nextStatus;
411}
412
413template <class Impl>
414void
415DefaultCommit<Impl>::setNextStatus()
416{
417 int squashes = 0;
418
|
422 std::list<unsigned>::iterator threads = activeThreads->begin();
423 std::list<unsigned>::iterator end = activeThreads->end();
| 419 std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
424
| 420
|
425 while (threads != end) {
| 421 while (threads != (*activeThreads).end()) {
|
426 unsigned tid = *threads++;
427
428 if (commitStatus[tid] == ROBSquashing) {
429 squashes++;
430 }
431 }
432
433 squashCounter = squashes;
434
435 // If commit is currently squashing, then it will have activity for the
436 // next cycle. Set its next status as active.
437 if (squashCounter) {
438 _nextStatus = Active;
439 }
440}
441
442template <class Impl>
443bool
444DefaultCommit<Impl>::changedROBEntries()
445{
| 422 unsigned tid = *threads++;
423
424 if (commitStatus[tid] == ROBSquashing) {
425 squashes++;
426 }
427 }
428
429 squashCounter = squashes;
430
431 // If commit is currently squashing, then it will have activity for the
432 // next cycle. Set its next status as active.
433 if (squashCounter) {
434 _nextStatus = Active;
435 }
436}
437
438template <class Impl>
439bool
440DefaultCommit<Impl>::changedROBEntries()
441{
|
446 std::list<unsigned>::iterator threads = activeThreads->begin();
447 std::list<unsigned>::iterator end = activeThreads->end();
| 442 std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
448
| 443
|
449 while (threads != end) {
| 444 while (threads != (*activeThreads).end()) {
|
450 unsigned tid = *threads++;
451
452 if (changedROBNumEntries[tid]) {
453 return true;
454 }
455 }
456
457 return false;
458}
459
460template <class Impl>
461unsigned
462DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
463{
464 return rob->numFreeEntries(tid);
465}
466
467template <class Impl>
468void
469DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
470{
471 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
472
473 TrapEvent *trap = new TrapEvent(this, tid);
474
475 trap->schedule(curTick + trapLatency);
476
477 thread[tid]->trapPending = true;
478}
479
480template <class Impl>
481void
482DefaultCommit<Impl>::generateTCEvent(unsigned tid)
483{
484 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
485
486 tcSquash[tid] = true;
487}
488
489template <class Impl>
490void
491DefaultCommit<Impl>::squashAll(unsigned tid)
492{
493 // If we want to include the squashing instruction in the squash,
494 // then use one older sequence number.
495 // Hopefully this doesn't mess things up. Basically I want to squash
496 // all instructions of this thread.
497 InstSeqNum squashed_inst = rob->isEmpty() ?
498 0 : rob->readHeadInst(tid)->seqNum - 1;;
499
500 // All younger instructions will be squashed. Set the sequence
501 // number as the youngest instruction in the ROB (0 in this case.
502 // Hopefully nothing breaks.)
503 youngestSeqNum[tid] = 0;
504
505 rob->squash(squashed_inst, tid);
506 changedROBNumEntries[tid] = true;
507
508 // Send back the sequence number of the squashed instruction.
509 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
510
511 // Send back the squash signal to tell stages that they should
512 // squash.
513 toIEW->commitInfo[tid].squash = true;
514
515 // Send back the rob squashing signal so other stages know that
516 // the ROB is in the process of squashing.
517 toIEW->commitInfo[tid].robSquashing = true;
518
519 toIEW->commitInfo[tid].branchMispredict = false;
520
521 toIEW->commitInfo[tid].nextPC = PC[tid];
| 445 unsigned tid = *threads++;
446
447 if (changedROBNumEntries[tid]) {
448 return true;
449 }
450 }
451
452 return false;
453}
454
455template <class Impl>
456unsigned
457DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
458{
459 return rob->numFreeEntries(tid);
460}
461
462template <class Impl>
463void
464DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
465{
466 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
467
468 TrapEvent *trap = new TrapEvent(this, tid);
469
470 trap->schedule(curTick + trapLatency);
471
472 thread[tid]->trapPending = true;
473}
474
475template <class Impl>
476void
477DefaultCommit<Impl>::generateTCEvent(unsigned tid)
478{
479 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
480
481 tcSquash[tid] = true;
482}
483
484template <class Impl>
485void
486DefaultCommit<Impl>::squashAll(unsigned tid)
487{
488 // If we want to include the squashing instruction in the squash,
489 // then use one older sequence number.
490 // Hopefully this doesn't mess things up. Basically I want to squash
491 // all instructions of this thread.
492 InstSeqNum squashed_inst = rob->isEmpty() ?
493 0 : rob->readHeadInst(tid)->seqNum - 1;;
494
495 // All younger instructions will be squashed. Set the sequence
496 // number as the youngest instruction in the ROB (0 in this case.
497 // Hopefully nothing breaks.)
498 youngestSeqNum[tid] = 0;
499
500 rob->squash(squashed_inst, tid);
501 changedROBNumEntries[tid] = true;
502
503 // Send back the sequence number of the squashed instruction.
504 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
505
506 // Send back the squash signal to tell stages that they should
507 // squash.
508 toIEW->commitInfo[tid].squash = true;
509
510 // Send back the rob squashing signal so other stages know that
511 // the ROB is in the process of squashing.
512 toIEW->commitInfo[tid].robSquashing = true;
513
514 toIEW->commitInfo[tid].branchMispredict = false;
515
516 toIEW->commitInfo[tid].nextPC = PC[tid];
|
| 517 toIEW->commitInfo[tid].nextNPC = nextPC[tid];
|
522}
523
524template <class Impl>
525void
526DefaultCommit<Impl>::squashFromTrap(unsigned tid)
527{
528 squashAll(tid);
529
530 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
531
532 thread[tid]->trapPending = false;
533 thread[tid]->inSyscall = false;
534
535 trapSquash[tid] = false;
536
537 commitStatus[tid] = ROBSquashing;
538 cpu->activityThisCycle();
539}
540
541template <class Impl>
542void
543DefaultCommit<Impl>::squashFromTC(unsigned tid)
544{
545 squashAll(tid);
546
547 DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
548
549 thread[tid]->inSyscall = false;
550 assert(!thread[tid]->trapPending);
551
552 commitStatus[tid] = ROBSquashing;
553 cpu->activityThisCycle();
554
555 tcSquash[tid] = false;
556}
557
558template <class Impl>
559void
560DefaultCommit<Impl>::tick()
561{
562 wroteToTimeBuffer = false;
563 _nextStatus = Inactive;
564
565 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
566 cpu->signalDrained();
567 drainPending = false;
568 return;
569 }
570
| 518}
519
520template <class Impl>
521void
522DefaultCommit<Impl>::squashFromTrap(unsigned tid)
523{
524 squashAll(tid);
525
526 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
527
528 thread[tid]->trapPending = false;
529 thread[tid]->inSyscall = false;
530
531 trapSquash[tid] = false;
532
533 commitStatus[tid] = ROBSquashing;
534 cpu->activityThisCycle();
535}
536
537template <class Impl>
538void
539DefaultCommit<Impl>::squashFromTC(unsigned tid)
540{
541 squashAll(tid);
542
543 DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
544
545 thread[tid]->inSyscall = false;
546 assert(!thread[tid]->trapPending);
547
548 commitStatus[tid] = ROBSquashing;
549 cpu->activityThisCycle();
550
551 tcSquash[tid] = false;
552}
553
554template <class Impl>
555void
556DefaultCommit<Impl>::tick()
557{
558 wroteToTimeBuffer = false;
559 _nextStatus = Inactive;
560
561 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
562 cpu->signalDrained();
563 drainPending = false;
564 return;
565 }
566
|
571 if (activeThreads->empty())
| 567 if ((*activeThreads).size() <= 0)
|
572 return;
573
| 568 return;
569
|
574 std::list<unsigned>::iterator threads = activeThreads->begin();
575 std::list<unsigned>::iterator end = activeThreads->end();
| 570 std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
576
577 // Check if any of the threads are done squashing. Change the
578 // status if they are done.
| 571
572 // Check if any of the threads are done squashing. Change the
573 // status if they are done.
|
579 while (threads != end) {
| 574 while (threads != (*activeThreads).end()) {
|
580 unsigned tid = *threads++;
581
582 if (commitStatus[tid] == ROBSquashing) {
583
584 if (rob->isDoneSquashing(tid)) {
585 commitStatus[tid] = Running;
586 } else {
587 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
588 " insts this cycle.\n", tid);
589 rob->doSquash(tid);
590 toIEW->commitInfo[tid].robSquashing = true;
591 wroteToTimeBuffer = true;
592 }
593 }
594 }
595
596 commit();
597
598 markCompletedInsts();
599
| 575 unsigned tid = *threads++;
576
577 if (commitStatus[tid] == ROBSquashing) {
578
579 if (rob->isDoneSquashing(tid)) {
580 commitStatus[tid] = Running;
581 } else {
582 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
583 " insts this cycle.\n", tid);
584 rob->doSquash(tid);
585 toIEW->commitInfo[tid].robSquashing = true;
586 wroteToTimeBuffer = true;
587 }
588 }
589 }
590
591 commit();
592
593 markCompletedInsts();
594
|
600 threads = activeThreads->begin();
| 595 threads = (*activeThreads).begin();
|
601
| 596
|
602 while (threads != end) {
| 597 while (threads != (*activeThreads).end()) {
|
603 unsigned tid = *threads++;
604
605 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
606 // The ROB has more instructions it can commit. Its next status
607 // will be active.
608 _nextStatus = Active;
609
610 DynInstPtr inst = rob->readHeadInst(tid);
611
612 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
613 " ROB and ready to commit\n",
614 tid, inst->seqNum, inst->readPC());
615
616 } else if (!rob->isEmpty(tid)) {
617 DynInstPtr inst = rob->readHeadInst(tid);
618
619 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
620 "%#x is head of ROB and not ready\n",
621 tid, inst->seqNum, inst->readPC());
622 }
623
624 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
625 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
626 }
627
628
629 if (wroteToTimeBuffer) {
630 DPRINTF(Activity, "Activity This Cycle.\n");
631 cpu->activityThisCycle();
632 }
633
634 updateStatus();
635}
636
637template <class Impl>
638void
639DefaultCommit<Impl>::commit()
640{
641
642 //////////////////////////////////////
643 // Check for interrupts
644 //////////////////////////////////////
645
646#if FULL_SYSTEM
647 if (interrupt != NoFault) {
648 // Wait until the ROB is empty and all stores have drained in
649 // order to enter the interrupt.
650 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
651 // Squash or record that I need to squash this cycle if
652 // an interrupt needed to be handled.
653 DPRINTF(Commit, "Interrupt detected.\n");
654
655 assert(!thread[0]->inSyscall);
656 thread[0]->inSyscall = true;
657
658 // CPU will handle interrupt.
659 cpu->processInterrupts(interrupt);
660
661 thread[0]->inSyscall = false;
662
663 commitStatus[0] = TrapPending;
664
665 // Generate trap squash event.
666 generateTrapEvent(0);
667
668 // Clear the interrupt now that it's been handled
669 toIEW->commitInfo[0].clearInterrupt = true;
670 interrupt = NoFault;
671 } else {
672 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
673 }
| 598 unsigned tid = *threads++;
599
600 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
601 // The ROB has more instructions it can commit. Its next status
602 // will be active.
603 _nextStatus = Active;
604
605 DynInstPtr inst = rob->readHeadInst(tid);
606
607 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
608 " ROB and ready to commit\n",
609 tid, inst->seqNum, inst->readPC());
610
611 } else if (!rob->isEmpty(tid)) {
612 DynInstPtr inst = rob->readHeadInst(tid);
613
614 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
615 "%#x is head of ROB and not ready\n",
616 tid, inst->seqNum, inst->readPC());
617 }
618
619 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
620 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
621 }
622
623
624 if (wroteToTimeBuffer) {
625 DPRINTF(Activity, "Activity This Cycle.\n");
626 cpu->activityThisCycle();
627 }
628
629 updateStatus();
630}
631
632template <class Impl>
633void
634DefaultCommit<Impl>::commit()
635{
636
637 //////////////////////////////////////
638 // Check for interrupts
639 //////////////////////////////////////
640
641#if FULL_SYSTEM
642 if (interrupt != NoFault) {
643 // Wait until the ROB is empty and all stores have drained in
644 // order to enter the interrupt.
645 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
646 // Squash or record that I need to squash this cycle if
647 // an interrupt needed to be handled.
648 DPRINTF(Commit, "Interrupt detected.\n");
649
650 assert(!thread[0]->inSyscall);
651 thread[0]->inSyscall = true;
652
653 // CPU will handle interrupt.
654 cpu->processInterrupts(interrupt);
655
656 thread[0]->inSyscall = false;
657
658 commitStatus[0] = TrapPending;
659
660 // Generate trap squash event.
661 generateTrapEvent(0);
662
663 // Clear the interrupt now that it's been handled
664 toIEW->commitInfo[0].clearInterrupt = true;
665 interrupt = NoFault;
666 } else {
667 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
668 }
|
674 } else if (cpu->check_interrupts(cpu->tcBase(0)) &&
| 669 } else if (cpu->checkInterrupts &&
670 cpu->check_interrupts(cpu->tcBase(0)) &&
|
675 commitStatus[0] != TrapPending &&
676 !trapSquash[0] &&
677 !tcSquash[0]) {
678 // Process interrupts if interrupts are enabled, not in PAL
679 // mode, and no other traps or external squashes are currently
680 // pending.
681 // @todo: Allow other threads to handle interrupts.
682
683 // Get any interrupt that happened
684 interrupt = cpu->getInterrupts();
685
686 if (interrupt != NoFault) {
687 // Tell fetch that there is an interrupt pending. This
688 // will make fetch wait until it sees a non PAL-mode PC,
689 // at which point it stops fetching instructions.
690 toIEW->commitInfo[0].interruptPending = true;
691 }
692 }
693
694#endif // FULL_SYSTEM
695
696 ////////////////////////////////////
697 // Check for any possible squashes, handle them first
698 ////////////////////////////////////
| 671 commitStatus[0] != TrapPending &&
672 !trapSquash[0] &&
673 !tcSquash[0]) {
674 // Process interrupts if interrupts are enabled, not in PAL
675 // mode, and no other traps or external squashes are currently
676 // pending.
677 // @todo: Allow other threads to handle interrupts.
678
679 // Get any interrupt that happened
680 interrupt = cpu->getInterrupts();
681
682 if (interrupt != NoFault) {
683 // Tell fetch that there is an interrupt pending. This
684 // will make fetch wait until it sees a non PAL-mode PC,
685 // at which point it stops fetching instructions.
686 toIEW->commitInfo[0].interruptPending = true;
687 }
688 }
689
690#endif // FULL_SYSTEM
691
692 ////////////////////////////////////
693 // Check for any possible squashes, handle them first
694 ////////////////////////////////////
|
699 std::list<unsigned>::iterator threads = activeThreads->begin();
700 std::list<unsigned>::iterator end = activeThreads->end();
| 695 std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
701
| 696
|
702 while (threads != end) {
| 697 while (threads != (*activeThreads).end()) {
|
703 unsigned tid = *threads++;
704
705 // Not sure which one takes priority. I think if we have
706 // both, that's a bad sign.
707 if (trapSquash[tid] == true) {
708 assert(!tcSquash[tid]);
709 squashFromTrap(tid);
710 } else if (tcSquash[tid] == true) {
711 squashFromTC(tid);
712 }
713
714 // Squashed sequence number must be older than youngest valid
715 // instruction in the ROB. This prevents squashes from younger
716 // instructions overriding squashes from older instructions.
717 if (fromIEW->squash[tid] &&
718 commitStatus[tid] != TrapPending &&
719 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
720
721 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
722 tid,
723 fromIEW->mispredPC[tid],
724 fromIEW->squashedSeqNum[tid]);
725
726 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
727 tid,
728 fromIEW->nextPC[tid]);
729
730 commitStatus[tid] = ROBSquashing;
731
732 // If we want to include the squashing instruction in the squash,
733 // then use one older sequence number.
734 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
735
736#if ISA_HAS_DELAY_SLOT
| 698 unsigned tid = *threads++;
699
700 // Not sure which one takes priority. I think if we have
701 // both, that's a bad sign.
702 if (trapSquash[tid] == true) {
703 assert(!tcSquash[tid]);
704 squashFromTrap(tid);
705 } else if (tcSquash[tid] == true) {
706 squashFromTC(tid);
707 }
708
709 // Squashed sequence number must be older than youngest valid
710 // instruction in the ROB. This prevents squashes from younger
711 // instructions overriding squashes from older instructions.
712 if (fromIEW->squash[tid] &&
713 commitStatus[tid] != TrapPending &&
714 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
715
716 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
717 tid,
718 fromIEW->mispredPC[tid],
719 fromIEW->squashedSeqNum[tid]);
720
721 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
722 tid,
723 fromIEW->nextPC[tid]);
724
725 commitStatus[tid] = ROBSquashing;
726
727 // If we want to include the squashing instruction in the squash,
728 // then use one older sequence number.
729 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
730
731#if ISA_HAS_DELAY_SLOT
|
737 InstSeqNum bdelay_done_seq_num;
738 bool squash_bdelay_slot;
| 732 InstSeqNum bdelay_done_seq_num = squashed_inst;
733 bool squash_bdelay_slot = fromIEW->squashDelaySlot[tid];
734 bool branchMispredict = fromIEW->branchMispredict[tid];
|
739
| 735
|
740 if (fromIEW->branchMispredict[tid]) {
741 if (fromIEW->branchTaken[tid] &&
742 fromIEW->condDelaySlotBranch[tid]) {
743 DPRINTF(Commit, "[tid:%i]: Cond. delay slot branch"
744 "mispredicted as taken. Squashing after previous "
745 "inst, [sn:%i]\n",
746 tid, squashed_inst);
747 bdelay_done_seq_num = squashed_inst;
748 squash_bdelay_slot = true;
749 } else {
750 DPRINTF(Commit, "[tid:%i]: Branch Mispredict. Squashing "
751 "after delay slot [sn:%i]\n", tid, squashed_inst+1);
752 bdelay_done_seq_num = squashed_inst + 1;
753 squash_bdelay_slot = false;
754 }
755 } else {
756 bdelay_done_seq_num = squashed_inst;
757 squash_bdelay_slot = true;
| 736 // Squashing/not squashing the branch delay slot only makes
737 // sense when you're squashing from a branch, ie from a branch
738 // mispredict.
739 if (branchMispredict && !squash_bdelay_slot) {
740 bdelay_done_seq_num++;
|
758 }
759#endif
760
761 if (fromIEW->includeSquashInst[tid] == true) {
762 squashed_inst--;
763#if ISA_HAS_DELAY_SLOT
764 bdelay_done_seq_num--;
765#endif
766 }
767 // All younger instructions will be squashed. Set the sequence
768 // number as the youngest instruction in the ROB.
769 youngestSeqNum[tid] = squashed_inst;
770
771#if ISA_HAS_DELAY_SLOT
772 rob->squash(bdelay_done_seq_num, tid);
773 toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot;
774 toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num;
775#else
776 rob->squash(squashed_inst, tid);
777 toIEW->commitInfo[tid].squashDelaySlot = true;
778#endif
779 changedROBNumEntries[tid] = true;
780
781 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
782
783 toIEW->commitInfo[tid].squash = true;
784
785 // Send back the rob squashing signal so other stages know that
786 // the ROB is in the process of squashing.
787 toIEW->commitInfo[tid].robSquashing = true;
788
789 toIEW->commitInfo[tid].branchMispredict =
790 fromIEW->branchMispredict[tid];
791
792 toIEW->commitInfo[tid].branchTaken =
793 fromIEW->branchTaken[tid];
794
795 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
| 741 }
742#endif
743
744 if (fromIEW->includeSquashInst[tid] == true) {
745 squashed_inst--;
746#if ISA_HAS_DELAY_SLOT
747 bdelay_done_seq_num--;
748#endif
749 }
750 // All younger instructions will be squashed. Set the sequence
751 // number as the youngest instruction in the ROB.
752 youngestSeqNum[tid] = squashed_inst;
753
754#if ISA_HAS_DELAY_SLOT
755 rob->squash(bdelay_done_seq_num, tid);
756 toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot;
757 toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num;
758#else
759 rob->squash(squashed_inst, tid);
760 toIEW->commitInfo[tid].squashDelaySlot = true;
761#endif
762 changedROBNumEntries[tid] = true;
763
764 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
765
766 toIEW->commitInfo[tid].squash = true;
767
768 // Send back the rob squashing signal so other stages know that
769 // the ROB is in the process of squashing.
770 toIEW->commitInfo[tid].robSquashing = true;
771
772 toIEW->commitInfo[tid].branchMispredict =
773 fromIEW->branchMispredict[tid];
774
775 toIEW->commitInfo[tid].branchTaken =
776 fromIEW->branchTaken[tid];
777
778 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
|
| 779 toIEW->commitInfo[tid].nextNPC = fromIEW->nextNPC[tid];
|
796
797 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
798
799 if (toIEW->commitInfo[tid].branchMispredict) {
800 ++branchMispredicts;
801 }
802 }
803
804 }
805
806 setNextStatus();
807
808 if (squashCounter != numThreads) {
809 // If we're not currently squashing, then get instructions.
810 getInsts();
811
812 // Try to commit any instructions.
813 commitInsts();
814 } else {
815#if ISA_HAS_DELAY_SLOT
816 skidInsert();
817#endif
818 }
819
820 //Check for any activity
| 780
781 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
782
783 if (toIEW->commitInfo[tid].branchMispredict) {
784 ++branchMispredicts;
785 }
786 }
787
788 }
789
790 setNextStatus();
791
792 if (squashCounter != numThreads) {
793 // If we're not currently squashing, then get instructions.
794 getInsts();
795
796 // Try to commit any instructions.
797 commitInsts();
798 } else {
799#if ISA_HAS_DELAY_SLOT
800 skidInsert();
801#endif
802 }
803
804 //Check for any activity
|
821 threads = activeThreads->begin();
| 805 threads = (*activeThreads).begin();
|
822
| 806
|
823 while (threads != end) {
| 807 while (threads != (*activeThreads).end()) {
|
824 unsigned tid = *threads++;
825
826 if (changedROBNumEntries[tid]) {
827 toIEW->commitInfo[tid].usedROB = true;
828 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
829
830 if (rob->isEmpty(tid)) {
831 toIEW->commitInfo[tid].emptyROB = true;
832 }
833
834 wroteToTimeBuffer = true;
835 changedROBNumEntries[tid] = false;
836 }
837 }
838}
839
840template <class Impl>
841void
842DefaultCommit<Impl>::commitInsts()
843{
844 ////////////////////////////////////
845 // Handle commit
846 // Note that commit will be handled prior to putting new
847 // instructions in the ROB so that the ROB only tries to commit
848 // instructions it has in this current cycle, and not instructions
849 // it is writing in during this cycle. Can't commit and squash
850 // things at the same time...
851 ////////////////////////////////////
852
853 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
854
855 unsigned num_committed = 0;
856
857 DynInstPtr head_inst;
858
859 // Commit as many instructions as possible until the commit bandwidth
860 // limit is reached, or it becomes impossible to commit any more.
861 while (num_committed < commitWidth) {
862 int commit_thread = getCommittingThread();
863
864 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
865 break;
866
867 head_inst = rob->readHeadInst(commit_thread);
868
869 int tid = head_inst->threadNumber;
870
871 assert(tid == commit_thread);
872
873 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
874 head_inst->seqNum, tid);
875
876 // If the head instruction is squashed, it is ready to retire
877 // (be removed from the ROB) at any time.
878 if (head_inst->isSquashed()) {
879
880 DPRINTF(Commit, "Retiring squashed instruction from "
881 "ROB.\n");
882
883 rob->retireHead(commit_thread);
884
885 ++commitSquashedInsts;
886
887 // Record that the number of ROB entries has changed.
888 changedROBNumEntries[tid] = true;
889 } else {
890 PC[tid] = head_inst->readPC();
891 nextPC[tid] = head_inst->readNextPC();
892 nextNPC[tid] = head_inst->readNextNPC();
893
894 // Increment the total number of non-speculative instructions
895 // executed.
896 // Hack for now: it really shouldn't happen until after the
897 // commit is deemed to be successful, but this count is needed
898 // for syscalls.
899 thread[tid]->funcExeInst++;
900
901 // Try to commit the head instruction.
902 bool commit_success = commitHead(head_inst, num_committed);
903
904 if (commit_success) {
905 ++num_committed;
906
907 changedROBNumEntries[tid] = true;
908
909 // Set the doneSeqNum to the youngest committed instruction.
910 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
911
912 ++commitCommittedInsts;
913
914 // To match the old model, don't count nops and instruction
915 // prefetches towards the total commit count.
916 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
917 cpu->instDone(tid);
918 }
919
920 PC[tid] = nextPC[tid];
921#if ISA_HAS_DELAY_SLOT
922 nextPC[tid] = nextNPC[tid];
923 nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
924#else
925 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
926#endif
927
928#if FULL_SYSTEM
929 int count = 0;
930 Addr oldpc;
931 do {
932 // Debug statement. Checks to make sure we're not
933 // currently updating state while handling PC events.
934 if (count == 0)
935 assert(!thread[tid]->inSyscall &&
936 !thread[tid]->trapPending);
937 oldpc = PC[tid];
938 cpu->system->pcEventQueue.service(
939 thread[tid]->getTC());
940 count++;
941 } while (oldpc != PC[tid]);
942 if (count > 1) {
943 DPRINTF(Commit, "PC skip function event, stopping commit\n");
944 break;
945 }
946#endif
947 } else {
948 DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
949 "[tid:%i] [sn:%i].\n",
950 head_inst->readPC(), tid ,head_inst->seqNum);
951 break;
952 }
953 }
954 }
955
956 DPRINTF(CommitRate, "%i\n", num_committed);
957 numCommittedDist.sample(num_committed);
958
959 if (num_committed == commitWidth) {
960 commitEligibleSamples++;
961 }
962}
963
964template <class Impl>
965bool
966DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
967{
968 assert(head_inst);
969
970 int tid = head_inst->threadNumber;
971
972 // If the instruction is not executed yet, then it will need extra
973 // handling. Signal backwards that it should be executed.
974 if (!head_inst->isExecuted()) {
975 // Keep this number correct. We have not yet actually executed
976 // and committed this instruction.
977 thread[tid]->funcExeInst--;
978
979 head_inst->setAtCommit();
980
981 if (head_inst->isNonSpeculative() ||
982 head_inst->isStoreConditional() ||
983 head_inst->isMemBarrier() ||
984 head_inst->isWriteBarrier()) {
985
986 DPRINTF(Commit, "Encountered a barrier or non-speculative "
987 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
988 head_inst->seqNum, head_inst->readPC());
989
| 808 unsigned tid = *threads++;
809
810 if (changedROBNumEntries[tid]) {
811 toIEW->commitInfo[tid].usedROB = true;
812 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
813
814 if (rob->isEmpty(tid)) {
815 toIEW->commitInfo[tid].emptyROB = true;
816 }
817
818 wroteToTimeBuffer = true;
819 changedROBNumEntries[tid] = false;
820 }
821 }
822}
823
824template <class Impl>
825void
826DefaultCommit<Impl>::commitInsts()
827{
828 ////////////////////////////////////
829 // Handle commit
830 // Note that commit will be handled prior to putting new
831 // instructions in the ROB so that the ROB only tries to commit
832 // instructions it has in this current cycle, and not instructions
833 // it is writing in during this cycle. Can't commit and squash
834 // things at the same time...
835 ////////////////////////////////////
836
837 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
838
839 unsigned num_committed = 0;
840
841 DynInstPtr head_inst;
842
843 // Commit as many instructions as possible until the commit bandwidth
844 // limit is reached, or it becomes impossible to commit any more.
845 while (num_committed < commitWidth) {
846 int commit_thread = getCommittingThread();
847
848 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
849 break;
850
851 head_inst = rob->readHeadInst(commit_thread);
852
853 int tid = head_inst->threadNumber;
854
855 assert(tid == commit_thread);
856
857 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
858 head_inst->seqNum, tid);
859
860 // If the head instruction is squashed, it is ready to retire
861 // (be removed from the ROB) at any time.
862 if (head_inst->isSquashed()) {
863
864 DPRINTF(Commit, "Retiring squashed instruction from "
865 "ROB.\n");
866
867 rob->retireHead(commit_thread);
868
869 ++commitSquashedInsts;
870
871 // Record that the number of ROB entries has changed.
872 changedROBNumEntries[tid] = true;
873 } else {
874 PC[tid] = head_inst->readPC();
875 nextPC[tid] = head_inst->readNextPC();
876 nextNPC[tid] = head_inst->readNextNPC();
877
878 // Increment the total number of non-speculative instructions
879 // executed.
880 // Hack for now: it really shouldn't happen until after the
881 // commit is deemed to be successful, but this count is needed
882 // for syscalls.
883 thread[tid]->funcExeInst++;
884
885 // Try to commit the head instruction.
886 bool commit_success = commitHead(head_inst, num_committed);
887
888 if (commit_success) {
889 ++num_committed;
890
891 changedROBNumEntries[tid] = true;
892
893 // Set the doneSeqNum to the youngest committed instruction.
894 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
895
896 ++commitCommittedInsts;
897
898 // To match the old model, don't count nops and instruction
899 // prefetches towards the total commit count.
900 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
901 cpu->instDone(tid);
902 }
903
904 PC[tid] = nextPC[tid];
905#if ISA_HAS_DELAY_SLOT
906 nextPC[tid] = nextNPC[tid];
907 nextNPC[tid] = nextNPC[tid] + sizeof(TheISA::MachInst);
908#else
909 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
910#endif
911
912#if FULL_SYSTEM
913 int count = 0;
914 Addr oldpc;
915 do {
916 // Debug statement. Checks to make sure we're not
917 // currently updating state while handling PC events.
918 if (count == 0)
919 assert(!thread[tid]->inSyscall &&
920 !thread[tid]->trapPending);
921 oldpc = PC[tid];
922 cpu->system->pcEventQueue.service(
923 thread[tid]->getTC());
924 count++;
925 } while (oldpc != PC[tid]);
926 if (count > 1) {
927 DPRINTF(Commit, "PC skip function event, stopping commit\n");
928 break;
929 }
930#endif
931 } else {
932 DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
933 "[tid:%i] [sn:%i].\n",
934 head_inst->readPC(), tid ,head_inst->seqNum);
935 break;
936 }
937 }
938 }
939
940 DPRINTF(CommitRate, "%i\n", num_committed);
941 numCommittedDist.sample(num_committed);
942
943 if (num_committed == commitWidth) {
944 commitEligibleSamples++;
945 }
946}
947
948template <class Impl>
949bool
950DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
951{
952 assert(head_inst);
953
954 int tid = head_inst->threadNumber;
955
956 // If the instruction is not executed yet, then it will need extra
957 // handling. Signal backwards that it should be executed.
958 if (!head_inst->isExecuted()) {
959 // Keep this number correct. We have not yet actually executed
960 // and committed this instruction.
961 thread[tid]->funcExeInst--;
962
963 head_inst->setAtCommit();
964
965 if (head_inst->isNonSpeculative() ||
966 head_inst->isStoreConditional() ||
967 head_inst->isMemBarrier() ||
968 head_inst->isWriteBarrier()) {
969
970 DPRINTF(Commit, "Encountered a barrier or non-speculative "
971 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
972 head_inst->seqNum, head_inst->readPC());
973
|
| 974#if !FULL_SYSTEM
|
990 // Hack to make sure syscalls/memory barriers/quiesces
991 // aren't executed until all stores write back their data.
992 // This direct communication shouldn't be used for
993 // anything other than this.
| 975 // Hack to make sure syscalls/memory barriers/quiesces
976 // aren't executed until all stores write back their data.
977 // This direct communication shouldn't be used for
978 // anything other than this.
|
| 979 if (inst_num > 0 || iewStage->hasStoresToWB())
980#else
|
994 if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
995 head_inst->isQuiesce()) &&
996 iewStage->hasStoresToWB())
| 981 if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
982 head_inst->isQuiesce()) &&
983 iewStage->hasStoresToWB())
|
| 984#endif
|
997 {
998 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
999 return false;
| 985 {
986 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
987 return false;
|
1000 } else if (inst_num > 0 || iewStage->hasStoresToWB()) {
1001 DPRINTF(Commit, "Waiting to become head of commit.\n");
1002 return false;
| |
1003 }
1004
1005 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1006
1007 // Change the instruction so it won't try to commit again until
1008 // it is executed.
1009 head_inst->clearCanCommit();
1010
1011 ++commitNonSpecStalls;
1012
1013 return false;
1014 } else if (head_inst->isLoad()) {
1015 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
1016 head_inst->seqNum, head_inst->readPC());
1017
1018 // Send back the non-speculative instruction's sequence
1019 // number. Tell the lsq to re-execute the load.
1020 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1021 toIEW->commitInfo[tid].uncached = true;
1022 toIEW->commitInfo[tid].uncachedLoad = head_inst;
1023
1024 head_inst->clearCanCommit();
1025
1026 return false;
1027 } else {
1028 panic("Trying to commit un-executed instruction "
1029 "of unknown type!\n");
1030 }
1031 }
1032
1033 if (head_inst->isThreadSync()) {
1034 // Not handled for now.
1035 panic("Thread sync instructions are not handled yet.\n");
1036 }
1037
1038 // Stores mark themselves as completed.
1039 if (!head_inst->isStore()) {
1040 head_inst->setCompleted();
1041 }
1042
1043#if USE_CHECKER
1044 // Use checker prior to updating anything due to traps or PC
1045 // based events.
1046 if (cpu->checker) {
1047 cpu->checker->verify(head_inst);
1048 }
1049#endif
1050
1051 // Check if the instruction caused a fault. If so, trap.
1052 Fault inst_fault = head_inst->getFault();
1053
1054 // DTB will sometimes need the machine instruction for when
1055 // faults happen. So we will set it here, prior to the DTB
1056 // possibly needing it for its fault.
1057 thread[tid]->setInst(
1058 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1059
1060 if (inst_fault != NoFault) {
1061 head_inst->setCompleted();
1062 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1063 head_inst->seqNum, head_inst->readPC());
1064
1065 if (iewStage->hasStoresToWB() || inst_num > 0) {
1066 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1067 return false;
1068 }
1069
1070#if USE_CHECKER
1071 if (cpu->checker && head_inst->isStore()) {
1072 cpu->checker->verify(head_inst);
1073 }
1074#endif
1075
1076 assert(!thread[tid]->inSyscall);
1077
1078 // Mark that we're in state update mode so that the trap's
1079 // execution doesn't generate extra squashes.
1080 thread[tid]->inSyscall = true;
1081
1082 // Execute the trap. Although it's slightly unrealistic in
1083 // terms of timing (as it doesn't wait for the full timing of
1084 // the trap event to complete before updating state), it's
1085 // needed to update the state as soon as possible. This
1086 // prevents external agents from changing any specific state
1087 // that the trap need.
1088 cpu->trap(inst_fault, tid);
1089
1090 // Exit state update mode to avoid accidental updating.
1091 thread[tid]->inSyscall = false;
1092
1093 commitStatus[tid] = TrapPending;
1094
1095 // Generate trap squash event.
1096 generateTrapEvent(tid);
1097// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC());
1098 return false;
1099 }
1100
1101 updateComInstStats(head_inst);
1102
1103#if FULL_SYSTEM
1104 if (thread[tid]->profile) {
1105// bool usermode = TheISA::inUserMode(thread[tid]->getTC());
1106// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC();
1107 thread[tid]->profilePC = head_inst->readPC();
1108 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1109 head_inst->staticInst);
1110
1111 if (node)
1112 thread[tid]->profileNode = node;
1113 }
1114#endif
1115
1116 if (head_inst->traceData) {
1117 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1118 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1119 head_inst->traceData->finalize();
1120 head_inst->traceData = NULL;
1121 }
1122
1123 // Update the commit rename map
1124 for (int i = 0; i < head_inst->numDestRegs(); i++) {
| 988 }
989
990 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
991
992 // Change the instruction so it won't try to commit again until
993 // it is executed.
994 head_inst->clearCanCommit();
995
996 ++commitNonSpecStalls;
997
998 return false;
999 } else if (head_inst->isLoad()) {
1000 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
1001 head_inst->seqNum, head_inst->readPC());
1002
1003 // Send back the non-speculative instruction's sequence
1004 // number. Tell the lsq to re-execute the load.
1005 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1006 toIEW->commitInfo[tid].uncached = true;
1007 toIEW->commitInfo[tid].uncachedLoad = head_inst;
1008
1009 head_inst->clearCanCommit();
1010
1011 return false;
1012 } else {
1013 panic("Trying to commit un-executed instruction "
1014 "of unknown type!\n");
1015 }
1016 }
1017
1018 if (head_inst->isThreadSync()) {
1019 // Not handled for now.
1020 panic("Thread sync instructions are not handled yet.\n");
1021 }
1022
1023 // Stores mark themselves as completed.
1024 if (!head_inst->isStore()) {
1025 head_inst->setCompleted();
1026 }
1027
1028#if USE_CHECKER
1029 // Use checker prior to updating anything due to traps or PC
1030 // based events.
1031 if (cpu->checker) {
1032 cpu->checker->verify(head_inst);
1033 }
1034#endif
1035
1036 // Check if the instruction caused a fault. If so, trap.
1037 Fault inst_fault = head_inst->getFault();
1038
1039 // DTB will sometimes need the machine instruction for when
1040 // faults happen. So we will set it here, prior to the DTB
1041 // possibly needing it for its fault.
1042 thread[tid]->setInst(
1043 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1044
1045 if (inst_fault != NoFault) {
1046 head_inst->setCompleted();
1047 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1048 head_inst->seqNum, head_inst->readPC());
1049
1050 if (iewStage->hasStoresToWB() || inst_num > 0) {
1051 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1052 return false;
1053 }
1054
1055#if USE_CHECKER
1056 if (cpu->checker && head_inst->isStore()) {
1057 cpu->checker->verify(head_inst);
1058 }
1059#endif
1060
1061 assert(!thread[tid]->inSyscall);
1062
1063 // Mark that we're in state update mode so that the trap's
1064 // execution doesn't generate extra squashes.
1065 thread[tid]->inSyscall = true;
1066
1067 // Execute the trap. Although it's slightly unrealistic in
1068 // terms of timing (as it doesn't wait for the full timing of
1069 // the trap event to complete before updating state), it's
1070 // needed to update the state as soon as possible. This
1071 // prevents external agents from changing any specific state
1072 // that the trap need.
1073 cpu->trap(inst_fault, tid);
1074
1075 // Exit state update mode to avoid accidental updating.
1076 thread[tid]->inSyscall = false;
1077
1078 commitStatus[tid] = TrapPending;
1079
1080 // Generate trap squash event.
1081 generateTrapEvent(tid);
1082// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC());
1083 return false;
1084 }
1085
1086 updateComInstStats(head_inst);
1087
1088#if FULL_SYSTEM
1089 if (thread[tid]->profile) {
1090// bool usermode = TheISA::inUserMode(thread[tid]->getTC());
1091// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC();
1092 thread[tid]->profilePC = head_inst->readPC();
1093 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1094 head_inst->staticInst);
1095
1096 if (node)
1097 thread[tid]->profileNode = node;
1098 }
1099#endif
1100
1101 if (head_inst->traceData) {
1102 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1103 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1104 head_inst->traceData->finalize();
1105 head_inst->traceData = NULL;
1106 }
1107
1108 // Update the commit rename map
1109 for (int i = 0; i < head_inst->numDestRegs(); i++) {
|
1125 renameMap[tid]->setEntry(head_inst->destRegIdx(i),
| 1110 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
|
1126 head_inst->renamedDestRegIdx(i));
1127 }
1128
1129 if (head_inst->isCopy())
1130 panic("Should not commit any copy instructions!");
1131
1132 // Finally clear the head ROB entry.
1133 rob->retireHead(tid);
1134
1135 // Return true to indicate that we have committed an instruction.
1136 return true;
1137}
1138
1139template <class Impl>
1140void
1141DefaultCommit<Impl>::getInsts()
1142{
1143 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1144
1145#if ISA_HAS_DELAY_SLOT
1146 // Read any renamed instructions and place them into the ROB.
1147 int insts_to_process = std::min((int)renameWidth,
1148 (int)(fromRename->size + skidBuffer.size()));
1149 int rename_idx = 0;
1150
1151 DPRINTF(Commit, "%i insts available to process. Rename Insts:%i "
1152 "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size,
1153 skidBuffer.size());
1154#else
1155 // Read any renamed instructions and place them into the ROB.
1156 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1157#endif
1158
1159
1160 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1161 DynInstPtr inst;
1162
1163#if ISA_HAS_DELAY_SLOT
1164 // Get insts from skidBuffer or from Rename
1165 if (skidBuffer.size() > 0) {
1166 DPRINTF(Commit, "Grabbing skidbuffer inst.\n");
1167 inst = skidBuffer.front();
1168 skidBuffer.pop();
1169 } else {
1170 DPRINTF(Commit, "Grabbing rename inst.\n");
1171 inst = fromRename->insts[rename_idx++];
1172 }
1173#else
1174 inst = fromRename->insts[inst_num];
1175#endif
1176 int tid = inst->threadNumber;
1177
1178 if (!inst->isSquashed() &&
1179 commitStatus[tid] != ROBSquashing) {
1180 changedROBNumEntries[tid] = true;
1181
1182 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1183 inst->readPC(), inst->seqNum, tid);
1184
1185 rob->insertInst(inst);
1186
1187 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1188
1189 youngestSeqNum[tid] = inst->seqNum;
1190 } else {
1191 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1192 "squashed, skipping.\n",
1193 inst->readPC(), inst->seqNum, tid);
1194 }
1195 }
1196
1197#if ISA_HAS_DELAY_SLOT
1198 if (rename_idx < fromRename->size) {
1199 DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n");
1200
1201 for (;
1202 rename_idx < fromRename->size;
1203 rename_idx++) {
1204 DynInstPtr inst = fromRename->insts[rename_idx];
1205
1206 if (!inst->isSquashed()) {
1207 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1208 "skidBuffer.\n", inst->readPC(), inst->seqNum,
1209 inst->threadNumber);
1210 skidBuffer.push(inst);
1211 } else {
1212 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1213 "squashed, skipping.\n",
1214 inst->readPC(), inst->seqNum, inst->threadNumber);
1215 }
1216 }
1217 }
1218#endif
1219
1220}
1221
1222template <class Impl>
1223void
1224DefaultCommit<Impl>::skidInsert()
1225{
1226 DPRINTF(Commit, "Attempting to any instructions from rename into "
1227 "skidBuffer.\n");
1228
1229 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1230 DynInstPtr inst = fromRename->insts[inst_num];
1231
1232 if (!inst->isSquashed()) {
1233 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1234 "skidBuffer.\n", inst->readPC(), inst->seqNum,
1235 inst->threadNumber);
1236 skidBuffer.push(inst);
1237 } else {
1238 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1239 "squashed, skipping.\n",
1240 inst->readPC(), inst->seqNum, inst->threadNumber);
1241 }
1242 }
1243}
1244
1245template <class Impl>
1246void
1247DefaultCommit<Impl>::markCompletedInsts()
1248{
1249 // Grab completed insts out of the IEW instruction queue, and mark
1250 // instructions completed within the ROB.
1251 for (int inst_num = 0;
1252 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1253 ++inst_num)
1254 {
1255 if (!fromIEW->insts[inst_num]->isSquashed()) {
1256 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1257 "within ROB.\n",
1258 fromIEW->insts[inst_num]->threadNumber,
1259 fromIEW->insts[inst_num]->readPC(),
1260 fromIEW->insts[inst_num]->seqNum);
1261
1262 // Mark the instruction as ready to commit.
1263 fromIEW->insts[inst_num]->setCanCommit();
1264 }
1265 }
1266}
1267
1268template <class Impl>
1269bool
1270DefaultCommit<Impl>::robDoneSquashing()
1271{
| 1111 head_inst->renamedDestRegIdx(i));
1112 }
1113
1114 if (head_inst->isCopy())
1115 panic("Should not commit any copy instructions!");
1116
1117 // Finally clear the head ROB entry.
1118 rob->retireHead(tid);
1119
1120 // Return true to indicate that we have committed an instruction.
1121 return true;
1122}
1123
1124template <class Impl>
1125void
1126DefaultCommit<Impl>::getInsts()
1127{
1128 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1129
1130#if ISA_HAS_DELAY_SLOT
1131 // Read any renamed instructions and place them into the ROB.
1132 int insts_to_process = std::min((int)renameWidth,
1133 (int)(fromRename->size + skidBuffer.size()));
1134 int rename_idx = 0;
1135
1136 DPRINTF(Commit, "%i insts available to process. Rename Insts:%i "
1137 "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size,
1138 skidBuffer.size());
1139#else
1140 // Read any renamed instructions and place them into the ROB.
1141 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1142#endif
1143
1144
1145 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1146 DynInstPtr inst;
1147
1148#if ISA_HAS_DELAY_SLOT
1149 // Get insts from skidBuffer or from Rename
1150 if (skidBuffer.size() > 0) {
1151 DPRINTF(Commit, "Grabbing skidbuffer inst.\n");
1152 inst = skidBuffer.front();
1153 skidBuffer.pop();
1154 } else {
1155 DPRINTF(Commit, "Grabbing rename inst.\n");
1156 inst = fromRename->insts[rename_idx++];
1157 }
1158#else
1159 inst = fromRename->insts[inst_num];
1160#endif
1161 int tid = inst->threadNumber;
1162
1163 if (!inst->isSquashed() &&
1164 commitStatus[tid] != ROBSquashing) {
1165 changedROBNumEntries[tid] = true;
1166
1167 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1168 inst->readPC(), inst->seqNum, tid);
1169
1170 rob->insertInst(inst);
1171
1172 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1173
1174 youngestSeqNum[tid] = inst->seqNum;
1175 } else {
1176 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1177 "squashed, skipping.\n",
1178 inst->readPC(), inst->seqNum, tid);
1179 }
1180 }
1181
1182#if ISA_HAS_DELAY_SLOT
1183 if (rename_idx < fromRename->size) {
1184 DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n");
1185
1186 for (;
1187 rename_idx < fromRename->size;
1188 rename_idx++) {
1189 DynInstPtr inst = fromRename->insts[rename_idx];
1190
1191 if (!inst->isSquashed()) {
1192 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1193 "skidBuffer.\n", inst->readPC(), inst->seqNum,
1194 inst->threadNumber);
1195 skidBuffer.push(inst);
1196 } else {
1197 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1198 "squashed, skipping.\n",
1199 inst->readPC(), inst->seqNum, inst->threadNumber);
1200 }
1201 }
1202 }
1203#endif
1204
1205}
1206
1207template <class Impl>
1208void
1209DefaultCommit<Impl>::skidInsert()
1210{
1211 DPRINTF(Commit, "Attempting to any instructions from rename into "
1212 "skidBuffer.\n");
1213
1214 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1215 DynInstPtr inst = fromRename->insts[inst_num];
1216
1217 if (!inst->isSquashed()) {
1218 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ",
1219 "skidBuffer.\n", inst->readPC(), inst->seqNum,
1220 inst->threadNumber);
1221 skidBuffer.push(inst);
1222 } else {
1223 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1224 "squashed, skipping.\n",
1225 inst->readPC(), inst->seqNum, inst->threadNumber);
1226 }
1227 }
1228}
1229
1230template <class Impl>
1231void
1232DefaultCommit<Impl>::markCompletedInsts()
1233{
1234 // Grab completed insts out of the IEW instruction queue, and mark
1235 // instructions completed within the ROB.
1236 for (int inst_num = 0;
1237 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1238 ++inst_num)
1239 {
1240 if (!fromIEW->insts[inst_num]->isSquashed()) {
1241 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1242 "within ROB.\n",
1243 fromIEW->insts[inst_num]->threadNumber,
1244 fromIEW->insts[inst_num]->readPC(),
1245 fromIEW->insts[inst_num]->seqNum);
1246
1247 // Mark the instruction as ready to commit.
1248 fromIEW->insts[inst_num]->setCanCommit();
1249 }
1250 }
1251}
1252
1253template <class Impl>
1254bool
1255DefaultCommit<Impl>::robDoneSquashing()
1256{
|
1272 std::list<unsigned>::iterator threads = activeThreads->begin();
1273 std::list<unsigned>::iterator end = activeThreads->end();
| 1257 std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
1274
| 1258
|
1275 while (threads != end) {
| 1259 while (threads != (*activeThreads).end()) {
|
1276 unsigned tid = *threads++;
1277
1278 if (!rob->isDoneSquashing(tid))
1279 return false;
1280 }
1281
1282 return true;
1283}
1284
1285template <class Impl>
1286void
1287DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1288{
1289 unsigned thread = inst->threadNumber;
1290
1291 //
1292 // Pick off the software prefetches
1293 //
1294#ifdef TARGET_ALPHA
1295 if (inst->isDataPrefetch()) {
1296 statComSwp[thread]++;
1297 } else {
1298 statComInst[thread]++;
1299 }
1300#else
1301 statComInst[thread]++;
1302#endif
1303
1304 //
1305 // Control Instructions
1306 //
1307 if (inst->isControl())
1308 statComBranches[thread]++;
1309
1310 //
1311 // Memory references
1312 //
1313 if (inst->isMemRef()) {
1314 statComRefs[thread]++;
1315
1316 if (inst->isLoad()) {
1317 statComLoads[thread]++;
1318 }
1319 }
1320
1321 if (inst->isMemBarrier()) {
1322 statComMembars[thread]++;
1323 }
1324}
1325
1326////////////////////////////////////////
1327// //
1328// SMT COMMIT POLICY MAINTAINED HERE //
1329// //
1330////////////////////////////////////////
1331template <class Impl>
1332int
1333DefaultCommit<Impl>::getCommittingThread()
1334{
1335 if (numThreads > 1) {
1336 switch (commitPolicy) {
1337
1338 case Aggressive:
1339 //If Policy is Aggressive, commit will call
1340 //this function multiple times per
1341 //cycle
1342 return oldestReady();
1343
1344 case RoundRobin:
1345 return roundRobin();
1346
1347 case OldestReady:
1348 return oldestReady();
1349
1350 default:
1351 return -1;
1352 }
1353 } else {
| 1260 unsigned tid = *threads++;
1261
1262 if (!rob->isDoneSquashing(tid))
1263 return false;
1264 }
1265
1266 return true;
1267}
1268
1269template <class Impl>
1270void
1271DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1272{
1273 unsigned thread = inst->threadNumber;
1274
1275 //
1276 // Pick off the software prefetches
1277 //
1278#ifdef TARGET_ALPHA
1279 if (inst->isDataPrefetch()) {
1280 statComSwp[thread]++;
1281 } else {
1282 statComInst[thread]++;
1283 }
1284#else
1285 statComInst[thread]++;
1286#endif
1287
1288 //
1289 // Control Instructions
1290 //
1291 if (inst->isControl())
1292 statComBranches[thread]++;
1293
1294 //
1295 // Memory references
1296 //
1297 if (inst->isMemRef()) {
1298 statComRefs[thread]++;
1299
1300 if (inst->isLoad()) {
1301 statComLoads[thread]++;
1302 }
1303 }
1304
1305 if (inst->isMemBarrier()) {
1306 statComMembars[thread]++;
1307 }
1308}
1309
1310////////////////////////////////////////
1311// //
1312// SMT COMMIT POLICY MAINTAINED HERE //
1313// //
1314////////////////////////////////////////
1315template <class Impl>
1316int
1317DefaultCommit<Impl>::getCommittingThread()
1318{
1319 if (numThreads > 1) {
1320 switch (commitPolicy) {
1321
1322 case Aggressive:
1323 //If Policy is Aggressive, commit will call
1324 //this function multiple times per
1325 //cycle
1326 return oldestReady();
1327
1328 case RoundRobin:
1329 return roundRobin();
1330
1331 case OldestReady:
1332 return oldestReady();
1333
1334 default:
1335 return -1;
1336 }
1337 } else {
|
1354 assert(!activeThreads->empty());
1355 int tid = activeThreads->front();
| 1338 int tid = (*activeThreads).front();
|
1356
1357 if (commitStatus[tid] == Running ||
1358 commitStatus[tid] == Idle ||
1359 commitStatus[tid] == FetchTrapPending) {
1360 return tid;
1361 } else {
1362 return -1;
1363 }
1364 }
1365}
1366
1367template<class Impl>
1368int
1369DefaultCommit<Impl>::roundRobin()
1370{
1371 std::list<unsigned>::iterator pri_iter = priority_list.begin();
1372 std::list<unsigned>::iterator end = priority_list.end();
1373
1374 while (pri_iter != end) {
1375 unsigned tid = *pri_iter;
1376
1377 if (commitStatus[tid] == Running ||
1378 commitStatus[tid] == Idle ||
1379 commitStatus[tid] == FetchTrapPending) {
1380
1381 if (rob->isHeadReady(tid)) {
1382 priority_list.erase(pri_iter);
1383 priority_list.push_back(tid);
1384
1385 return tid;
1386 }
1387 }
1388
1389 pri_iter++;
1390 }
1391
1392 return -1;
1393}
1394
1395template<class Impl>
1396int
1397DefaultCommit<Impl>::oldestReady()
1398{
1399 unsigned oldest = 0;
1400 bool first = true;
1401
| 1339
1340 if (commitStatus[tid] == Running ||
1341 commitStatus[tid] == Idle ||
1342 commitStatus[tid] == FetchTrapPending) {
1343 return tid;
1344 } else {
1345 return -1;
1346 }
1347 }
1348}
1349
1350template<class Impl>
1351int
1352DefaultCommit<Impl>::roundRobin()
1353{
1354 std::list<unsigned>::iterator pri_iter = priority_list.begin();
1355 std::list<unsigned>::iterator end = priority_list.end();
1356
1357 while (pri_iter != end) {
1358 unsigned tid = *pri_iter;
1359
1360 if (commitStatus[tid] == Running ||
1361 commitStatus[tid] == Idle ||
1362 commitStatus[tid] == FetchTrapPending) {
1363
1364 if (rob->isHeadReady(tid)) {
1365 priority_list.erase(pri_iter);
1366 priority_list.push_back(tid);
1367
1368 return tid;
1369 }
1370 }
1371
1372 pri_iter++;
1373 }
1374
1375 return -1;
1376}
1377
1378template<class Impl>
1379int
1380DefaultCommit<Impl>::oldestReady()
1381{
1382 unsigned oldest = 0;
1383 bool first = true;
1384
|
1402 std::list<unsigned>::iterator threads = activeThreads->begin();
1403 std::list<unsigned>::iterator end = activeThreads->end();
| 1385 std::list<unsigned>::iterator threads = (*activeThreads).begin();
|
1404
| 1386
|
1405 while (threads != end) {
| 1387 while (threads != (*activeThreads).end()) {
|
1406 unsigned tid = *threads++;
1407
1408 if (!rob->isEmpty(tid) &&
1409 (commitStatus[tid] == Running ||
1410 commitStatus[tid] == Idle ||
1411 commitStatus[tid] == FetchTrapPending)) {
1412
1413 if (rob->isHeadReady(tid)) {
1414
1415 DynInstPtr head_inst = rob->readHeadInst(tid);
1416
1417 if (first) {
1418 oldest = tid;
1419 first = false;
1420 } else if (head_inst->seqNum < oldest) {
1421 oldest = tid;
1422 }
1423 }
1424 }
1425 }
1426
1427 if (!first) {
1428 return oldest;
1429 } else {
1430 return -1;
1431 }
1432}
| 1388 unsigned tid = *threads++;
1389
1390 if (!rob->isEmpty(tid) &&
1391 (commitStatus[tid] == Running ||
1392 commitStatus[tid] == Idle ||
1393 commitStatus[tid] == FetchTrapPending)) {
1394
1395 if (rob->isHeadReady(tid)) {
1396
1397 DynInstPtr head_inst = rob->readHeadInst(tid);
1398
1399 if (first) {
1400 oldest = tid;
1401 first = false;
1402 } else if (head_inst->seqNum < oldest) {
1403 oldest = tid;
1404 }
1405 }
1406 }
1407 }
1408
1409 if (!first) {
1410 return oldest;
1411 } else {
1412 return -1;
1413 }
1414}
|