commit_impl.hh (4405:57af43e114b5) | commit_impl.hh (4632:be5b8f67b8fb) |
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1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 627 unchanged lines hidden (view full) --- 636 if (interrupt != NoFault) { 637 // Wait until the ROB is empty and all stores have drained in 638 // order to enter the interrupt. 639 if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 640 // Squash or record that I need to squash this cycle if 641 // an interrupt needed to be handled. 642 DPRINTF(Commit, "Interrupt detected.\n"); 643 | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 627 unchanged lines hidden (view full) --- 636 if (interrupt != NoFault) { 637 // Wait until the ROB is empty and all stores have drained in 638 // order to enter the interrupt. 639 if (rob->isEmpty() && !iewStage->hasStoresToWB()) { 640 // Squash or record that I need to squash this cycle if 641 // an interrupt needed to be handled. 642 DPRINTF(Commit, "Interrupt detected.\n"); 643 |
644 Fault new_interrupt = cpu->getInterrupts(); 645 assert(new_interrupt != NoFault); 646 |
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644 // Clear the interrupt now that it's going to be handled 645 toIEW->commitInfo[0].clearInterrupt = true; 646 647 assert(!thread[0]->inSyscall); 648 thread[0]->inSyscall = true; 649 650 // CPU will handle interrupt. 651 cpu->processInterrupts(interrupt); --- 81 unchanged lines hidden (view full) --- 733 fromIEW->nextPC[tid]); 734 735 commitStatus[tid] = ROBSquashing; 736 737 // If we want to include the squashing instruction in the squash, 738 // then use one older sequence number. 739 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 740 | 647 // Clear the interrupt now that it's going to be handled 648 toIEW->commitInfo[0].clearInterrupt = true; 649 650 assert(!thread[0]->inSyscall); 651 thread[0]->inSyscall = true; 652 653 // CPU will handle interrupt. 654 cpu->processInterrupts(interrupt); --- 81 unchanged lines hidden (view full) --- 736 fromIEW->nextPC[tid]); 737 738 commitStatus[tid] = ROBSquashing; 739 740 // If we want to include the squashing instruction in the squash, 741 // then use one older sequence number. 742 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; 743 |
741#if ISA_HAS_DELAY_SLOT 742 InstSeqNum bdelay_done_seq_num = squashed_inst; 743 bool squash_bdelay_slot = fromIEW->squashDelaySlot[tid]; 744 bool branchMispredict = fromIEW->branchMispredict[tid]; 745 746 // Squashing/not squashing the branch delay slot only makes 747 // sense when you're squashing from a branch, ie from a branch 748 // mispredict. 749 if (branchMispredict && !squash_bdelay_slot) { 750 bdelay_done_seq_num++; 751 } 752#endif 753 | |
754 if (fromIEW->includeSquashInst[tid] == true) { 755 squashed_inst--; | 744 if (fromIEW->includeSquashInst[tid] == true) { 745 squashed_inst--; |
756#if ISA_HAS_DELAY_SLOT 757 bdelay_done_seq_num--; 758#endif | |
759 } 760 761 // All younger instructions will be squashed. Set the sequence 762 // number as the youngest instruction in the ROB. 763 youngestSeqNum[tid] = squashed_inst; 764 | 746 } 747 748 // All younger instructions will be squashed. Set the sequence 749 // number as the youngest instruction in the ROB. 750 youngestSeqNum[tid] = squashed_inst; 751 |
765#if ISA_HAS_DELAY_SLOT 766 rob->squash(bdelay_done_seq_num, tid); 767 toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot; 768 toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num; 769#else | |
770 rob->squash(squashed_inst, tid); | 752 rob->squash(squashed_inst, tid); |
771 toIEW->commitInfo[tid].squashDelaySlot = true; 772#endif | |
773 changedROBNumEntries[tid] = true; 774 775 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 776 777 toIEW->commitInfo[tid].squash = true; 778 779 // Send back the rob squashing signal so other stages know that 780 // the ROB is in the process of squashing. --- 20 unchanged lines hidden (view full) --- 801 setNextStatus(); 802 803 if (squashCounter != numThreads) { 804 // If we're not currently squashing, then get instructions. 805 getInsts(); 806 807 // Try to commit any instructions. 808 commitInsts(); | 753 changedROBNumEntries[tid] = true; 754 755 toIEW->commitInfo[tid].doneSeqNum = squashed_inst; 756 757 toIEW->commitInfo[tid].squash = true; 758 759 // Send back the rob squashing signal so other stages know that 760 // the ROB is in the process of squashing. --- 20 unchanged lines hidden (view full) --- 781 setNextStatus(); 782 783 if (squashCounter != numThreads) { 784 // If we're not currently squashing, then get instructions. 785 getInsts(); 786 787 // Try to commit any instructions. 788 commitInsts(); |
809 } else { 810#if ISA_HAS_DELAY_SLOT 811 skidInsert(); 812#endif | |
813 } 814 815 //Check for any activity 816 threads = activeThreads->begin(); 817 818 while (threads != end) { 819 unsigned tid = *threads++; 820 --- 335 unchanged lines hidden (view full) --- 1156} 1157 1158template <class Impl> 1159void 1160DefaultCommit<Impl>::getInsts() 1161{ 1162 DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 1163 | 789 } 790 791 //Check for any activity 792 threads = activeThreads->begin(); 793 794 while (threads != end) { 795 unsigned tid = *threads++; 796 --- 335 unchanged lines hidden (view full) --- 1132} 1133 1134template <class Impl> 1135void 1136DefaultCommit<Impl>::getInsts() 1137{ 1138 DPRINTF(Commit, "Getting instructions from Rename stage.\n"); 1139 |
1164#if ISA_HAS_DELAY_SLOT | |
1165 // Read any renamed instructions and place them into the ROB. | 1140 // Read any renamed instructions and place them into the ROB. |
1166 int insts_to_process = std::min((int)renameWidth, 1167 (int)(fromRename->size + skidBuffer.size())); 1168 int rename_idx = 0; 1169 1170 DPRINTF(Commit, "%i insts available to process. Rename Insts:%i " 1171 "SkidBuffer Insts:%i\n", insts_to_process, fromRename->size, 1172 skidBuffer.size()); 1173#else 1174 // Read any renamed instructions and place them into the ROB. | |
1175 int insts_to_process = std::min((int)renameWidth, fromRename->size); | 1141 int insts_to_process = std::min((int)renameWidth, fromRename->size); |
1176#endif | |
1177 | 1142 |
1178 | |
1179 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 1180 DynInstPtr inst; 1181 | 1143 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) { 1144 DynInstPtr inst; 1145 |
1182#if ISA_HAS_DELAY_SLOT 1183 // Get insts from skidBuffer or from Rename 1184 if (skidBuffer.size() > 0) { 1185 DPRINTF(Commit, "Grabbing skidbuffer inst.\n"); 1186 inst = skidBuffer.front(); 1187 skidBuffer.pop(); 1188 } else { 1189 DPRINTF(Commit, "Grabbing rename inst.\n"); 1190 inst = fromRename->insts[rename_idx++]; 1191 } 1192#else | |
1193 inst = fromRename->insts[inst_num]; | 1146 inst = fromRename->insts[inst_num]; |
1194#endif | |
1195 int tid = inst->threadNumber; 1196 1197 if (!inst->isSquashed() && 1198 commitStatus[tid] != ROBSquashing && 1199 commitStatus[tid] != TrapPending) { 1200 changedROBNumEntries[tid] = true; 1201 1202 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n", --- 5 unchanged lines hidden (view full) --- 1208 1209 youngestSeqNum[tid] = inst->seqNum; 1210 } else { 1211 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 1212 "squashed, skipping.\n", 1213 inst->readPC(), inst->seqNum, tid); 1214 } 1215 } | 1147 int tid = inst->threadNumber; 1148 1149 if (!inst->isSquashed() && 1150 commitStatus[tid] != ROBSquashing && 1151 commitStatus[tid] != TrapPending) { 1152 changedROBNumEntries[tid] = true; 1153 1154 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n", --- 5 unchanged lines hidden (view full) --- 1160 1161 youngestSeqNum[tid] = inst->seqNum; 1162 } else { 1163 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 1164 "squashed, skipping.\n", 1165 inst->readPC(), inst->seqNum, tid); 1166 } 1167 } |
1216 1217#if ISA_HAS_DELAY_SLOT 1218 if (rename_idx < fromRename->size) { 1219 DPRINTF(Commit,"Placing Rename Insts into skidBuffer.\n"); 1220 1221 for (; 1222 rename_idx < fromRename->size; 1223 rename_idx++) { 1224 DynInstPtr inst = fromRename->insts[rename_idx]; 1225 1226 if (!inst->isSquashed()) { 1227 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ", 1228 "skidBuffer.\n", inst->readPC(), inst->seqNum, 1229 inst->threadNumber); 1230 skidBuffer.push(inst); 1231 } else { 1232 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " 1233 "squashed, skipping.\n", 1234 inst->readPC(), inst->seqNum, inst->threadNumber); 1235 } 1236 } 1237 } 1238#endif 1239 | |
1240} 1241 1242template <class Impl> 1243void 1244DefaultCommit<Impl>::skidInsert() 1245{ 1246 DPRINTF(Commit, "Attempting to any instructions from rename into " 1247 "skidBuffer.\n"); --- 205 unchanged lines hidden --- | 1168} 1169 1170template <class Impl> 1171void 1172DefaultCommit<Impl>::skidInsert() 1173{ 1174 DPRINTF(Commit, "Attempting to any instructions from rename into " 1175 "skidBuffer.\n"); --- 205 unchanged lines hidden --- |