1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#include <algorithm>
45#include <set>
46#include <string>
47
48#include "arch/utility.hh"
49#include "base/loader/symtab.hh"
50#include "base/cp_annotate.hh"
51#include "config/the_isa.hh"
52#include "cpu/checker/cpu.hh"
53#include "cpu/o3/commit.hh"
54#include "cpu/o3/thread_state.hh"
55#include "cpu/base.hh"
56#include "cpu/exetrace.hh"
57#include "cpu/timebuf.hh"
58#include "debug/Activity.hh"
59#include "debug/Commit.hh"
60#include "debug/CommitRate.hh"
61#include "debug/Drain.hh"
62#include "debug/ExecFaulting.hh"
63#include "params/DerivO3CPU.hh"
64#include "sim/faults.hh"
65#include "sim/full_system.hh"
66
67using namespace std;
68
69template <class Impl>
70DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
71 ThreadID _tid)
72 : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid)
73{
74}
75
76template <class Impl>
77void
78DefaultCommit<Impl>::TrapEvent::process()
79{
80 // This will get reset by commit if it was switched out at the
81 // time of this event processing.
82 commit->trapSquash[tid] = true;
83}
84
85template <class Impl>
86const char *
87DefaultCommit<Impl>::TrapEvent::description() const
88{
89 return "Trap";
90}
91
92template <class Impl>
93DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
94 : cpu(_cpu),
95 squashCounter(0),
96 iewToCommitDelay(params->iewToCommitDelay),
97 commitToIEWDelay(params->commitToIEWDelay),
98 renameToROBDelay(params->renameToROBDelay),
99 fetchToCommitDelay(params->commitToFetchDelay),
100 renameWidth(params->renameWidth),
101 commitWidth(params->commitWidth),
102 numThreads(params->numThreads),
103 drainPending(false),
104 trapLatency(params->trapLatency),
105 canHandleInterrupts(true),
106 avoidQuiesceLiveLock(false)
107{
108 _status = Active;
109 _nextStatus = Inactive;
110 std::string policy = params->smtCommitPolicy;
111
112 //Convert string to lowercase
113 std::transform(policy.begin(), policy.end(), policy.begin(),
114 (int(*)(int)) tolower);
115
116 //Assign commit policy
117 if (policy == "aggressive"){
118 commitPolicy = Aggressive;
119
120 DPRINTF(Commit,"Commit Policy set to Aggressive.\n");
121 } else if (policy == "roundrobin"){
122 commitPolicy = RoundRobin;
123
124 //Set-Up Priority List
125 for (ThreadID tid = 0; tid < numThreads; tid++) {
126 priority_list.push_back(tid);
127 }
128
129 DPRINTF(Commit,"Commit Policy set to Round Robin.\n");
130 } else if (policy == "oldestready"){
131 commitPolicy = OldestReady;
132
133 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
134 } else {
135 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
136 "RoundRobin,OldestReady}");
137 }
138
139 for (ThreadID tid = 0; tid < numThreads; tid++) {
140 commitStatus[tid] = Idle;
141 changedROBNumEntries[tid] = false;
142 checkEmptyROB[tid] = false;
143 trapInFlight[tid] = false;
144 committedStores[tid] = false;
145 trapSquash[tid] = false;
146 tcSquash[tid] = false;
147 pc[tid].set(0);
148 lastCommitedSeqNum[tid] = 0;
149 squashAfterInst[tid] = NULL;
150 }
151 interrupt = NoFault;
152}
153
154template <class Impl>
155std::string
156DefaultCommit<Impl>::name() const
157{
158 return cpu->name() + ".commit";
159}
160
161template <class Impl>
162void
163DefaultCommit<Impl>::regStats()
164{
165 using namespace Stats;
166 commitSquashedInsts
167 .name(name() + ".commitSquashedInsts")
168 .desc("The number of squashed insts skipped by commit")
169 .prereq(commitSquashedInsts);
170 commitSquashEvents
171 .name(name() + ".commitSquashEvents")
172 .desc("The number of times commit is told to squash")
173 .prereq(commitSquashEvents);
174 commitNonSpecStalls
175 .name(name() + ".commitNonSpecStalls")
176 .desc("The number of times commit has been forced to stall to "
177 "communicate backwards")
178 .prereq(commitNonSpecStalls);
179 branchMispredicts
180 .name(name() + ".branchMispredicts")
181 .desc("The number of times a branch was mispredicted")
182 .prereq(branchMispredicts);
183 numCommittedDist
184 .init(0,commitWidth,1)
185 .name(name() + ".committed_per_cycle")
186 .desc("Number of insts commited each cycle")
187 .flags(Stats::pdf)
188 ;
189
190 instsCommitted
191 .init(cpu->numThreads)
192 .name(name() + ".committedInsts")
193 .desc("Number of instructions committed")
194 .flags(total)
195 ;
196
197 opsCommitted
198 .init(cpu->numThreads)
199 .name(name() + ".committedOps")
200 .desc("Number of ops (including micro ops) committed")
201 .flags(total)
202 ;
203
204 statComSwp
205 .init(cpu->numThreads)
206 .name(name() + ".swp_count")
207 .desc("Number of s/w prefetches committed")
208 .flags(total)
209 ;
210
211 statComRefs
212 .init(cpu->numThreads)
213 .name(name() + ".refs")
214 .desc("Number of memory references committed")
215 .flags(total)
216 ;
217
218 statComLoads
219 .init(cpu->numThreads)
220 .name(name() + ".loads")
221 .desc("Number of loads committed")
222 .flags(total)
223 ;
224
225 statComMembars
226 .init(cpu->numThreads)
227 .name(name() + ".membars")
228 .desc("Number of memory barriers committed")
229 .flags(total)
230 ;
231
232 statComBranches
233 .init(cpu->numThreads)
234 .name(name() + ".branches")
235 .desc("Number of branches committed")
236 .flags(total)
237 ;
238
239 statComFloating
240 .init(cpu->numThreads)
241 .name(name() + ".fp_insts")
242 .desc("Number of committed floating point instructions.")
243 .flags(total)
244 ;
245
246 statComInteger
247 .init(cpu->numThreads)
248 .name(name()+".int_insts")
249 .desc("Number of committed integer instructions.")
250 .flags(total)
251 ;
252
253 statComFunctionCalls
254 .init(cpu->numThreads)
255 .name(name()+".function_calls")
256 .desc("Number of function calls committed.")
257 .flags(total)
258 ;
259
260 commitEligible
261 .init(cpu->numThreads)
262 .name(name() + ".bw_limited")
263 .desc("number of insts not committed due to BW limits")
264 .flags(total)
265 ;
266
267 commitEligibleSamples
268 .name(name() + ".bw_lim_events")
269 .desc("number cycles where commit BW limit reached")
270 ;
271}
272
273template <class Impl>
274void
275DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
276{
277 thread = threads;
278}
279
280template <class Impl>
281void
282DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
283{
284 timeBuffer = tb_ptr;
285
286 // Setup wire to send information back to IEW.
287 toIEW = timeBuffer->getWire(0);
288
289 // Setup wire to read data from IEW (for the ROB).
290 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
291}
292
293template <class Impl>
294void
295DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
296{
297 fetchQueue = fq_ptr;
298
299 // Setup wire to get instructions from rename (for the ROB).
300 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
301}
302
303template <class Impl>
304void
305DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
306{
307 renameQueue = rq_ptr;
308
309 // Setup wire to get instructions from rename (for the ROB).
310 fromRename = renameQueue->getWire(-renameToROBDelay);
311}
312
313template <class Impl>
314void
315DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
316{
317 iewQueue = iq_ptr;
318
319 // Setup wire to get instructions from IEW.
320 fromIEW = iewQueue->getWire(-iewToCommitDelay);
321}
322
323template <class Impl>
324void
325DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
326{
327 iewStage = iew_stage;
328}
329
330template<class Impl>
331void
332DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
333{
334 activeThreads = at_ptr;
335}
336
337template <class Impl>
338void
339DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
340{
341 for (ThreadID tid = 0; tid < numThreads; tid++)
342 renameMap[tid] = &rm_ptr[tid];
343}
344
345template <class Impl>
346void
347DefaultCommit<Impl>::setROB(ROB *rob_ptr)
348{
349 rob = rob_ptr;
350}
351
352template <class Impl>
353void
354DefaultCommit<Impl>::startupStage()
355{
356 rob->setActiveThreads(activeThreads);
357 rob->resetEntries();
358
359 // Broadcast the number of free entries.
360 for (ThreadID tid = 0; tid < numThreads; tid++) {
361 toIEW->commitInfo[tid].usedROB = true;
362 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
363 toIEW->commitInfo[tid].emptyROB = true;
364 }
365
366 // Commit must broadcast the number of free entries it has at the
367 // start of the simulation, so it starts as active.
368 cpu->activateStage(O3CPU::CommitIdx);
369
370 cpu->activityThisCycle();
371}
372
373template <class Impl>
374void
375DefaultCommit<Impl>::drain()
376{
377 drainPending = true;
378}
379
380template <class Impl>
381void
382DefaultCommit<Impl>::drainResume()
383{
384 drainPending = false;
385}
386
387template <class Impl>
388void
389DefaultCommit<Impl>::drainSanityCheck() const
390{
391 assert(isDrained());
392 rob->drainSanityCheck();
393}
394
395template <class Impl>
396bool
397DefaultCommit<Impl>::isDrained() const
398{
399 /* Make sure no one is executing microcode. There are two reasons
400 * for this:
401 * - Hardware virtualized CPUs can't switch into the middle of a
402 * microcode sequence.
403 * - The current fetch implementation will most likely get very
404 * confused if it tries to start fetching an instruction that
405 * is executing in the middle of a ucode sequence that changes
406 * address mappings. This can happen on for example x86.
407 */
408 for (ThreadID tid = 0; tid < numThreads; tid++) {
409 if (pc[tid].microPC() != 0)
410 return false;
411 }
412
413 /* Make sure that all instructions have finished committing before
414 * declaring the system as drained. We want the pipeline to be
415 * completely empty when we declare the CPU to be drained. This
416 * makes debugging easier since CPU handover and restoring from a
417 * checkpoint with a different CPU should have the same timing.
418 */
419 return rob->isEmpty() &&
420 interrupt == NoFault;
421}
422
423template <class Impl>
424void
425DefaultCommit<Impl>::takeOverFrom()
426{
427 _status = Active;
428 _nextStatus = Inactive;
429 for (ThreadID tid = 0; tid < numThreads; tid++) {
430 commitStatus[tid] = Idle;
431 changedROBNumEntries[tid] = false;
432 trapSquash[tid] = false;
433 tcSquash[tid] = false;
434 squashAfterInst[tid] = NULL;
435 }
436 squashCounter = 0;
437 rob->takeOverFrom();
438}
439
440template <class Impl>
441void
442DefaultCommit<Impl>::updateStatus()
443{
444 // reset ROB changed variable
445 list<ThreadID>::iterator threads = activeThreads->begin();
446 list<ThreadID>::iterator end = activeThreads->end();
447
448 while (threads != end) {
449 ThreadID tid = *threads++;
450
451 changedROBNumEntries[tid] = false;
452
453 // Also check if any of the threads has a trap pending
454 if (commitStatus[tid] == TrapPending ||
455 commitStatus[tid] == FetchTrapPending) {
456 _nextStatus = Active;
457 }
458 }
459
460 if (_nextStatus == Inactive && _status == Active) {
461 DPRINTF(Activity, "Deactivating stage.\n");
462 cpu->deactivateStage(O3CPU::CommitIdx);
463 } else if (_nextStatus == Active && _status == Inactive) {
464 DPRINTF(Activity, "Activating stage.\n");
465 cpu->activateStage(O3CPU::CommitIdx);
466 }
467
468 _status = _nextStatus;
469}
470
471template <class Impl>
472void
473DefaultCommit<Impl>::setNextStatus()
474{
475 int squashes = 0;
476
477 list<ThreadID>::iterator threads = activeThreads->begin();
478 list<ThreadID>::iterator end = activeThreads->end();
479
480 while (threads != end) {
481 ThreadID tid = *threads++;
482
483 if (commitStatus[tid] == ROBSquashing) {
484 squashes++;
485 }
486 }
487
488 squashCounter = squashes;
489
490 // If commit is currently squashing, then it will have activity for the
491 // next cycle. Set its next status as active.
492 if (squashCounter) {
493 _nextStatus = Active;
494 }
495}
496
497template <class Impl>
498bool
499DefaultCommit<Impl>::changedROBEntries()
500{
501 list<ThreadID>::iterator threads = activeThreads->begin();
502 list<ThreadID>::iterator end = activeThreads->end();
503
504 while (threads != end) {
505 ThreadID tid = *threads++;
506
507 if (changedROBNumEntries[tid]) {
508 return true;
509 }
510 }
511
512 return false;
513}
514
515template <class Impl>
516size_t
517DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
518{
519 return rob->numFreeEntries(tid);
520}
521
522template <class Impl>
523void
524DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
525{
526 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
527
528 TrapEvent *trap = new TrapEvent(this, tid);
529
530 cpu->schedule(trap, cpu->clockEdge(trapLatency));
531 trapInFlight[tid] = true;
532 thread[tid]->trapPending = true;
533}
534
535template <class Impl>
536void
537DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
538{
539 assert(!trapInFlight[tid]);
540 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
541
542 tcSquash[tid] = true;
543}
544
545template <class Impl>
546void
547DefaultCommit<Impl>::squashAll(ThreadID tid)
548{
549 // If we want to include the squashing instruction in the squash,
550 // then use one older sequence number.
551 // Hopefully this doesn't mess things up. Basically I want to squash
552 // all instructions of this thread.
553 InstSeqNum squashed_inst = rob->isEmpty() ?
554 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
555
556 // All younger instructions will be squashed. Set the sequence
557 // number as the youngest instruction in the ROB (0 in this case.
558 // Hopefully nothing breaks.)
559 youngestSeqNum[tid] = lastCommitedSeqNum[tid];
560
561 rob->squash(squashed_inst, tid);
562 changedROBNumEntries[tid] = true;
563
564 // Send back the sequence number of the squashed instruction.
565 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
566
567 // Send back the squash signal to tell stages that they should
568 // squash.
569 toIEW->commitInfo[tid].squash = true;
570
571 // Send back the rob squashing signal so other stages know that
572 // the ROB is in the process of squashing.
573 toIEW->commitInfo[tid].robSquashing = true;
574
575 toIEW->commitInfo[tid].mispredictInst = NULL;
576 toIEW->commitInfo[tid].squashInst = NULL;
577
578 toIEW->commitInfo[tid].pc = pc[tid];
579}
580
581template <class Impl>
582void
583DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
584{
585 squashAll(tid);
586
587 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
588
589 thread[tid]->trapPending = false;
590 thread[tid]->noSquashFromTC = false;
591 trapInFlight[tid] = false;
592
593 trapSquash[tid] = false;
594
595 commitStatus[tid] = ROBSquashing;
596 cpu->activityThisCycle();
597}
598
599template <class Impl>
600void
601DefaultCommit<Impl>::squashFromTC(ThreadID tid)
602{
603 squashAll(tid);
604
605 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
606
607 thread[tid]->noSquashFromTC = false;
608 assert(!thread[tid]->trapPending);
609
610 commitStatus[tid] = ROBSquashing;
611 cpu->activityThisCycle();
612
613 tcSquash[tid] = false;
614}
615
616template <class Impl>
617void
618DefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid)
619{
620 DPRINTF(Commit, "Squashing after squash after request, "
621 "restarting at PC %s\n", pc[tid]);
622
623 squashAll(tid);
624 // Make sure to inform the fetch stage of which instruction caused
625 // the squash. It'll try to re-fetch an instruction executing in
626 // microcode unless this is set.
627 toIEW->commitInfo[tid].squashInst = squashAfterInst[tid];
628 squashAfterInst[tid] = NULL;
629
630 commitStatus[tid] = ROBSquashing;
631 cpu->activityThisCycle();
632}
633
634template <class Impl>
635void
636DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst)
637{
638 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
639 tid, head_inst->seqNum);
640
641 assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst);
642 commitStatus[tid] = SquashAfterPending;
643 squashAfterInst[tid] = head_inst;
644}
645
646template <class Impl>
647void
648DefaultCommit<Impl>::tick()
649{
650 wroteToTimeBuffer = false;
651 _nextStatus = Inactive;
652
653 if (activeThreads->empty())
654 return;
655
656 list<ThreadID>::iterator threads = activeThreads->begin();
657 list<ThreadID>::iterator end = activeThreads->end();
658
659 // Check if any of the threads are done squashing. Change the
660 // status if they are done.
661 while (threads != end) {
662 ThreadID tid = *threads++;
663
664 // Clear the bit saying if the thread has committed stores
665 // this cycle.
666 committedStores[tid] = false;
667
668 if (commitStatus[tid] == ROBSquashing) {
669
670 if (rob->isDoneSquashing(tid)) {
671 commitStatus[tid] = Running;
672 } else {
673 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
674 " insts this cycle.\n", tid);
675 rob->doSquash(tid);
676 toIEW->commitInfo[tid].robSquashing = true;
677 wroteToTimeBuffer = true;
678 }
679 }
680 }
681
682 commit();
683
684 markCompletedInsts();
685
686 threads = activeThreads->begin();
687
688 while (threads != end) {
689 ThreadID tid = *threads++;
690
691 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
692 // The ROB has more instructions it can commit. Its next status
693 // will be active.
694 _nextStatus = Active;
695
696 DynInstPtr inst = rob->readHeadInst(tid);
697
698 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
699 " ROB and ready to commit\n",
700 tid, inst->seqNum, inst->pcState());
701
702 } else if (!rob->isEmpty(tid)) {
703 DynInstPtr inst = rob->readHeadInst(tid);
704
705 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
706 "%s is head of ROB and not ready\n",
707 tid, inst->seqNum, inst->pcState());
708 }
709
710 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
711 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
712 }
713
714
715 if (wroteToTimeBuffer) {
716 DPRINTF(Activity, "Activity This Cycle.\n");
717 cpu->activityThisCycle();
718 }
719
720 updateStatus();
721}
722
723template <class Impl>
724void
725DefaultCommit<Impl>::handleInterrupt()
726{
727 // Verify that we still have an interrupt to handle
728 if (!cpu->checkInterrupts(cpu->tcBase(0))) {
729 DPRINTF(Commit, "Pending interrupt is cleared by master before "
730 "it got handled. Restart fetching from the orig path.\n");
731 toIEW->commitInfo[0].clearInterrupt = true;
732 interrupt = NoFault;
733 avoidQuiesceLiveLock = true;
734 return;
735 }
736
737 // Wait until all in flight instructions are finished before enterring
738 // the interrupt.
739 if (canHandleInterrupts && cpu->instList.empty()) {
740 // Squash or record that I need to squash this cycle if
741 // an interrupt needed to be handled.
742 DPRINTF(Commit, "Interrupt detected.\n");
743
744 // Clear the interrupt now that it's going to be handled
745 toIEW->commitInfo[0].clearInterrupt = true;
746
747 assert(!thread[0]->noSquashFromTC);
748 thread[0]->noSquashFromTC = true;
749
750 if (cpu->checker) {
751 cpu->checker->handlePendingInt();
752 }
753
754 // CPU will handle interrupt.
755 cpu->processInterrupts(interrupt);
756
757 thread[0]->noSquashFromTC = false;
758
759 commitStatus[0] = TrapPending;
760
761 // Generate trap squash event.
762 generateTrapEvent(0);
763
764 interrupt = NoFault;
765 avoidQuiesceLiveLock = false;
766 } else {
767 DPRINTF(Commit, "Interrupt pending: instruction is %sin "
768 "flight, ROB is %sempty\n",
769 canHandleInterrupts ? "not " : "",
770 cpu->instList.empty() ? "" : "not " );
771 }
772}
773
774template <class Impl>
775void
776DefaultCommit<Impl>::propagateInterrupt()
777{
778 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
779 tcSquash[0])
780 return;
781
782 // Process interrupts if interrupts are enabled, not in PAL
783 // mode, and no other traps or external squashes are currently
784 // pending.
785 // @todo: Allow other threads to handle interrupts.
786
787 // Get any interrupt that happened
788 interrupt = cpu->getInterrupts();
789
790 // Tell fetch that there is an interrupt pending. This
791 // will make fetch wait until it sees a non PAL-mode PC,
792 // at which point it stops fetching instructions.
793 if (interrupt != NoFault)
794 toIEW->commitInfo[0].interruptPending = true;
795}
796
797template <class Impl>
798void
799DefaultCommit<Impl>::commit()
800{
801 if (FullSystem) {
802 // Check if we have a interrupt and get read to handle it
803 if (cpu->checkInterrupts(cpu->tcBase(0)))
804 propagateInterrupt();
805 }
806
807 ////////////////////////////////////
808 // Check for any possible squashes, handle them first
809 ////////////////////////////////////
810 list<ThreadID>::iterator threads = activeThreads->begin();
811 list<ThreadID>::iterator end = activeThreads->end();
812
813 while (threads != end) {
814 ThreadID tid = *threads++;
815
816 // Not sure which one takes priority. I think if we have
817 // both, that's a bad sign.
818 if (trapSquash[tid] == true) {
819 assert(!tcSquash[tid]);
820 squashFromTrap(tid);
821 } else if (tcSquash[tid] == true) {
822 assert(commitStatus[tid] != TrapPending);
823 squashFromTC(tid);
824 } else if (commitStatus[tid] == SquashAfterPending) {
825 // A squash from the previous cycle of the commit stage (i.e.,
826 // commitInsts() called squashAfter) is pending. Squash the
827 // thread now.
828 squashFromSquashAfter(tid);
829 }
830
831 // Squashed sequence number must be older than youngest valid
832 // instruction in the ROB. This prevents squashes from younger
833 // instructions overriding squashes from older instructions.
834 if (fromIEW->squash[tid] &&
835 commitStatus[tid] != TrapPending &&
836 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
837
838 if (fromIEW->mispredictInst[tid]) {
839 DPRINTF(Commit,
840 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
841 tid,
842 fromIEW->mispredictInst[tid]->instAddr(),
843 fromIEW->squashedSeqNum[tid]);
844 } else {
845 DPRINTF(Commit,
846 "[tid:%i]: Squashing due to order violation [sn:%i]\n",
847 tid, fromIEW->squashedSeqNum[tid]);
848 }
849
850 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
851 tid,
852 fromIEW->pc[tid].nextInstAddr());
853
854 commitStatus[tid] = ROBSquashing;
855
856 // If we want to include the squashing instruction in the squash,
857 // then use one older sequence number.
858 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
859
860 if (fromIEW->includeSquashInst[tid] == true) {
861 squashed_inst--;
862 }
863
864 // All younger instructions will be squashed. Set the sequence
865 // number as the youngest instruction in the ROB.
866 youngestSeqNum[tid] = squashed_inst;
867
868 rob->squash(squashed_inst, tid);
869 changedROBNumEntries[tid] = true;
870
871 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
872
873 toIEW->commitInfo[tid].squash = true;
874
875 // Send back the rob squashing signal so other stages know that
876 // the ROB is in the process of squashing.
877 toIEW->commitInfo[tid].robSquashing = true;
878
879 toIEW->commitInfo[tid].mispredictInst =
880 fromIEW->mispredictInst[tid];
881 toIEW->commitInfo[tid].branchTaken =
882 fromIEW->branchTaken[tid];
883 toIEW->commitInfo[tid].squashInst =
884 rob->findInst(tid, squashed_inst);
885 if (toIEW->commitInfo[tid].mispredictInst) {
886 if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) {
887 toIEW->commitInfo[tid].branchTaken = true;
888 }
889 }
890
891 toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
892
893 if (toIEW->commitInfo[tid].mispredictInst) {
894 ++branchMispredicts;
895 }
896 }
897
898 }
899
900 setNextStatus();
901
902 if (squashCounter != numThreads) {
903 // If we're not currently squashing, then get instructions.
904 getInsts();
905
906 // Try to commit any instructions.
907 commitInsts();
908 }
909
910 //Check for any activity
911 threads = activeThreads->begin();
912
913 while (threads != end) {
914 ThreadID tid = *threads++;
915
916 if (changedROBNumEntries[tid]) {
917 toIEW->commitInfo[tid].usedROB = true;
918 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
919
920 wroteToTimeBuffer = true;
921 changedROBNumEntries[tid] = false;
922 if (rob->isEmpty(tid))
923 checkEmptyROB[tid] = true;
924 }
925
926 // ROB is only considered "empty" for previous stages if: a)
927 // ROB is empty, b) there are no outstanding stores, c) IEW
928 // stage has received any information regarding stores that
929 // committed.
930 // c) is checked by making sure to not consider the ROB empty
931 // on the same cycle as when stores have been committed.
932 // @todo: Make this handle multi-cycle communication between
933 // commit and IEW.
934 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
935 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
936 checkEmptyROB[tid] = false;
937 toIEW->commitInfo[tid].usedROB = true;
938 toIEW->commitInfo[tid].emptyROB = true;
939 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
940 wroteToTimeBuffer = true;
941 }
942
943 }
944}
945
946template <class Impl>
947void
948DefaultCommit<Impl>::commitInsts()
949{
950 ////////////////////////////////////
951 // Handle commit
952 // Note that commit will be handled prior to putting new
953 // instructions in the ROB so that the ROB only tries to commit
954 // instructions it has in this current cycle, and not instructions
955 // it is writing in during this cycle. Can't commit and squash
956 // things at the same time...
957 ////////////////////////////////////
958
959 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
960
961 unsigned num_committed = 0;
962
963 DynInstPtr head_inst;
964
965 // Commit as many instructions as possible until the commit bandwidth
966 // limit is reached, or it becomes impossible to commit any more.
967 while (num_committed < commitWidth) {
968 // Check for any interrupt that we've already squashed for
969 // and start processing it.
970 if (interrupt != NoFault)
971 handleInterrupt();
972
973 int commit_thread = getCommittingThread();
974
975 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
976 break;
977
978 head_inst = rob->readHeadInst(commit_thread);
979
980 ThreadID tid = head_inst->threadNumber;
981
982 assert(tid == commit_thread);
983
984 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
985 head_inst->seqNum, tid);
986
987 // If the head instruction is squashed, it is ready to retire
988 // (be removed from the ROB) at any time.
989 if (head_inst->isSquashed()) {
990
991 DPRINTF(Commit, "Retiring squashed instruction from "
992 "ROB.\n");
993
994 rob->retireHead(commit_thread);
995
996 ++commitSquashedInsts;
997
998 // Record that the number of ROB entries has changed.
999 changedROBNumEntries[tid] = true;
1000 } else {
1001 pc[tid] = head_inst->pcState();
1002
1003 // Increment the total number of non-speculative instructions
1004 // executed.
1005 // Hack for now: it really shouldn't happen until after the
1006 // commit is deemed to be successful, but this count is needed
1007 // for syscalls.
1008 thread[tid]->funcExeInst++;
1009
1010 // Try to commit the head instruction.
1011 bool commit_success = commitHead(head_inst, num_committed);
1012
1013 if (commit_success) {
1014 ++num_committed;
1015
1016 changedROBNumEntries[tid] = true;
1017
1018 // Set the doneSeqNum to the youngest committed instruction.
1019 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
1020
1021 if (tid == 0) {
1022 canHandleInterrupts = (!head_inst->isDelayedCommit()) &&
1023 ((THE_ISA != ALPHA_ISA) ||
1024 (!(pc[0].instAddr() & 0x3)));
1025 }
1026
1027 // Updates misc. registers.
1028 head_inst->updateMiscRegs();
1029
1030 cpu->traceFunctions(pc[tid].instAddr());
1031
1032 TheISA::advancePC(pc[tid], head_inst->staticInst);
1033
1034 // Keep track of the last sequence number commited
1035 lastCommitedSeqNum[tid] = head_inst->seqNum;
1036
1037 // If this is an instruction that doesn't play nicely with
1038 // others squash everything and restart fetch
1039 if (head_inst->isSquashAfter())
1040 squashAfter(tid, head_inst);
1041
1042 if (drainPending) {
1043 DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]);
1044 if (pc[tid].microPC() == 0 && interrupt == NoFault) {
1045 squashAfter(tid, head_inst);
1046 cpu->commitDrained(tid);
1047 }
1048 }
1049
1050 int count = 0;
1051 Addr oldpc;
1052 // Debug statement. Checks to make sure we're not
1053 // currently updating state while handling PC events.
1054 assert(!thread[tid]->noSquashFromTC && !thread[tid]->trapPending);
1055 do {
1056 oldpc = pc[tid].instAddr();
1057 cpu->system->pcEventQueue.service(thread[tid]->getTC());
1058 count++;
1059 } while (oldpc != pc[tid].instAddr());
1060 if (count > 1) {
1061 DPRINTF(Commit,
1062 "PC skip function event, stopping commit\n");
1063 break;
1064 }
1065
1066 // Check if an instruction just enabled interrupts and we've
1067 // previously had an interrupt pending that was not handled
1068 // because interrupts were subsequently disabled before the
1069 // pipeline reached a place to handle the interrupt. In that
1070 // case squash now to make sure the interrupt is handled.
1071 //
1072 // If we don't do this, we might end up in a live lock situation
1073 if (!interrupt && avoidQuiesceLiveLock &&
1074 (!head_inst->isMicroop() || head_inst->isLastMicroop()) &&
1075 cpu->checkInterrupts(cpu->tcBase(0)))
1076 squashAfter(tid, head_inst);
1077 } else {
1078 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1079 "[tid:%i] [sn:%i].\n",
1080 head_inst->pcState(), tid ,head_inst->seqNum);
1081 break;
1082 }
1083 }
1084 }
1085
1086 DPRINTF(CommitRate, "%i\n", num_committed);
1087 numCommittedDist.sample(num_committed);
1088
1089 if (num_committed == commitWidth) {
1090 commitEligibleSamples++;
1091 }
1092}
1093
1094template <class Impl>
1095bool
1096DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1097{
1098 assert(head_inst);
1099
1100 ThreadID tid = head_inst->threadNumber;
1101
1102 // If the instruction is not executed yet, then it will need extra
1103 // handling. Signal backwards that it should be executed.
1104 if (!head_inst->isExecuted()) {
1105 // Keep this number correct. We have not yet actually executed
1106 // and committed this instruction.
1107 thread[tid]->funcExeInst--;
1108
1109 if (head_inst->isNonSpeculative() ||
1110 head_inst->isStoreConditional() ||
1111 head_inst->isMemBarrier() ||
1112 head_inst->isWriteBarrier()) {
1113
1114 DPRINTF(Commit, "Encountered a barrier or non-speculative "
1115 "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1116 head_inst->seqNum, head_inst->pcState());
1117
1118 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1119 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1120 return false;
1121 }
1122
1123 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1124
1125 // Change the instruction so it won't try to commit again until
1126 // it is executed.
1127 head_inst->clearCanCommit();
1128
1129 ++commitNonSpecStalls;
1130
1131 return false;
1132 } else if (head_inst->isLoad()) {
1133 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1134 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1135 return false;
1136 }
1137
1138 assert(head_inst->uncacheable());
1139 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
1140 head_inst->seqNum, head_inst->pcState());
1141
1142 // Send back the non-speculative instruction's sequence
1143 // number. Tell the lsq to re-execute the load.
1144 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1145 toIEW->commitInfo[tid].uncached = true;
1146 toIEW->commitInfo[tid].uncachedLoad = head_inst;
1147
1148 head_inst->clearCanCommit();
1149
1150 return false;
1151 } else {
1152 panic("Trying to commit un-executed instruction "
1153 "of unknown type!\n");
1154 }
1155 }
1156
1157 if (head_inst->isThreadSync()) {
1158 // Not handled for now.
1159 panic("Thread sync instructions are not handled yet.\n");
1160 }
1161
1162 // Check if the instruction caused a fault. If so, trap.
1163 Fault inst_fault = head_inst->getFault();
1164
1165 // Stores mark themselves as completed.
1166 if (!head_inst->isStore() && inst_fault == NoFault) {
1167 head_inst->setCompleted();
1168 }
1169
1170 // Use checker prior to updating anything due to traps or PC
1171 // based events.
1172 if (cpu->checker) {
1173 cpu->checker->verify(head_inst);
1174 }
1175
1176 if (inst_fault != NoFault) {
1177 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1178 head_inst->seqNum, head_inst->pcState());
1179
1180 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1181 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1182 return false;
1183 }
1184
1185 head_inst->setCompleted();
1186
1187 if (cpu->checker) {
1188 // Need to check the instruction before its fault is processed
1189 cpu->checker->verify(head_inst);
1190 }
1191
1192 assert(!thread[tid]->noSquashFromTC);
1193
1194 // Mark that we're in state update mode so that the trap's
1195 // execution doesn't generate extra squashes.
1196 thread[tid]->noSquashFromTC = true;
1197
1198 // Execute the trap. Although it's slightly unrealistic in
1199 // terms of timing (as it doesn't wait for the full timing of
1200 // the trap event to complete before updating state), it's
1201 // needed to update the state as soon as possible. This
1202 // prevents external agents from changing any specific state
1203 // that the trap need.
1204 cpu->trap(inst_fault, tid, head_inst->staticInst);
1205
1206 // Exit state update mode to avoid accidental updating.
1207 thread[tid]->noSquashFromTC = false;
1208
1209 commitStatus[tid] = TrapPending;
1210
1211 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1212 head_inst->seqNum);
1213 if (head_inst->traceData) {
1214 if (DTRACE(ExecFaulting)) {
1215 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1216 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1217 head_inst->traceData->dump();
1218 }
1219 delete head_inst->traceData;
1220 head_inst->traceData = NULL;
1221 }
1222
1223 // Generate trap squash event.
1224 generateTrapEvent(tid);
1225 return false;
1226 }
1227
1228 updateComInstStats(head_inst);
1229
1230 if (FullSystem) {
1231 if (thread[tid]->profile) {
1232 thread[tid]->profilePC = head_inst->instAddr();
1233 ProfileNode *node = thread[tid]->profile->consume(
1234 thread[tid]->getTC(), head_inst->staticInst);
1235
1236 if (node)
1237 thread[tid]->profileNode = node;
1238 }
1239 if (CPA::available()) {
1240 if (head_inst->isControl()) {
1241 ThreadContext *tc = thread[tid]->getTC();
1242 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1243 }
1244 }
1245 }
1246 DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
1247 head_inst->seqNum, head_inst->pcState());
1248 if (head_inst->traceData) {
1249 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1250 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1251 head_inst->traceData->dump();
1252 delete head_inst->traceData;
1253 head_inst->traceData = NULL;
1254 }
1255 if (head_inst->isReturn()) {
1256 DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n",
1257 head_inst->seqNum, head_inst->pcState());
1258 }
1259
1260 // Update the commit rename map
1261 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1262 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1263 head_inst->renamedDestRegIdx(i));
1264 }
1265
1266 // Finally clear the head ROB entry.
1267 rob->retireHead(tid);
1268
1269#if TRACING_ON
1270 head_inst->commitTick = curTick() - head_inst->fetchTick;
1271#endif
1272
1273 // If this was a store, record it for this cycle.
1274 if (head_inst->isStore())
1275 committedStores[tid] = true;
1276
1277 // Return true to indicate that we have committed an instruction.
1278 return true;
1279}
1280
1281template <class Impl>
1282void
1283DefaultCommit<Impl>::getInsts()
1284{
1285 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1286
1287 // Read any renamed instructions and place them into the ROB.
1288 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1289
1290 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1291 DynInstPtr inst;
1292
1293 inst = fromRename->insts[inst_num];
1294 ThreadID tid = inst->threadNumber;
1295
1296 if (!inst->isSquashed() &&
1297 commitStatus[tid] != ROBSquashing &&
1298 commitStatus[tid] != TrapPending) {
1299 changedROBNumEntries[tid] = true;
1300
1301 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1302 inst->pcState(), inst->seqNum, tid);
1303
1304 rob->insertInst(inst);
1305
1306 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1307
1308 youngestSeqNum[tid] = inst->seqNum;
1309 } else {
1310 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1311 "squashed, skipping.\n",
1312 inst->pcState(), inst->seqNum, tid);
1313 }
1314 }
1315}
1316
1317template <class Impl>
1318void
1319DefaultCommit<Impl>::skidInsert()
1320{
1321 DPRINTF(Commit, "Attempting to any instructions from rename into "
1322 "skidBuffer.\n");
1323
1324 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1325 DynInstPtr inst = fromRename->insts[inst_num];
1326
1327 if (!inst->isSquashed()) {
1328 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1329 "skidBuffer.\n", inst->pcState(), inst->seqNum,
1330 inst->threadNumber);
1331 skidBuffer.push(inst);
1332 } else {
1333 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1334 "squashed, skipping.\n",
1335 inst->pcState(), inst->seqNum, inst->threadNumber);
1336 }
1337 }
1338}
1339
1340template <class Impl>
1341void
1342DefaultCommit<Impl>::markCompletedInsts()
1343{
1344 // Grab completed insts out of the IEW instruction queue, and mark
1345 // instructions completed within the ROB.
1346 for (int inst_num = 0;
1347 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1348 ++inst_num)
1349 {
1350 if (!fromIEW->insts[inst_num]->isSquashed()) {
1351 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1352 "within ROB.\n",
1353 fromIEW->insts[inst_num]->threadNumber,
1354 fromIEW->insts[inst_num]->pcState(),
1355 fromIEW->insts[inst_num]->seqNum);
1356
1357 // Mark the instruction as ready to commit.
1358 fromIEW->insts[inst_num]->setCanCommit();
1359 }
1360 }
1361}
1362
1363template <class Impl>
1364bool
1365DefaultCommit<Impl>::robDoneSquashing()
1366{
1367 list<ThreadID>::iterator threads = activeThreads->begin();
1368 list<ThreadID>::iterator end = activeThreads->end();
1369
1370 while (threads != end) {
1371 ThreadID tid = *threads++;
1372
1373 if (!rob->isDoneSquashing(tid))
1374 return false;
1375 }
1376
1377 return true;
1378}
1379
1380template <class Impl>
1381void
1382DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1383{
1384 ThreadID tid = inst->threadNumber;
1385
1386 if (!inst->isMicroop() || inst->isLastMicroop())
1387 instsCommitted[tid]++;
1388 opsCommitted[tid]++;
1389
1390 // To match the old model, don't count nops and instruction
1391 // prefetches towards the total commit count.
1392 if (!inst->isNop() && !inst->isInstPrefetch()) {
1393 cpu->instDone(tid, inst);
1394 }
1395
1396 //
1397 // Control Instructions
1398 //
1399 if (inst->isControl())
1400 statComBranches[tid]++;
1401
1402 //
1403 // Memory references
1404 //
1405 if (inst->isMemRef()) {
1406 statComRefs[tid]++;
1407
1408 if (inst->isLoad()) {
1409 statComLoads[tid]++;
1410 }
1411 }
1412
1413 if (inst->isMemBarrier()) {
1414 statComMembars[tid]++;
1415 }
1416
1417 // Integer Instruction
1418 if (inst->isInteger())
1419 statComInteger[tid]++;
1420
1421 // Floating Point Instruction
1422 if (inst->isFloating())
1423 statComFloating[tid]++;
1424
1425 // Function Calls
1426 if (inst->isCall())
1427 statComFunctionCalls[tid]++;
1428
1429}
1430
1431////////////////////////////////////////
1432// //
1433// SMT COMMIT POLICY MAINTAINED HERE //
1434// //
1435////////////////////////////////////////
1436template <class Impl>
1437ThreadID
1438DefaultCommit<Impl>::getCommittingThread()
1439{
1440 if (numThreads > 1) {
1441 switch (commitPolicy) {
1442
1443 case Aggressive:
1444 //If Policy is Aggressive, commit will call
1445 //this function multiple times per
1446 //cycle
1447 return oldestReady();
1448
1449 case RoundRobin:
1450 return roundRobin();
1451
1452 case OldestReady:
1453 return oldestReady();
1454
1455 default:
1456 return InvalidThreadID;
1457 }
1458 } else {
1459 assert(!activeThreads->empty());
1460 ThreadID tid = activeThreads->front();
1461
1462 if (commitStatus[tid] == Running ||
1463 commitStatus[tid] == Idle ||
1464 commitStatus[tid] == FetchTrapPending) {
1465 return tid;
1466 } else {
1467 return InvalidThreadID;
1468 }
1469 }
1470}
1471
1472template<class Impl>
1473ThreadID
1474DefaultCommit<Impl>::roundRobin()
1475{
1476 list<ThreadID>::iterator pri_iter = priority_list.begin();
1477 list<ThreadID>::iterator end = priority_list.end();
1478
1479 while (pri_iter != end) {
1480 ThreadID tid = *pri_iter;
1481
1482 if (commitStatus[tid] == Running ||
1483 commitStatus[tid] == Idle ||
1484 commitStatus[tid] == FetchTrapPending) {
1485
1486 if (rob->isHeadReady(tid)) {
1487 priority_list.erase(pri_iter);
1488 priority_list.push_back(tid);
1489
1490 return tid;
1491 }
1492 }
1493
1494 pri_iter++;
1495 }
1496
1497 return InvalidThreadID;
1498}
1499
1500template<class Impl>
1501ThreadID
1502DefaultCommit<Impl>::oldestReady()
1503{
1504 unsigned oldest = 0;
1505 bool first = true;
1506
1507 list<ThreadID>::iterator threads = activeThreads->begin();
1508 list<ThreadID>::iterator end = activeThreads->end();
1509
1510 while (threads != end) {
1511 ThreadID tid = *threads++;
1512
1513 if (!rob->isEmpty(tid) &&
1514 (commitStatus[tid] == Running ||
1515 commitStatus[tid] == Idle ||
1516 commitStatus[tid] == FetchTrapPending)) {
1517
1518 if (rob->isHeadReady(tid)) {
1519
1520 DynInstPtr head_inst = rob->readHeadInst(tid);
1521
1522 if (first) {
1523 oldest = tid;
1524 first = false;
1525 } else if (head_inst->seqNum < oldest) {
1526 oldest = tid;
1527 }
1528 }
1529 }
1530 }
1531
1532 if (!first) {
1533 return oldest;
1534 } else {
1535 return InvalidThreadID;
1536 }
1537}
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#include <algorithm>
45#include <set>
46#include <string>
47
48#include "arch/utility.hh"
49#include "base/loader/symtab.hh"
50#include "base/cp_annotate.hh"
51#include "config/the_isa.hh"
52#include "cpu/checker/cpu.hh"
53#include "cpu/o3/commit.hh"
54#include "cpu/o3/thread_state.hh"
55#include "cpu/base.hh"
56#include "cpu/exetrace.hh"
57#include "cpu/timebuf.hh"
58#include "debug/Activity.hh"
59#include "debug/Commit.hh"
60#include "debug/CommitRate.hh"
61#include "debug/Drain.hh"
62#include "debug/ExecFaulting.hh"
63#include "params/DerivO3CPU.hh"
64#include "sim/faults.hh"
65#include "sim/full_system.hh"
66
67using namespace std;
68
69template <class Impl>
70DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
71 ThreadID _tid)
72 : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid)
73{
74}
75
76template <class Impl>
77void
78DefaultCommit<Impl>::TrapEvent::process()
79{
80 // This will get reset by commit if it was switched out at the
81 // time of this event processing.
82 commit->trapSquash[tid] = true;
83}
84
85template <class Impl>
86const char *
87DefaultCommit<Impl>::TrapEvent::description() const
88{
89 return "Trap";
90}
91
92template <class Impl>
93DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
94 : cpu(_cpu),
95 squashCounter(0),
96 iewToCommitDelay(params->iewToCommitDelay),
97 commitToIEWDelay(params->commitToIEWDelay),
98 renameToROBDelay(params->renameToROBDelay),
99 fetchToCommitDelay(params->commitToFetchDelay),
100 renameWidth(params->renameWidth),
101 commitWidth(params->commitWidth),
102 numThreads(params->numThreads),
103 drainPending(false),
104 trapLatency(params->trapLatency),
105 canHandleInterrupts(true),
106 avoidQuiesceLiveLock(false)
107{
108 _status = Active;
109 _nextStatus = Inactive;
110 std::string policy = params->smtCommitPolicy;
111
112 //Convert string to lowercase
113 std::transform(policy.begin(), policy.end(), policy.begin(),
114 (int(*)(int)) tolower);
115
116 //Assign commit policy
117 if (policy == "aggressive"){
118 commitPolicy = Aggressive;
119
120 DPRINTF(Commit,"Commit Policy set to Aggressive.\n");
121 } else if (policy == "roundrobin"){
122 commitPolicy = RoundRobin;
123
124 //Set-Up Priority List
125 for (ThreadID tid = 0; tid < numThreads; tid++) {
126 priority_list.push_back(tid);
127 }
128
129 DPRINTF(Commit,"Commit Policy set to Round Robin.\n");
130 } else if (policy == "oldestready"){
131 commitPolicy = OldestReady;
132
133 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
134 } else {
135 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
136 "RoundRobin,OldestReady}");
137 }
138
139 for (ThreadID tid = 0; tid < numThreads; tid++) {
140 commitStatus[tid] = Idle;
141 changedROBNumEntries[tid] = false;
142 checkEmptyROB[tid] = false;
143 trapInFlight[tid] = false;
144 committedStores[tid] = false;
145 trapSquash[tid] = false;
146 tcSquash[tid] = false;
147 pc[tid].set(0);
148 lastCommitedSeqNum[tid] = 0;
149 squashAfterInst[tid] = NULL;
150 }
151 interrupt = NoFault;
152}
153
154template <class Impl>
155std::string
156DefaultCommit<Impl>::name() const
157{
158 return cpu->name() + ".commit";
159}
160
161template <class Impl>
162void
163DefaultCommit<Impl>::regStats()
164{
165 using namespace Stats;
166 commitSquashedInsts
167 .name(name() + ".commitSquashedInsts")
168 .desc("The number of squashed insts skipped by commit")
169 .prereq(commitSquashedInsts);
170 commitSquashEvents
171 .name(name() + ".commitSquashEvents")
172 .desc("The number of times commit is told to squash")
173 .prereq(commitSquashEvents);
174 commitNonSpecStalls
175 .name(name() + ".commitNonSpecStalls")
176 .desc("The number of times commit has been forced to stall to "
177 "communicate backwards")
178 .prereq(commitNonSpecStalls);
179 branchMispredicts
180 .name(name() + ".branchMispredicts")
181 .desc("The number of times a branch was mispredicted")
182 .prereq(branchMispredicts);
183 numCommittedDist
184 .init(0,commitWidth,1)
185 .name(name() + ".committed_per_cycle")
186 .desc("Number of insts commited each cycle")
187 .flags(Stats::pdf)
188 ;
189
190 instsCommitted
191 .init(cpu->numThreads)
192 .name(name() + ".committedInsts")
193 .desc("Number of instructions committed")
194 .flags(total)
195 ;
196
197 opsCommitted
198 .init(cpu->numThreads)
199 .name(name() + ".committedOps")
200 .desc("Number of ops (including micro ops) committed")
201 .flags(total)
202 ;
203
204 statComSwp
205 .init(cpu->numThreads)
206 .name(name() + ".swp_count")
207 .desc("Number of s/w prefetches committed")
208 .flags(total)
209 ;
210
211 statComRefs
212 .init(cpu->numThreads)
213 .name(name() + ".refs")
214 .desc("Number of memory references committed")
215 .flags(total)
216 ;
217
218 statComLoads
219 .init(cpu->numThreads)
220 .name(name() + ".loads")
221 .desc("Number of loads committed")
222 .flags(total)
223 ;
224
225 statComMembars
226 .init(cpu->numThreads)
227 .name(name() + ".membars")
228 .desc("Number of memory barriers committed")
229 .flags(total)
230 ;
231
232 statComBranches
233 .init(cpu->numThreads)
234 .name(name() + ".branches")
235 .desc("Number of branches committed")
236 .flags(total)
237 ;
238
239 statComFloating
240 .init(cpu->numThreads)
241 .name(name() + ".fp_insts")
242 .desc("Number of committed floating point instructions.")
243 .flags(total)
244 ;
245
246 statComInteger
247 .init(cpu->numThreads)
248 .name(name()+".int_insts")
249 .desc("Number of committed integer instructions.")
250 .flags(total)
251 ;
252
253 statComFunctionCalls
254 .init(cpu->numThreads)
255 .name(name()+".function_calls")
256 .desc("Number of function calls committed.")
257 .flags(total)
258 ;
259
260 commitEligible
261 .init(cpu->numThreads)
262 .name(name() + ".bw_limited")
263 .desc("number of insts not committed due to BW limits")
264 .flags(total)
265 ;
266
267 commitEligibleSamples
268 .name(name() + ".bw_lim_events")
269 .desc("number cycles where commit BW limit reached")
270 ;
271}
272
273template <class Impl>
274void
275DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
276{
277 thread = threads;
278}
279
280template <class Impl>
281void
282DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
283{
284 timeBuffer = tb_ptr;
285
286 // Setup wire to send information back to IEW.
287 toIEW = timeBuffer->getWire(0);
288
289 // Setup wire to read data from IEW (for the ROB).
290 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
291}
292
293template <class Impl>
294void
295DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
296{
297 fetchQueue = fq_ptr;
298
299 // Setup wire to get instructions from rename (for the ROB).
300 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
301}
302
303template <class Impl>
304void
305DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
306{
307 renameQueue = rq_ptr;
308
309 // Setup wire to get instructions from rename (for the ROB).
310 fromRename = renameQueue->getWire(-renameToROBDelay);
311}
312
313template <class Impl>
314void
315DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
316{
317 iewQueue = iq_ptr;
318
319 // Setup wire to get instructions from IEW.
320 fromIEW = iewQueue->getWire(-iewToCommitDelay);
321}
322
323template <class Impl>
324void
325DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
326{
327 iewStage = iew_stage;
328}
329
330template<class Impl>
331void
332DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
333{
334 activeThreads = at_ptr;
335}
336
337template <class Impl>
338void
339DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
340{
341 for (ThreadID tid = 0; tid < numThreads; tid++)
342 renameMap[tid] = &rm_ptr[tid];
343}
344
345template <class Impl>
346void
347DefaultCommit<Impl>::setROB(ROB *rob_ptr)
348{
349 rob = rob_ptr;
350}
351
352template <class Impl>
353void
354DefaultCommit<Impl>::startupStage()
355{
356 rob->setActiveThreads(activeThreads);
357 rob->resetEntries();
358
359 // Broadcast the number of free entries.
360 for (ThreadID tid = 0; tid < numThreads; tid++) {
361 toIEW->commitInfo[tid].usedROB = true;
362 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
363 toIEW->commitInfo[tid].emptyROB = true;
364 }
365
366 // Commit must broadcast the number of free entries it has at the
367 // start of the simulation, so it starts as active.
368 cpu->activateStage(O3CPU::CommitIdx);
369
370 cpu->activityThisCycle();
371}
372
373template <class Impl>
374void
375DefaultCommit<Impl>::drain()
376{
377 drainPending = true;
378}
379
380template <class Impl>
381void
382DefaultCommit<Impl>::drainResume()
383{
384 drainPending = false;
385}
386
387template <class Impl>
388void
389DefaultCommit<Impl>::drainSanityCheck() const
390{
391 assert(isDrained());
392 rob->drainSanityCheck();
393}
394
395template <class Impl>
396bool
397DefaultCommit<Impl>::isDrained() const
398{
399 /* Make sure no one is executing microcode. There are two reasons
400 * for this:
401 * - Hardware virtualized CPUs can't switch into the middle of a
402 * microcode sequence.
403 * - The current fetch implementation will most likely get very
404 * confused if it tries to start fetching an instruction that
405 * is executing in the middle of a ucode sequence that changes
406 * address mappings. This can happen on for example x86.
407 */
408 for (ThreadID tid = 0; tid < numThreads; tid++) {
409 if (pc[tid].microPC() != 0)
410 return false;
411 }
412
413 /* Make sure that all instructions have finished committing before
414 * declaring the system as drained. We want the pipeline to be
415 * completely empty when we declare the CPU to be drained. This
416 * makes debugging easier since CPU handover and restoring from a
417 * checkpoint with a different CPU should have the same timing.
418 */
419 return rob->isEmpty() &&
420 interrupt == NoFault;
421}
422
423template <class Impl>
424void
425DefaultCommit<Impl>::takeOverFrom()
426{
427 _status = Active;
428 _nextStatus = Inactive;
429 for (ThreadID tid = 0; tid < numThreads; tid++) {
430 commitStatus[tid] = Idle;
431 changedROBNumEntries[tid] = false;
432 trapSquash[tid] = false;
433 tcSquash[tid] = false;
434 squashAfterInst[tid] = NULL;
435 }
436 squashCounter = 0;
437 rob->takeOverFrom();
438}
439
440template <class Impl>
441void
442DefaultCommit<Impl>::updateStatus()
443{
444 // reset ROB changed variable
445 list<ThreadID>::iterator threads = activeThreads->begin();
446 list<ThreadID>::iterator end = activeThreads->end();
447
448 while (threads != end) {
449 ThreadID tid = *threads++;
450
451 changedROBNumEntries[tid] = false;
452
453 // Also check if any of the threads has a trap pending
454 if (commitStatus[tid] == TrapPending ||
455 commitStatus[tid] == FetchTrapPending) {
456 _nextStatus = Active;
457 }
458 }
459
460 if (_nextStatus == Inactive && _status == Active) {
461 DPRINTF(Activity, "Deactivating stage.\n");
462 cpu->deactivateStage(O3CPU::CommitIdx);
463 } else if (_nextStatus == Active && _status == Inactive) {
464 DPRINTF(Activity, "Activating stage.\n");
465 cpu->activateStage(O3CPU::CommitIdx);
466 }
467
468 _status = _nextStatus;
469}
470
471template <class Impl>
472void
473DefaultCommit<Impl>::setNextStatus()
474{
475 int squashes = 0;
476
477 list<ThreadID>::iterator threads = activeThreads->begin();
478 list<ThreadID>::iterator end = activeThreads->end();
479
480 while (threads != end) {
481 ThreadID tid = *threads++;
482
483 if (commitStatus[tid] == ROBSquashing) {
484 squashes++;
485 }
486 }
487
488 squashCounter = squashes;
489
490 // If commit is currently squashing, then it will have activity for the
491 // next cycle. Set its next status as active.
492 if (squashCounter) {
493 _nextStatus = Active;
494 }
495}
496
497template <class Impl>
498bool
499DefaultCommit<Impl>::changedROBEntries()
500{
501 list<ThreadID>::iterator threads = activeThreads->begin();
502 list<ThreadID>::iterator end = activeThreads->end();
503
504 while (threads != end) {
505 ThreadID tid = *threads++;
506
507 if (changedROBNumEntries[tid]) {
508 return true;
509 }
510 }
511
512 return false;
513}
514
515template <class Impl>
516size_t
517DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
518{
519 return rob->numFreeEntries(tid);
520}
521
522template <class Impl>
523void
524DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
525{
526 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
527
528 TrapEvent *trap = new TrapEvent(this, tid);
529
530 cpu->schedule(trap, cpu->clockEdge(trapLatency));
531 trapInFlight[tid] = true;
532 thread[tid]->trapPending = true;
533}
534
535template <class Impl>
536void
537DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
538{
539 assert(!trapInFlight[tid]);
540 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
541
542 tcSquash[tid] = true;
543}
544
545template <class Impl>
546void
547DefaultCommit<Impl>::squashAll(ThreadID tid)
548{
549 // If we want to include the squashing instruction in the squash,
550 // then use one older sequence number.
551 // Hopefully this doesn't mess things up. Basically I want to squash
552 // all instructions of this thread.
553 InstSeqNum squashed_inst = rob->isEmpty() ?
554 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
555
556 // All younger instructions will be squashed. Set the sequence
557 // number as the youngest instruction in the ROB (0 in this case.
558 // Hopefully nothing breaks.)
559 youngestSeqNum[tid] = lastCommitedSeqNum[tid];
560
561 rob->squash(squashed_inst, tid);
562 changedROBNumEntries[tid] = true;
563
564 // Send back the sequence number of the squashed instruction.
565 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
566
567 // Send back the squash signal to tell stages that they should
568 // squash.
569 toIEW->commitInfo[tid].squash = true;
570
571 // Send back the rob squashing signal so other stages know that
572 // the ROB is in the process of squashing.
573 toIEW->commitInfo[tid].robSquashing = true;
574
575 toIEW->commitInfo[tid].mispredictInst = NULL;
576 toIEW->commitInfo[tid].squashInst = NULL;
577
578 toIEW->commitInfo[tid].pc = pc[tid];
579}
580
581template <class Impl>
582void
583DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
584{
585 squashAll(tid);
586
587 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
588
589 thread[tid]->trapPending = false;
590 thread[tid]->noSquashFromTC = false;
591 trapInFlight[tid] = false;
592
593 trapSquash[tid] = false;
594
595 commitStatus[tid] = ROBSquashing;
596 cpu->activityThisCycle();
597}
598
599template <class Impl>
600void
601DefaultCommit<Impl>::squashFromTC(ThreadID tid)
602{
603 squashAll(tid);
604
605 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
606
607 thread[tid]->noSquashFromTC = false;
608 assert(!thread[tid]->trapPending);
609
610 commitStatus[tid] = ROBSquashing;
611 cpu->activityThisCycle();
612
613 tcSquash[tid] = false;
614}
615
616template <class Impl>
617void
618DefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid)
619{
620 DPRINTF(Commit, "Squashing after squash after request, "
621 "restarting at PC %s\n", pc[tid]);
622
623 squashAll(tid);
624 // Make sure to inform the fetch stage of which instruction caused
625 // the squash. It'll try to re-fetch an instruction executing in
626 // microcode unless this is set.
627 toIEW->commitInfo[tid].squashInst = squashAfterInst[tid];
628 squashAfterInst[tid] = NULL;
629
630 commitStatus[tid] = ROBSquashing;
631 cpu->activityThisCycle();
632}
633
634template <class Impl>
635void
636DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst)
637{
638 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
639 tid, head_inst->seqNum);
640
641 assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst);
642 commitStatus[tid] = SquashAfterPending;
643 squashAfterInst[tid] = head_inst;
644}
645
646template <class Impl>
647void
648DefaultCommit<Impl>::tick()
649{
650 wroteToTimeBuffer = false;
651 _nextStatus = Inactive;
652
653 if (activeThreads->empty())
654 return;
655
656 list<ThreadID>::iterator threads = activeThreads->begin();
657 list<ThreadID>::iterator end = activeThreads->end();
658
659 // Check if any of the threads are done squashing. Change the
660 // status if they are done.
661 while (threads != end) {
662 ThreadID tid = *threads++;
663
664 // Clear the bit saying if the thread has committed stores
665 // this cycle.
666 committedStores[tid] = false;
667
668 if (commitStatus[tid] == ROBSquashing) {
669
670 if (rob->isDoneSquashing(tid)) {
671 commitStatus[tid] = Running;
672 } else {
673 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
674 " insts this cycle.\n", tid);
675 rob->doSquash(tid);
676 toIEW->commitInfo[tid].robSquashing = true;
677 wroteToTimeBuffer = true;
678 }
679 }
680 }
681
682 commit();
683
684 markCompletedInsts();
685
686 threads = activeThreads->begin();
687
688 while (threads != end) {
689 ThreadID tid = *threads++;
690
691 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
692 // The ROB has more instructions it can commit. Its next status
693 // will be active.
694 _nextStatus = Active;
695
696 DynInstPtr inst = rob->readHeadInst(tid);
697
698 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
699 " ROB and ready to commit\n",
700 tid, inst->seqNum, inst->pcState());
701
702 } else if (!rob->isEmpty(tid)) {
703 DynInstPtr inst = rob->readHeadInst(tid);
704
705 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
706 "%s is head of ROB and not ready\n",
707 tid, inst->seqNum, inst->pcState());
708 }
709
710 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
711 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
712 }
713
714
715 if (wroteToTimeBuffer) {
716 DPRINTF(Activity, "Activity This Cycle.\n");
717 cpu->activityThisCycle();
718 }
719
720 updateStatus();
721}
722
723template <class Impl>
724void
725DefaultCommit<Impl>::handleInterrupt()
726{
727 // Verify that we still have an interrupt to handle
728 if (!cpu->checkInterrupts(cpu->tcBase(0))) {
729 DPRINTF(Commit, "Pending interrupt is cleared by master before "
730 "it got handled. Restart fetching from the orig path.\n");
731 toIEW->commitInfo[0].clearInterrupt = true;
732 interrupt = NoFault;
733 avoidQuiesceLiveLock = true;
734 return;
735 }
736
737 // Wait until all in flight instructions are finished before enterring
738 // the interrupt.
739 if (canHandleInterrupts && cpu->instList.empty()) {
740 // Squash or record that I need to squash this cycle if
741 // an interrupt needed to be handled.
742 DPRINTF(Commit, "Interrupt detected.\n");
743
744 // Clear the interrupt now that it's going to be handled
745 toIEW->commitInfo[0].clearInterrupt = true;
746
747 assert(!thread[0]->noSquashFromTC);
748 thread[0]->noSquashFromTC = true;
749
750 if (cpu->checker) {
751 cpu->checker->handlePendingInt();
752 }
753
754 // CPU will handle interrupt.
755 cpu->processInterrupts(interrupt);
756
757 thread[0]->noSquashFromTC = false;
758
759 commitStatus[0] = TrapPending;
760
761 // Generate trap squash event.
762 generateTrapEvent(0);
763
764 interrupt = NoFault;
765 avoidQuiesceLiveLock = false;
766 } else {
767 DPRINTF(Commit, "Interrupt pending: instruction is %sin "
768 "flight, ROB is %sempty\n",
769 canHandleInterrupts ? "not " : "",
770 cpu->instList.empty() ? "" : "not " );
771 }
772}
773
774template <class Impl>
775void
776DefaultCommit<Impl>::propagateInterrupt()
777{
778 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
779 tcSquash[0])
780 return;
781
782 // Process interrupts if interrupts are enabled, not in PAL
783 // mode, and no other traps or external squashes are currently
784 // pending.
785 // @todo: Allow other threads to handle interrupts.
786
787 // Get any interrupt that happened
788 interrupt = cpu->getInterrupts();
789
790 // Tell fetch that there is an interrupt pending. This
791 // will make fetch wait until it sees a non PAL-mode PC,
792 // at which point it stops fetching instructions.
793 if (interrupt != NoFault)
794 toIEW->commitInfo[0].interruptPending = true;
795}
796
797template <class Impl>
798void
799DefaultCommit<Impl>::commit()
800{
801 if (FullSystem) {
802 // Check if we have a interrupt and get read to handle it
803 if (cpu->checkInterrupts(cpu->tcBase(0)))
804 propagateInterrupt();
805 }
806
807 ////////////////////////////////////
808 // Check for any possible squashes, handle them first
809 ////////////////////////////////////
810 list<ThreadID>::iterator threads = activeThreads->begin();
811 list<ThreadID>::iterator end = activeThreads->end();
812
813 while (threads != end) {
814 ThreadID tid = *threads++;
815
816 // Not sure which one takes priority. I think if we have
817 // both, that's a bad sign.
818 if (trapSquash[tid] == true) {
819 assert(!tcSquash[tid]);
820 squashFromTrap(tid);
821 } else if (tcSquash[tid] == true) {
822 assert(commitStatus[tid] != TrapPending);
823 squashFromTC(tid);
824 } else if (commitStatus[tid] == SquashAfterPending) {
825 // A squash from the previous cycle of the commit stage (i.e.,
826 // commitInsts() called squashAfter) is pending. Squash the
827 // thread now.
828 squashFromSquashAfter(tid);
829 }
830
831 // Squashed sequence number must be older than youngest valid
832 // instruction in the ROB. This prevents squashes from younger
833 // instructions overriding squashes from older instructions.
834 if (fromIEW->squash[tid] &&
835 commitStatus[tid] != TrapPending &&
836 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
837
838 if (fromIEW->mispredictInst[tid]) {
839 DPRINTF(Commit,
840 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
841 tid,
842 fromIEW->mispredictInst[tid]->instAddr(),
843 fromIEW->squashedSeqNum[tid]);
844 } else {
845 DPRINTF(Commit,
846 "[tid:%i]: Squashing due to order violation [sn:%i]\n",
847 tid, fromIEW->squashedSeqNum[tid]);
848 }
849
850 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
851 tid,
852 fromIEW->pc[tid].nextInstAddr());
853
854 commitStatus[tid] = ROBSquashing;
855
856 // If we want to include the squashing instruction in the squash,
857 // then use one older sequence number.
858 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
859
860 if (fromIEW->includeSquashInst[tid] == true) {
861 squashed_inst--;
862 }
863
864 // All younger instructions will be squashed. Set the sequence
865 // number as the youngest instruction in the ROB.
866 youngestSeqNum[tid] = squashed_inst;
867
868 rob->squash(squashed_inst, tid);
869 changedROBNumEntries[tid] = true;
870
871 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
872
873 toIEW->commitInfo[tid].squash = true;
874
875 // Send back the rob squashing signal so other stages know that
876 // the ROB is in the process of squashing.
877 toIEW->commitInfo[tid].robSquashing = true;
878
879 toIEW->commitInfo[tid].mispredictInst =
880 fromIEW->mispredictInst[tid];
881 toIEW->commitInfo[tid].branchTaken =
882 fromIEW->branchTaken[tid];
883 toIEW->commitInfo[tid].squashInst =
884 rob->findInst(tid, squashed_inst);
885 if (toIEW->commitInfo[tid].mispredictInst) {
886 if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) {
887 toIEW->commitInfo[tid].branchTaken = true;
888 }
889 }
890
891 toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
892
893 if (toIEW->commitInfo[tid].mispredictInst) {
894 ++branchMispredicts;
895 }
896 }
897
898 }
899
900 setNextStatus();
901
902 if (squashCounter != numThreads) {
903 // If we're not currently squashing, then get instructions.
904 getInsts();
905
906 // Try to commit any instructions.
907 commitInsts();
908 }
909
910 //Check for any activity
911 threads = activeThreads->begin();
912
913 while (threads != end) {
914 ThreadID tid = *threads++;
915
916 if (changedROBNumEntries[tid]) {
917 toIEW->commitInfo[tid].usedROB = true;
918 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
919
920 wroteToTimeBuffer = true;
921 changedROBNumEntries[tid] = false;
922 if (rob->isEmpty(tid))
923 checkEmptyROB[tid] = true;
924 }
925
926 // ROB is only considered "empty" for previous stages if: a)
927 // ROB is empty, b) there are no outstanding stores, c) IEW
928 // stage has received any information regarding stores that
929 // committed.
930 // c) is checked by making sure to not consider the ROB empty
931 // on the same cycle as when stores have been committed.
932 // @todo: Make this handle multi-cycle communication between
933 // commit and IEW.
934 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
935 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
936 checkEmptyROB[tid] = false;
937 toIEW->commitInfo[tid].usedROB = true;
938 toIEW->commitInfo[tid].emptyROB = true;
939 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
940 wroteToTimeBuffer = true;
941 }
942
943 }
944}
945
946template <class Impl>
947void
948DefaultCommit<Impl>::commitInsts()
949{
950 ////////////////////////////////////
951 // Handle commit
952 // Note that commit will be handled prior to putting new
953 // instructions in the ROB so that the ROB only tries to commit
954 // instructions it has in this current cycle, and not instructions
955 // it is writing in during this cycle. Can't commit and squash
956 // things at the same time...
957 ////////////////////////////////////
958
959 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
960
961 unsigned num_committed = 0;
962
963 DynInstPtr head_inst;
964
965 // Commit as many instructions as possible until the commit bandwidth
966 // limit is reached, or it becomes impossible to commit any more.
967 while (num_committed < commitWidth) {
968 // Check for any interrupt that we've already squashed for
969 // and start processing it.
970 if (interrupt != NoFault)
971 handleInterrupt();
972
973 int commit_thread = getCommittingThread();
974
975 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
976 break;
977
978 head_inst = rob->readHeadInst(commit_thread);
979
980 ThreadID tid = head_inst->threadNumber;
981
982 assert(tid == commit_thread);
983
984 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
985 head_inst->seqNum, tid);
986
987 // If the head instruction is squashed, it is ready to retire
988 // (be removed from the ROB) at any time.
989 if (head_inst->isSquashed()) {
990
991 DPRINTF(Commit, "Retiring squashed instruction from "
992 "ROB.\n");
993
994 rob->retireHead(commit_thread);
995
996 ++commitSquashedInsts;
997
998 // Record that the number of ROB entries has changed.
999 changedROBNumEntries[tid] = true;
1000 } else {
1001 pc[tid] = head_inst->pcState();
1002
1003 // Increment the total number of non-speculative instructions
1004 // executed.
1005 // Hack for now: it really shouldn't happen until after the
1006 // commit is deemed to be successful, but this count is needed
1007 // for syscalls.
1008 thread[tid]->funcExeInst++;
1009
1010 // Try to commit the head instruction.
1011 bool commit_success = commitHead(head_inst, num_committed);
1012
1013 if (commit_success) {
1014 ++num_committed;
1015
1016 changedROBNumEntries[tid] = true;
1017
1018 // Set the doneSeqNum to the youngest committed instruction.
1019 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
1020
1021 if (tid == 0) {
1022 canHandleInterrupts = (!head_inst->isDelayedCommit()) &&
1023 ((THE_ISA != ALPHA_ISA) ||
1024 (!(pc[0].instAddr() & 0x3)));
1025 }
1026
1027 // Updates misc. registers.
1028 head_inst->updateMiscRegs();
1029
1030 cpu->traceFunctions(pc[tid].instAddr());
1031
1032 TheISA::advancePC(pc[tid], head_inst->staticInst);
1033
1034 // Keep track of the last sequence number commited
1035 lastCommitedSeqNum[tid] = head_inst->seqNum;
1036
1037 // If this is an instruction that doesn't play nicely with
1038 // others squash everything and restart fetch
1039 if (head_inst->isSquashAfter())
1040 squashAfter(tid, head_inst);
1041
1042 if (drainPending) {
1043 DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]);
1044 if (pc[tid].microPC() == 0 && interrupt == NoFault) {
1045 squashAfter(tid, head_inst);
1046 cpu->commitDrained(tid);
1047 }
1048 }
1049
1050 int count = 0;
1051 Addr oldpc;
1052 // Debug statement. Checks to make sure we're not
1053 // currently updating state while handling PC events.
1054 assert(!thread[tid]->noSquashFromTC && !thread[tid]->trapPending);
1055 do {
1056 oldpc = pc[tid].instAddr();
1057 cpu->system->pcEventQueue.service(thread[tid]->getTC());
1058 count++;
1059 } while (oldpc != pc[tid].instAddr());
1060 if (count > 1) {
1061 DPRINTF(Commit,
1062 "PC skip function event, stopping commit\n");
1063 break;
1064 }
1065
1066 // Check if an instruction just enabled interrupts and we've
1067 // previously had an interrupt pending that was not handled
1068 // because interrupts were subsequently disabled before the
1069 // pipeline reached a place to handle the interrupt. In that
1070 // case squash now to make sure the interrupt is handled.
1071 //
1072 // If we don't do this, we might end up in a live lock situation
1073 if (!interrupt && avoidQuiesceLiveLock &&
1074 (!head_inst->isMicroop() || head_inst->isLastMicroop()) &&
1075 cpu->checkInterrupts(cpu->tcBase(0)))
1076 squashAfter(tid, head_inst);
1077 } else {
1078 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1079 "[tid:%i] [sn:%i].\n",
1080 head_inst->pcState(), tid ,head_inst->seqNum);
1081 break;
1082 }
1083 }
1084 }
1085
1086 DPRINTF(CommitRate, "%i\n", num_committed);
1087 numCommittedDist.sample(num_committed);
1088
1089 if (num_committed == commitWidth) {
1090 commitEligibleSamples++;
1091 }
1092}
1093
1094template <class Impl>
1095bool
1096DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1097{
1098 assert(head_inst);
1099
1100 ThreadID tid = head_inst->threadNumber;
1101
1102 // If the instruction is not executed yet, then it will need extra
1103 // handling. Signal backwards that it should be executed.
1104 if (!head_inst->isExecuted()) {
1105 // Keep this number correct. We have not yet actually executed
1106 // and committed this instruction.
1107 thread[tid]->funcExeInst--;
1108
1109 if (head_inst->isNonSpeculative() ||
1110 head_inst->isStoreConditional() ||
1111 head_inst->isMemBarrier() ||
1112 head_inst->isWriteBarrier()) {
1113
1114 DPRINTF(Commit, "Encountered a barrier or non-speculative "
1115 "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1116 head_inst->seqNum, head_inst->pcState());
1117
1118 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1119 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1120 return false;
1121 }
1122
1123 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1124
1125 // Change the instruction so it won't try to commit again until
1126 // it is executed.
1127 head_inst->clearCanCommit();
1128
1129 ++commitNonSpecStalls;
1130
1131 return false;
1132 } else if (head_inst->isLoad()) {
1133 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1134 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1135 return false;
1136 }
1137
1138 assert(head_inst->uncacheable());
1139 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
1140 head_inst->seqNum, head_inst->pcState());
1141
1142 // Send back the non-speculative instruction's sequence
1143 // number. Tell the lsq to re-execute the load.
1144 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1145 toIEW->commitInfo[tid].uncached = true;
1146 toIEW->commitInfo[tid].uncachedLoad = head_inst;
1147
1148 head_inst->clearCanCommit();
1149
1150 return false;
1151 } else {
1152 panic("Trying to commit un-executed instruction "
1153 "of unknown type!\n");
1154 }
1155 }
1156
1157 if (head_inst->isThreadSync()) {
1158 // Not handled for now.
1159 panic("Thread sync instructions are not handled yet.\n");
1160 }
1161
1162 // Check if the instruction caused a fault. If so, trap.
1163 Fault inst_fault = head_inst->getFault();
1164
1165 // Stores mark themselves as completed.
1166 if (!head_inst->isStore() && inst_fault == NoFault) {
1167 head_inst->setCompleted();
1168 }
1169
1170 // Use checker prior to updating anything due to traps or PC
1171 // based events.
1172 if (cpu->checker) {
1173 cpu->checker->verify(head_inst);
1174 }
1175
1176 if (inst_fault != NoFault) {
1177 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1178 head_inst->seqNum, head_inst->pcState());
1179
1180 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1181 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1182 return false;
1183 }
1184
1185 head_inst->setCompleted();
1186
1187 if (cpu->checker) {
1188 // Need to check the instruction before its fault is processed
1189 cpu->checker->verify(head_inst);
1190 }
1191
1192 assert(!thread[tid]->noSquashFromTC);
1193
1194 // Mark that we're in state update mode so that the trap's
1195 // execution doesn't generate extra squashes.
1196 thread[tid]->noSquashFromTC = true;
1197
1198 // Execute the trap. Although it's slightly unrealistic in
1199 // terms of timing (as it doesn't wait for the full timing of
1200 // the trap event to complete before updating state), it's
1201 // needed to update the state as soon as possible. This
1202 // prevents external agents from changing any specific state
1203 // that the trap need.
1204 cpu->trap(inst_fault, tid, head_inst->staticInst);
1205
1206 // Exit state update mode to avoid accidental updating.
1207 thread[tid]->noSquashFromTC = false;
1208
1209 commitStatus[tid] = TrapPending;
1210
1211 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1212 head_inst->seqNum);
1213 if (head_inst->traceData) {
1214 if (DTRACE(ExecFaulting)) {
1215 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1216 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1217 head_inst->traceData->dump();
1218 }
1219 delete head_inst->traceData;
1220 head_inst->traceData = NULL;
1221 }
1222
1223 // Generate trap squash event.
1224 generateTrapEvent(tid);
1225 return false;
1226 }
1227
1228 updateComInstStats(head_inst);
1229
1230 if (FullSystem) {
1231 if (thread[tid]->profile) {
1232 thread[tid]->profilePC = head_inst->instAddr();
1233 ProfileNode *node = thread[tid]->profile->consume(
1234 thread[tid]->getTC(), head_inst->staticInst);
1235
1236 if (node)
1237 thread[tid]->profileNode = node;
1238 }
1239 if (CPA::available()) {
1240 if (head_inst->isControl()) {
1241 ThreadContext *tc = thread[tid]->getTC();
1242 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1243 }
1244 }
1245 }
1246 DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
1247 head_inst->seqNum, head_inst->pcState());
1248 if (head_inst->traceData) {
1249 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1250 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1251 head_inst->traceData->dump();
1252 delete head_inst->traceData;
1253 head_inst->traceData = NULL;
1254 }
1255 if (head_inst->isReturn()) {
1256 DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n",
1257 head_inst->seqNum, head_inst->pcState());
1258 }
1259
1260 // Update the commit rename map
1261 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1262 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1263 head_inst->renamedDestRegIdx(i));
1264 }
1265
1266 // Finally clear the head ROB entry.
1267 rob->retireHead(tid);
1268
1269#if TRACING_ON
1270 head_inst->commitTick = curTick() - head_inst->fetchTick;
1271#endif
1272
1273 // If this was a store, record it for this cycle.
1274 if (head_inst->isStore())
1275 committedStores[tid] = true;
1276
1277 // Return true to indicate that we have committed an instruction.
1278 return true;
1279}
1280
1281template <class Impl>
1282void
1283DefaultCommit<Impl>::getInsts()
1284{
1285 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1286
1287 // Read any renamed instructions and place them into the ROB.
1288 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1289
1290 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1291 DynInstPtr inst;
1292
1293 inst = fromRename->insts[inst_num];
1294 ThreadID tid = inst->threadNumber;
1295
1296 if (!inst->isSquashed() &&
1297 commitStatus[tid] != ROBSquashing &&
1298 commitStatus[tid] != TrapPending) {
1299 changedROBNumEntries[tid] = true;
1300
1301 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1302 inst->pcState(), inst->seqNum, tid);
1303
1304 rob->insertInst(inst);
1305
1306 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1307
1308 youngestSeqNum[tid] = inst->seqNum;
1309 } else {
1310 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1311 "squashed, skipping.\n",
1312 inst->pcState(), inst->seqNum, tid);
1313 }
1314 }
1315}
1316
1317template <class Impl>
1318void
1319DefaultCommit<Impl>::skidInsert()
1320{
1321 DPRINTF(Commit, "Attempting to any instructions from rename into "
1322 "skidBuffer.\n");
1323
1324 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1325 DynInstPtr inst = fromRename->insts[inst_num];
1326
1327 if (!inst->isSquashed()) {
1328 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1329 "skidBuffer.\n", inst->pcState(), inst->seqNum,
1330 inst->threadNumber);
1331 skidBuffer.push(inst);
1332 } else {
1333 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1334 "squashed, skipping.\n",
1335 inst->pcState(), inst->seqNum, inst->threadNumber);
1336 }
1337 }
1338}
1339
1340template <class Impl>
1341void
1342DefaultCommit<Impl>::markCompletedInsts()
1343{
1344 // Grab completed insts out of the IEW instruction queue, and mark
1345 // instructions completed within the ROB.
1346 for (int inst_num = 0;
1347 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1348 ++inst_num)
1349 {
1350 if (!fromIEW->insts[inst_num]->isSquashed()) {
1351 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1352 "within ROB.\n",
1353 fromIEW->insts[inst_num]->threadNumber,
1354 fromIEW->insts[inst_num]->pcState(),
1355 fromIEW->insts[inst_num]->seqNum);
1356
1357 // Mark the instruction as ready to commit.
1358 fromIEW->insts[inst_num]->setCanCommit();
1359 }
1360 }
1361}
1362
1363template <class Impl>
1364bool
1365DefaultCommit<Impl>::robDoneSquashing()
1366{
1367 list<ThreadID>::iterator threads = activeThreads->begin();
1368 list<ThreadID>::iterator end = activeThreads->end();
1369
1370 while (threads != end) {
1371 ThreadID tid = *threads++;
1372
1373 if (!rob->isDoneSquashing(tid))
1374 return false;
1375 }
1376
1377 return true;
1378}
1379
1380template <class Impl>
1381void
1382DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1383{
1384 ThreadID tid = inst->threadNumber;
1385
1386 if (!inst->isMicroop() || inst->isLastMicroop())
1387 instsCommitted[tid]++;
1388 opsCommitted[tid]++;
1389
1390 // To match the old model, don't count nops and instruction
1391 // prefetches towards the total commit count.
1392 if (!inst->isNop() && !inst->isInstPrefetch()) {
1393 cpu->instDone(tid, inst);
1394 }
1395
1396 //
1397 // Control Instructions
1398 //
1399 if (inst->isControl())
1400 statComBranches[tid]++;
1401
1402 //
1403 // Memory references
1404 //
1405 if (inst->isMemRef()) {
1406 statComRefs[tid]++;
1407
1408 if (inst->isLoad()) {
1409 statComLoads[tid]++;
1410 }
1411 }
1412
1413 if (inst->isMemBarrier()) {
1414 statComMembars[tid]++;
1415 }
1416
1417 // Integer Instruction
1418 if (inst->isInteger())
1419 statComInteger[tid]++;
1420
1421 // Floating Point Instruction
1422 if (inst->isFloating())
1423 statComFloating[tid]++;
1424
1425 // Function Calls
1426 if (inst->isCall())
1427 statComFunctionCalls[tid]++;
1428
1429}
1430
1431////////////////////////////////////////
1432// //
1433// SMT COMMIT POLICY MAINTAINED HERE //
1434// //
1435////////////////////////////////////////
1436template <class Impl>
1437ThreadID
1438DefaultCommit<Impl>::getCommittingThread()
1439{
1440 if (numThreads > 1) {
1441 switch (commitPolicy) {
1442
1443 case Aggressive:
1444 //If Policy is Aggressive, commit will call
1445 //this function multiple times per
1446 //cycle
1447 return oldestReady();
1448
1449 case RoundRobin:
1450 return roundRobin();
1451
1452 case OldestReady:
1453 return oldestReady();
1454
1455 default:
1456 return InvalidThreadID;
1457 }
1458 } else {
1459 assert(!activeThreads->empty());
1460 ThreadID tid = activeThreads->front();
1461
1462 if (commitStatus[tid] == Running ||
1463 commitStatus[tid] == Idle ||
1464 commitStatus[tid] == FetchTrapPending) {
1465 return tid;
1466 } else {
1467 return InvalidThreadID;
1468 }
1469 }
1470}
1471
1472template<class Impl>
1473ThreadID
1474DefaultCommit<Impl>::roundRobin()
1475{
1476 list<ThreadID>::iterator pri_iter = priority_list.begin();
1477 list<ThreadID>::iterator end = priority_list.end();
1478
1479 while (pri_iter != end) {
1480 ThreadID tid = *pri_iter;
1481
1482 if (commitStatus[tid] == Running ||
1483 commitStatus[tid] == Idle ||
1484 commitStatus[tid] == FetchTrapPending) {
1485
1486 if (rob->isHeadReady(tid)) {
1487 priority_list.erase(pri_iter);
1488 priority_list.push_back(tid);
1489
1490 return tid;
1491 }
1492 }
1493
1494 pri_iter++;
1495 }
1496
1497 return InvalidThreadID;
1498}
1499
1500template<class Impl>
1501ThreadID
1502DefaultCommit<Impl>::oldestReady()
1503{
1504 unsigned oldest = 0;
1505 bool first = true;
1506
1507 list<ThreadID>::iterator threads = activeThreads->begin();
1508 list<ThreadID>::iterator end = activeThreads->end();
1509
1510 while (threads != end) {
1511 ThreadID tid = *threads++;
1512
1513 if (!rob->isEmpty(tid) &&
1514 (commitStatus[tid] == Running ||
1515 commitStatus[tid] == Idle ||
1516 commitStatus[tid] == FetchTrapPending)) {
1517
1518 if (rob->isHeadReady(tid)) {
1519
1520 DynInstPtr head_inst = rob->readHeadInst(tid);
1521
1522 if (first) {
1523 oldest = tid;
1524 first = false;
1525 } else if (head_inst->seqNum < oldest) {
1526 oldest = tid;
1527 }
1528 }
1529 }
1530 }
1531
1532 if (!first) {
1533 return oldest;
1534 } else {
1535 return InvalidThreadID;
1536 }
1537}