1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#include <algorithm>
45#include <string>
46
47#include "arch/utility.hh"
48#include "base/loader/symtab.hh"
49#include "base/cp_annotate.hh"
50#include "config/full_system.hh"
51#include "config/the_isa.hh"
52#include "config/use_checker.hh"
53#include "cpu/o3/commit.hh"
54#include "cpu/o3/thread_state.hh"
55#include "cpu/exetrace.hh"
56#include "cpu/timebuf.hh"
57#include "debug/Activity.hh"
58#include "debug/Commit.hh"
59#include "debug/CommitRate.hh"
60#include "debug/ExecFaulting.hh"
61#include "debug/O3PipeView.hh"
62#include "params/DerivO3CPU.hh"
63#include "sim/faults.hh"
64
65#if USE_CHECKER
66#include "cpu/checker/cpu.hh"
67#endif
68
69using namespace std;
70
71template <class Impl>
72DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
73 ThreadID _tid)
74 : Event(CPU_Tick_Pri), commit(_commit), tid(_tid)
75{
76 this->setFlags(AutoDelete);
77}
78
79template <class Impl>
80void
81DefaultCommit<Impl>::TrapEvent::process()
82{
83 // This will get reset by commit if it was switched out at the
84 // time of this event processing.
85 commit->trapSquash[tid] = true;
86}
87
88template <class Impl>
89const char *
90DefaultCommit<Impl>::TrapEvent::description() const
91{
92 return "Trap";
93}
94
95template <class Impl>
96DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
97 : cpu(_cpu),
98 squashCounter(0),
99 iewToCommitDelay(params->iewToCommitDelay),
100 commitToIEWDelay(params->commitToIEWDelay),
101 renameToROBDelay(params->renameToROBDelay),
102 fetchToCommitDelay(params->commitToFetchDelay),
103 renameWidth(params->renameWidth),
104 commitWidth(params->commitWidth),
105 numThreads(params->numThreads),
106 drainPending(false),
107 switchedOut(false),
108 trapLatency(params->trapLatency)
109{
110 _status = Active;
111 _nextStatus = Inactive;
112 std::string policy = params->smtCommitPolicy;
113
114 //Convert string to lowercase
115 std::transform(policy.begin(), policy.end(), policy.begin(),
116 (int(*)(int)) tolower);
117
118 //Assign commit policy
119 if (policy == "aggressive"){
120 commitPolicy = Aggressive;
121
122 DPRINTF(Commit,"Commit Policy set to Aggressive.\n");
123 } else if (policy == "roundrobin"){
124 commitPolicy = RoundRobin;
125
126 //Set-Up Priority List
127 for (ThreadID tid = 0; tid < numThreads; tid++) {
128 priority_list.push_back(tid);
129 }
130
131 DPRINTF(Commit,"Commit Policy set to Round Robin.\n");
132 } else if (policy == "oldestready"){
133 commitPolicy = OldestReady;
134
135 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
136 } else {
137 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
138 "RoundRobin,OldestReady}");
139 }
140
141 for (ThreadID tid = 0; tid < numThreads; tid++) {
142 commitStatus[tid] = Idle;
143 changedROBNumEntries[tid] = false;
144 checkEmptyROB[tid] = false;
145 trapInFlight[tid] = false;
146 committedStores[tid] = false;
147 trapSquash[tid] = false;
148 tcSquash[tid] = false;
149 pc[tid].set(0);
150 lastCommitedSeqNum[tid] = 0;
151 }
152#if FULL_SYSTEM
153 interrupt = NoFault;
154#endif
155}
156
157template <class Impl>
158std::string
159DefaultCommit<Impl>::name() const
160{
161 return cpu->name() + ".commit";
162}
163
164template <class Impl>
165void
166DefaultCommit<Impl>::regStats()
167{
168 using namespace Stats;
169 commitCommittedInsts
170 .name(name() + ".commitCommittedInsts")
171 .desc("The number of committed instructions")
172 .prereq(commitCommittedInsts);
173 commitSquashedInsts
174 .name(name() + ".commitSquashedInsts")
175 .desc("The number of squashed insts skipped by commit")
176 .prereq(commitSquashedInsts);
177 commitSquashEvents
178 .name(name() + ".commitSquashEvents")
179 .desc("The number of times commit is told to squash")
180 .prereq(commitSquashEvents);
181 commitNonSpecStalls
182 .name(name() + ".commitNonSpecStalls")
183 .desc("The number of times commit has been forced to stall to "
184 "communicate backwards")
185 .prereq(commitNonSpecStalls);
186 branchMispredicts
187 .name(name() + ".branchMispredicts")
188 .desc("The number of times a branch was mispredicted")
189 .prereq(branchMispredicts);
190 numCommittedDist
191 .init(0,commitWidth,1)
192 .name(name() + ".committed_per_cycle")
193 .desc("Number of insts commited each cycle")
194 .flags(Stats::pdf)
195 ;
196
197 statComInst
198 .init(cpu->numThreads)
199 .name(name() + ".count")
200 .desc("Number of instructions committed")
201 .flags(total)
202 ;
203
204 statComSwp
205 .init(cpu->numThreads)
206 .name(name() + ".swp_count")
207 .desc("Number of s/w prefetches committed")
208 .flags(total)
209 ;
210
211 statComRefs
212 .init(cpu->numThreads)
213 .name(name() + ".refs")
214 .desc("Number of memory references committed")
215 .flags(total)
216 ;
217
218 statComLoads
219 .init(cpu->numThreads)
220 .name(name() + ".loads")
221 .desc("Number of loads committed")
222 .flags(total)
223 ;
224
225 statComMembars
226 .init(cpu->numThreads)
227 .name(name() + ".membars")
228 .desc("Number of memory barriers committed")
229 .flags(total)
230 ;
231
232 statComBranches
233 .init(cpu->numThreads)
234 .name(name() + ".branches")
235 .desc("Number of branches committed")
236 .flags(total)
237 ;
238
239 statComFloating
240 .init(cpu->numThreads)
241 .name(name() + ".fp_insts")
242 .desc("Number of committed floating point instructions.")
243 .flags(total)
244 ;
245
246 statComInteger
247 .init(cpu->numThreads)
248 .name(name()+".int_insts")
249 .desc("Number of committed integer instructions.")
250 .flags(total)
251 ;
252
253 statComFunctionCalls
254 .init(cpu->numThreads)
255 .name(name()+".function_calls")
256 .desc("Number of function calls committed.")
257 .flags(total)
258 ;
259
260 commitEligible
261 .init(cpu->numThreads)
262 .name(name() + ".bw_limited")
263 .desc("number of insts not committed due to BW limits")
264 .flags(total)
265 ;
266
267 commitEligibleSamples
268 .name(name() + ".bw_lim_events")
269 .desc("number cycles where commit BW limit reached")
270 ;
271}
272
273template <class Impl>
274void
275DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
276{
277 thread = threads;
278}
279
280template <class Impl>
281void
282DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
283{
284 timeBuffer = tb_ptr;
285
286 // Setup wire to send information back to IEW.
287 toIEW = timeBuffer->getWire(0);
288
289 // Setup wire to read data from IEW (for the ROB).
290 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
291}
292
293template <class Impl>
294void
295DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
296{
297 fetchQueue = fq_ptr;
298
299 // Setup wire to get instructions from rename (for the ROB).
300 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
301}
302
303template <class Impl>
304void
305DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
306{
307 renameQueue = rq_ptr;
308
309 // Setup wire to get instructions from rename (for the ROB).
310 fromRename = renameQueue->getWire(-renameToROBDelay);
311}
312
313template <class Impl>
314void
315DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
316{
317 iewQueue = iq_ptr;
318
319 // Setup wire to get instructions from IEW.
320 fromIEW = iewQueue->getWire(-iewToCommitDelay);
321}
322
323template <class Impl>
324void
325DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
326{
327 iewStage = iew_stage;
328}
329
330template<class Impl>
331void
332DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
333{
334 activeThreads = at_ptr;
335}
336
337template <class Impl>
338void
339DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
340{
341 for (ThreadID tid = 0; tid < numThreads; tid++)
342 renameMap[tid] = &rm_ptr[tid];
343}
344
345template <class Impl>
346void
347DefaultCommit<Impl>::setROB(ROB *rob_ptr)
348{
349 rob = rob_ptr;
350}
351
352template <class Impl>
353void
354DefaultCommit<Impl>::initStage()
355{
356 rob->setActiveThreads(activeThreads);
357 rob->resetEntries();
358
359 // Broadcast the number of free entries.
360 for (ThreadID tid = 0; tid < numThreads; tid++) {
361 toIEW->commitInfo[tid].usedROB = true;
362 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
363 toIEW->commitInfo[tid].emptyROB = true;
364 }
365
366 // Commit must broadcast the number of free entries it has at the
367 // start of the simulation, so it starts as active.
368 cpu->activateStage(O3CPU::CommitIdx);
369
370 cpu->activityThisCycle();
371 trapLatency = cpu->ticks(trapLatency);
372}
373
374template <class Impl>
375bool
376DefaultCommit<Impl>::drain()
377{
378 drainPending = true;
379
380 return false;
381}
382
383template <class Impl>
384void
385DefaultCommit<Impl>::switchOut()
386{
387 switchedOut = true;
388 drainPending = false;
389 rob->switchOut();
390}
391
392template <class Impl>
393void
394DefaultCommit<Impl>::resume()
395{
396 drainPending = false;
397}
398
399template <class Impl>
400void
401DefaultCommit<Impl>::takeOverFrom()
402{
403 switchedOut = false;
404 _status = Active;
405 _nextStatus = Inactive;
406 for (ThreadID tid = 0; tid < numThreads; tid++) {
407 commitStatus[tid] = Idle;
408 changedROBNumEntries[tid] = false;
409 trapSquash[tid] = false;
410 tcSquash[tid] = false;
411 }
412 squashCounter = 0;
413 rob->takeOverFrom();
414}
415
416template <class Impl>
417void
418DefaultCommit<Impl>::updateStatus()
419{
420 // reset ROB changed variable
421 list<ThreadID>::iterator threads = activeThreads->begin();
422 list<ThreadID>::iterator end = activeThreads->end();
423
424 while (threads != end) {
425 ThreadID tid = *threads++;
426
427 changedROBNumEntries[tid] = false;
428
429 // Also check if any of the threads has a trap pending
430 if (commitStatus[tid] == TrapPending ||
431 commitStatus[tid] == FetchTrapPending) {
432 _nextStatus = Active;
433 }
434 }
435
436 if (_nextStatus == Inactive && _status == Active) {
437 DPRINTF(Activity, "Deactivating stage.\n");
438 cpu->deactivateStage(O3CPU::CommitIdx);
439 } else if (_nextStatus == Active && _status == Inactive) {
440 DPRINTF(Activity, "Activating stage.\n");
441 cpu->activateStage(O3CPU::CommitIdx);
442 }
443
444 _status = _nextStatus;
445}
446
447template <class Impl>
448void
449DefaultCommit<Impl>::setNextStatus()
450{
451 int squashes = 0;
452
453 list<ThreadID>::iterator threads = activeThreads->begin();
454 list<ThreadID>::iterator end = activeThreads->end();
455
456 while (threads != end) {
457 ThreadID tid = *threads++;
458
459 if (commitStatus[tid] == ROBSquashing) {
460 squashes++;
461 }
462 }
463
464 squashCounter = squashes;
465
466 // If commit is currently squashing, then it will have activity for the
467 // next cycle. Set its next status as active.
468 if (squashCounter) {
469 _nextStatus = Active;
470 }
471}
472
473template <class Impl>
474bool
475DefaultCommit<Impl>::changedROBEntries()
476{
477 list<ThreadID>::iterator threads = activeThreads->begin();
478 list<ThreadID>::iterator end = activeThreads->end();
479
480 while (threads != end) {
481 ThreadID tid = *threads++;
482
483 if (changedROBNumEntries[tid]) {
484 return true;
485 }
486 }
487
488 return false;
489}
490
491template <class Impl>
492size_t
493DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
494{
495 return rob->numFreeEntries(tid);
496}
497
498template <class Impl>
499void
500DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
501{
502 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
503
504 TrapEvent *trap = new TrapEvent(this, tid);
505
506 cpu->schedule(trap, curTick() + trapLatency);
507 trapInFlight[tid] = true;
508 thread[tid]->trapPending = true;
509}
510
511template <class Impl>
512void
513DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
514{
515 assert(!trapInFlight[tid]);
516 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
517
518 tcSquash[tid] = true;
519}
520
521template <class Impl>
522void
523DefaultCommit<Impl>::squashAll(ThreadID tid)
524{
525 // If we want to include the squashing instruction in the squash,
526 // then use one older sequence number.
527 // Hopefully this doesn't mess things up. Basically I want to squash
528 // all instructions of this thread.
529 InstSeqNum squashed_inst = rob->isEmpty() ?
530 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
531
532 // All younger instructions will be squashed. Set the sequence
533 // number as the youngest instruction in the ROB (0 in this case.
534 // Hopefully nothing breaks.)
535 youngestSeqNum[tid] = lastCommitedSeqNum[tid];
536
537 rob->squash(squashed_inst, tid);
538 changedROBNumEntries[tid] = true;
539
540 // Send back the sequence number of the squashed instruction.
541 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
542
543 // Send back the squash signal to tell stages that they should
544 // squash.
545 toIEW->commitInfo[tid].squash = true;
546
547 // Send back the rob squashing signal so other stages know that
548 // the ROB is in the process of squashing.
549 toIEW->commitInfo[tid].robSquashing = true;
550
551 toIEW->commitInfo[tid].mispredictInst = NULL;
552 toIEW->commitInfo[tid].squashInst = NULL;
553
554 toIEW->commitInfo[tid].pc = pc[tid];
555}
556
557template <class Impl>
558void
559DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
560{
561 squashAll(tid);
562
563 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
564
565 thread[tid]->trapPending = false;
566 thread[tid]->inSyscall = false;
567 trapInFlight[tid] = false;
568
569 trapSquash[tid] = false;
570
571 commitStatus[tid] = ROBSquashing;
572 cpu->activityThisCycle();
573}
574
575template <class Impl>
576void
577DefaultCommit<Impl>::squashFromTC(ThreadID tid)
578{
579 squashAll(tid);
580
581 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
582
583 thread[tid]->inSyscall = false;
584 assert(!thread[tid]->trapPending);
585
586 commitStatus[tid] = ROBSquashing;
587 cpu->activityThisCycle();
588
589 tcSquash[tid] = false;
590}
591
592template <class Impl>
593void
594DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst,
595 uint64_t squash_after_seq_num)
596{
597 youngestSeqNum[tid] = squash_after_seq_num;
598
599 rob->squash(squash_after_seq_num, tid);
600 changedROBNumEntries[tid] = true;
601
602 // Send back the sequence number of the squashed instruction.
603 toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num;
604
605 toIEW->commitInfo[tid].squashInst = head_inst;
606 // Send back the squash signal to tell stages that they should squash.
607 toIEW->commitInfo[tid].squash = true;
608
609 // Send back the rob squashing signal so other stages know that
610 // the ROB is in the process of squashing.
611 toIEW->commitInfo[tid].robSquashing = true;
612
613 toIEW->commitInfo[tid].mispredictInst = NULL;
614
615 toIEW->commitInfo[tid].pc = pc[tid];
616 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
617 tid, squash_after_seq_num);
618 commitStatus[tid] = ROBSquashing;
619}
620
621template <class Impl>
622void
623DefaultCommit<Impl>::tick()
624{
625 wroteToTimeBuffer = false;
626 _nextStatus = Inactive;
627
628 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
629 cpu->signalDrained();
630 drainPending = false;
631 return;
632 }
633
634 if (activeThreads->empty())
635 return;
636
637 list<ThreadID>::iterator threads = activeThreads->begin();
638 list<ThreadID>::iterator end = activeThreads->end();
639
640 // Check if any of the threads are done squashing. Change the
641 // status if they are done.
642 while (threads != end) {
643 ThreadID tid = *threads++;
644
645 // Clear the bit saying if the thread has committed stores
646 // this cycle.
647 committedStores[tid] = false;
648
649 if (commitStatus[tid] == ROBSquashing) {
650
651 if (rob->isDoneSquashing(tid)) {
652 commitStatus[tid] = Running;
653 } else {
654 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
655 " insts this cycle.\n", tid);
656 rob->doSquash(tid);
657 toIEW->commitInfo[tid].robSquashing = true;
658 wroteToTimeBuffer = true;
659 }
660 }
661 }
662
663 commit();
664
665 markCompletedInsts();
666
667 threads = activeThreads->begin();
668
669 while (threads != end) {
670 ThreadID tid = *threads++;
671
672 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
673 // The ROB has more instructions it can commit. Its next status
674 // will be active.
675 _nextStatus = Active;
676
677 DynInstPtr inst = rob->readHeadInst(tid);
678
679 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
680 " ROB and ready to commit\n",
681 tid, inst->seqNum, inst->pcState());
682
683 } else if (!rob->isEmpty(tid)) {
684 DynInstPtr inst = rob->readHeadInst(tid);
685
686 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
687 "%s is head of ROB and not ready\n",
688 tid, inst->seqNum, inst->pcState());
689 }
690
691 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
692 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
693 }
694
695
696 if (wroteToTimeBuffer) {
697 DPRINTF(Activity, "Activity This Cycle.\n");
698 cpu->activityThisCycle();
699 }
700
701 updateStatus();
702}
703
704#if FULL_SYSTEM
705template <class Impl>
706void
707DefaultCommit<Impl>::handleInterrupt()
708{
709 // Verify that we still have an interrupt to handle
710 if (!cpu->checkInterrupts(cpu->tcBase(0))) {
711 DPRINTF(Commit, "Pending interrupt is cleared by master before "
712 "it got handled. Restart fetching from the orig path.\n");
713 toIEW->commitInfo[0].clearInterrupt = true;
714 interrupt = NoFault;
715 return;
716 }
717
718 // Wait until all in flight instructions are finished before enterring
719 // the interrupt.
720 if (cpu->instList.empty()) {
721 // Squash or record that I need to squash this cycle if
722 // an interrupt needed to be handled.
723 DPRINTF(Commit, "Interrupt detected.\n");
724
725 // Clear the interrupt now that it's going to be handled
726 toIEW->commitInfo[0].clearInterrupt = true;
727
728 assert(!thread[0]->inSyscall);
729 thread[0]->inSyscall = true;
730
731 // CPU will handle interrupt.
732 cpu->processInterrupts(interrupt);
733
734 thread[0]->inSyscall = false;
735
736 commitStatus[0] = TrapPending;
737
738 // Generate trap squash event.
739 generateTrapEvent(0);
740
741 interrupt = NoFault;
742 } else {
743 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
744 }
745}
746
747template <class Impl>
748void
749DefaultCommit<Impl>::propagateInterrupt()
750{
751 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
752 tcSquash[0])
753 return;
754
755 // Process interrupts if interrupts are enabled, not in PAL
756 // mode, and no other traps or external squashes are currently
757 // pending.
758 // @todo: Allow other threads to handle interrupts.
759
760 // Get any interrupt that happened
761 interrupt = cpu->getInterrupts();
762
763 // Tell fetch that there is an interrupt pending. This
764 // will make fetch wait until it sees a non PAL-mode PC,
765 // at which point it stops fetching instructions.
766 if (interrupt != NoFault)
767 toIEW->commitInfo[0].interruptPending = true;
768}
769
770#endif // FULL_SYSTEM
771
772template <class Impl>
773void
774DefaultCommit<Impl>::commit()
775{
776
777#if FULL_SYSTEM
778 // Check for any interrupt that we've already squashed for and start processing it.
779 if (interrupt != NoFault)
780 handleInterrupt();
781
782 // Check if we have a interrupt and get read to handle it
783 if (cpu->checkInterrupts(cpu->tcBase(0)))
784 propagateInterrupt();
785#endif // FULL_SYSTEM
786
787 ////////////////////////////////////
788 // Check for any possible squashes, handle them first
789 ////////////////////////////////////
790 list<ThreadID>::iterator threads = activeThreads->begin();
791 list<ThreadID>::iterator end = activeThreads->end();
792
793 while (threads != end) {
794 ThreadID tid = *threads++;
795
796 // Not sure which one takes priority. I think if we have
797 // both, that's a bad sign.
798 if (trapSquash[tid] == true) {
799 assert(!tcSquash[tid]);
800 squashFromTrap(tid);
801 } else if (tcSquash[tid] == true) {
802 assert(commitStatus[tid] != TrapPending);
803 squashFromTC(tid);
804 }
805
806 // Squashed sequence number must be older than youngest valid
807 // instruction in the ROB. This prevents squashes from younger
808 // instructions overriding squashes from older instructions.
809 if (fromIEW->squash[tid] &&
810 commitStatus[tid] != TrapPending &&
811 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
812
813 if (fromIEW->mispredictInst[tid]) {
814 DPRINTF(Commit,
815 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
816 tid,
817 fromIEW->mispredictInst[tid]->instAddr(),
818 fromIEW->squashedSeqNum[tid]);
819 } else {
820 DPRINTF(Commit,
821 "[tid:%i]: Squashing due to order violation [sn:%i]\n",
822 tid, fromIEW->squashedSeqNum[tid]);
823 }
824
825 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
826 tid,
827 fromIEW->pc[tid].nextInstAddr());
828
829 commitStatus[tid] = ROBSquashing;
830
831 // If we want to include the squashing instruction in the squash,
832 // then use one older sequence number.
833 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
834
835 if (fromIEW->includeSquashInst[tid] == true) {
836 squashed_inst--;
837 }
838
839 // All younger instructions will be squashed. Set the sequence
840 // number as the youngest instruction in the ROB.
841 youngestSeqNum[tid] = squashed_inst;
842
843 rob->squash(squashed_inst, tid);
844 changedROBNumEntries[tid] = true;
845
846 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
847
848 toIEW->commitInfo[tid].squash = true;
849
850 // Send back the rob squashing signal so other stages know that
851 // the ROB is in the process of squashing.
852 toIEW->commitInfo[tid].robSquashing = true;
853
854 toIEW->commitInfo[tid].mispredictInst =
855 fromIEW->mispredictInst[tid];
856 toIEW->commitInfo[tid].branchTaken =
857 fromIEW->branchTaken[tid];
858 toIEW->commitInfo[tid].squashInst = NULL;
859
860 toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
861
862 if (toIEW->commitInfo[tid].mispredictInst) {
863 ++branchMispredicts;
864 }
865 }
866
867 }
868
869 setNextStatus();
870
871 if (squashCounter != numThreads) {
872 // If we're not currently squashing, then get instructions.
873 getInsts();
874
875 // Try to commit any instructions.
876 commitInsts();
877 }
878
879 //Check for any activity
880 threads = activeThreads->begin();
881
882 while (threads != end) {
883 ThreadID tid = *threads++;
884
885 if (changedROBNumEntries[tid]) {
886 toIEW->commitInfo[tid].usedROB = true;
887 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
888
889 wroteToTimeBuffer = true;
890 changedROBNumEntries[tid] = false;
891 if (rob->isEmpty(tid))
892 checkEmptyROB[tid] = true;
893 }
894
895 // ROB is only considered "empty" for previous stages if: a)
896 // ROB is empty, b) there are no outstanding stores, c) IEW
897 // stage has received any information regarding stores that
898 // committed.
899 // c) is checked by making sure to not consider the ROB empty
900 // on the same cycle as when stores have been committed.
901 // @todo: Make this handle multi-cycle communication between
902 // commit and IEW.
903 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
904 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
905 checkEmptyROB[tid] = false;
906 toIEW->commitInfo[tid].usedROB = true;
907 toIEW->commitInfo[tid].emptyROB = true;
908 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
909 wroteToTimeBuffer = true;
910 }
911
912 }
913}
914
915template <class Impl>
916void
917DefaultCommit<Impl>::commitInsts()
918{
919 ////////////////////////////////////
920 // Handle commit
921 // Note that commit will be handled prior to putting new
922 // instructions in the ROB so that the ROB only tries to commit
923 // instructions it has in this current cycle, and not instructions
924 // it is writing in during this cycle. Can't commit and squash
925 // things at the same time...
926 ////////////////////////////////////
927
928 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
929
930 unsigned num_committed = 0;
931
932 DynInstPtr head_inst;
933
934 // Commit as many instructions as possible until the commit bandwidth
935 // limit is reached, or it becomes impossible to commit any more.
936 while (num_committed < commitWidth) {
937 int commit_thread = getCommittingThread();
938
939 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
940 break;
941
942 head_inst = rob->readHeadInst(commit_thread);
943
944 ThreadID tid = head_inst->threadNumber;
945
946 assert(tid == commit_thread);
947
948 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
949 head_inst->seqNum, tid);
950
951 // If the head instruction is squashed, it is ready to retire
952 // (be removed from the ROB) at any time.
953 if (head_inst->isSquashed()) {
954
955 DPRINTF(Commit, "Retiring squashed instruction from "
956 "ROB.\n");
957
958 rob->retireHead(commit_thread);
959
960 ++commitSquashedInsts;
961
962 // Record that the number of ROB entries has changed.
963 changedROBNumEntries[tid] = true;
964 } else {
965 pc[tid] = head_inst->pcState();
966
967 // Increment the total number of non-speculative instructions
968 // executed.
969 // Hack for now: it really shouldn't happen until after the
970 // commit is deemed to be successful, but this count is needed
971 // for syscalls.
972 thread[tid]->funcExeInst++;
973
974 // Try to commit the head instruction.
975 bool commit_success = commitHead(head_inst, num_committed);
976
977 if (commit_success) {
978 ++num_committed;
979
980 changedROBNumEntries[tid] = true;
981
982 // Set the doneSeqNum to the youngest committed instruction.
983 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
984
985 ++commitCommittedInsts;
986
987 // To match the old model, don't count nops and instruction
988 // prefetches towards the total commit count.
989 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
990 cpu->instDone(tid);
991 }
992
993 // Updates misc. registers.
994 head_inst->updateMiscRegs();
995
996 TheISA::advancePC(pc[tid], head_inst->staticInst);
997
998 // Keep track of the last sequence number commited
999 lastCommitedSeqNum[tid] = head_inst->seqNum;
1000
1001 // If this is an instruction that doesn't play nicely with
1002 // others squash everything and restart fetch
1003 if (head_inst->isSquashAfter())
1004 squashAfter(tid, head_inst, head_inst->seqNum);
1005
1006 int count = 0;
1007 Addr oldpc;
1008 // Debug statement. Checks to make sure we're not
1009 // currently updating state while handling PC events.
1010 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
1011 do {
1012 oldpc = pc[tid].instAddr();
1013 cpu->system->pcEventQueue.service(thread[tid]->getTC());
1014 count++;
1015 } while (oldpc != pc[tid].instAddr());
1016 if (count > 1) {
1017 DPRINTF(Commit,
1018 "PC skip function event, stopping commit\n");
1019 break;
1020 }
1021 } else {
1022 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1023 "[tid:%i] [sn:%i].\n",
1024 head_inst->pcState(), tid ,head_inst->seqNum);
1025 break;
1026 }
1027 }
1028 }
1029
1030 DPRINTF(CommitRate, "%i\n", num_committed);
1031 numCommittedDist.sample(num_committed);
1032
1033 if (num_committed == commitWidth) {
1034 commitEligibleSamples++;
1035 }
1036}
1037
1038template <class Impl>
1039bool
1040DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1041{
1042 assert(head_inst);
1043
1044 ThreadID tid = head_inst->threadNumber;
1045
1046 // If the instruction is not executed yet, then it will need extra
1047 // handling. Signal backwards that it should be executed.
1048 if (!head_inst->isExecuted()) {
1049 // Keep this number correct. We have not yet actually executed
1050 // and committed this instruction.
1051 thread[tid]->funcExeInst--;
1052
1053 if (head_inst->isNonSpeculative() ||
1054 head_inst->isStoreConditional() ||
1055 head_inst->isMemBarrier() ||
1056 head_inst->isWriteBarrier()) {
1057
1058 DPRINTF(Commit, "Encountered a barrier or non-speculative "
1059 "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1060 head_inst->seqNum, head_inst->pcState());
1061
1062 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1063 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1064 return false;
1065 }
1066
1067 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1068
1069 // Change the instruction so it won't try to commit again until
1070 // it is executed.
1071 head_inst->clearCanCommit();
1072
1073 ++commitNonSpecStalls;
1074
1075 return false;
1076 } else if (head_inst->isLoad()) {
1077 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1078 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1079 return false;
1080 }
1081
1082 assert(head_inst->uncacheable());
1083 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
1084 head_inst->seqNum, head_inst->pcState());
1085
1086 // Send back the non-speculative instruction's sequence
1087 // number. Tell the lsq to re-execute the load.
1088 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1089 toIEW->commitInfo[tid].uncached = true;
1090 toIEW->commitInfo[tid].uncachedLoad = head_inst;
1091
1092 head_inst->clearCanCommit();
1093
1094 return false;
1095 } else {
1096 panic("Trying to commit un-executed instruction "
1097 "of unknown type!\n");
1098 }
1099 }
1100
1101 if (head_inst->isThreadSync()) {
1102 // Not handled for now.
1103 panic("Thread sync instructions are not handled yet.\n");
1104 }
1105
1106 // Check if the instruction caused a fault. If so, trap.
1107 Fault inst_fault = head_inst->getFault();
1108
1109 // Stores mark themselves as completed.
1110 if (!head_inst->isStore() && inst_fault == NoFault) {
1111 head_inst->setCompleted();
1112 }
1113
1114#if USE_CHECKER
1115 // Use checker prior to updating anything due to traps or PC
1116 // based events.
1117 if (cpu->checker) {
1118 cpu->checker->verify(head_inst);
1119 }
1120#endif
1121
1122 if (inst_fault != NoFault) {
1123 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1124 head_inst->seqNum, head_inst->pcState());
1125
1126 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1127 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1128 return false;
1129 }
1130
1131 head_inst->setCompleted();
1132
1133#if USE_CHECKER
1134 if (cpu->checker && head_inst->isStore()) {
1135 cpu->checker->verify(head_inst);
1136 }
1137#endif
1138
1139 assert(!thread[tid]->inSyscall);
1140
1141 // Mark that we're in state update mode so that the trap's
1142 // execution doesn't generate extra squashes.
1143 thread[tid]->inSyscall = true;
1144
1145 // Execute the trap. Although it's slightly unrealistic in
1146 // terms of timing (as it doesn't wait for the full timing of
1147 // the trap event to complete before updating state), it's
1148 // needed to update the state as soon as possible. This
1149 // prevents external agents from changing any specific state
1150 // that the trap need.
1151 cpu->trap(inst_fault, tid, head_inst->staticInst);
1152
1153 // Exit state update mode to avoid accidental updating.
1154 thread[tid]->inSyscall = false;
1155
1156 commitStatus[tid] = TrapPending;
1157
1158 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1159 head_inst->seqNum);
1160 if (head_inst->traceData) {
1161 if (DTRACE(ExecFaulting)) {
1162 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1163 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1164 head_inst->traceData->dump();
1165 }
1166 delete head_inst->traceData;
1167 head_inst->traceData = NULL;
1168 }
1169
1170 // Generate trap squash event.
1171 generateTrapEvent(tid);
1172 return false;
1173 }
1174
1175 updateComInstStats(head_inst);
1176
1177#if FULL_SYSTEM
1178 if (thread[tid]->profile) {
1179 thread[tid]->profilePC = head_inst->instAddr();
1180 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1181 head_inst->staticInst);
1182
1183 if (node)
1184 thread[tid]->profileNode = node;
1185 }
1186 if (CPA::available()) {
1187 if (head_inst->isControl()) {
1188 ThreadContext *tc = thread[tid]->getTC();
1189 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1190 }
1191 }
1192#endif
1193 DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
1194 head_inst->seqNum, head_inst->pcState());
1195 if (head_inst->traceData) {
1196 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1197 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1198 head_inst->traceData->dump();
1199 delete head_inst->traceData;
1200 head_inst->traceData = NULL;
1201 }
1202
1203 // Update the commit rename map
1204 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1205 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1206 head_inst->renamedDestRegIdx(i));
1207 }
1208
1209 // Finally clear the head ROB entry.
1210 rob->retireHead(tid);
1211
1212#if TRACING_ON
1213 // Print info needed by the pipeline activity viewer.
1214 DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
1215 head_inst->fetchTick,
1216 head_inst->instAddr(),
1217 head_inst->microPC(),
1218 head_inst->seqNum,
1219 head_inst->staticInst->disassemble(head_inst->instAddr()));
1220 DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", head_inst->decodeTick);
1221 DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", head_inst->renameTick);
1222 DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", head_inst->dispatchTick);
1223 DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", head_inst->issueTick);
1224 DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", head_inst->completeTick);
1225 DPRINTFR(O3PipeView, "O3PipeView:retire:%llu\n", curTick());
1226#endif
1227
1228 // If this was a store, record it for this cycle.
1229 if (head_inst->isStore())
1230 committedStores[tid] = true;
1231
1232 // Return true to indicate that we have committed an instruction.
1233 return true;
1234}
1235
1236template <class Impl>
1237void
1238DefaultCommit<Impl>::getInsts()
1239{
1240 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1241
1242 // Read any renamed instructions and place them into the ROB.
1243 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1244
1245 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1246 DynInstPtr inst;
1247
1248 inst = fromRename->insts[inst_num];
1249 ThreadID tid = inst->threadNumber;
1250
1251 if (!inst->isSquashed() &&
1252 commitStatus[tid] != ROBSquashing &&
1253 commitStatus[tid] != TrapPending) {
1254 changedROBNumEntries[tid] = true;
1255
1256 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1257 inst->pcState(), inst->seqNum, tid);
1258
1259 rob->insertInst(inst);
1260
1261 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1262
1263 youngestSeqNum[tid] = inst->seqNum;
1264 } else {
1265 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1266 "squashed, skipping.\n",
1267 inst->pcState(), inst->seqNum, tid);
1268 }
1269 }
1270}
1271
1272template <class Impl>
1273void
1274DefaultCommit<Impl>::skidInsert()
1275{
1276 DPRINTF(Commit, "Attempting to any instructions from rename into "
1277 "skidBuffer.\n");
1278
1279 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1280 DynInstPtr inst = fromRename->insts[inst_num];
1281
1282 if (!inst->isSquashed()) {
1283 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1284 "skidBuffer.\n", inst->pcState(), inst->seqNum,
1285 inst->threadNumber);
1286 skidBuffer.push(inst);
1287 } else {
1288 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1289 "squashed, skipping.\n",
1290 inst->pcState(), inst->seqNum, inst->threadNumber);
1291 }
1292 }
1293}
1294
1295template <class Impl>
1296void
1297DefaultCommit<Impl>::markCompletedInsts()
1298{
1299 // Grab completed insts out of the IEW instruction queue, and mark
1300 // instructions completed within the ROB.
1301 for (int inst_num = 0;
1302 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1303 ++inst_num)
1304 {
1305 if (!fromIEW->insts[inst_num]->isSquashed()) {
1306 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1307 "within ROB.\n",
1308 fromIEW->insts[inst_num]->threadNumber,
1309 fromIEW->insts[inst_num]->pcState(),
1310 fromIEW->insts[inst_num]->seqNum);
1311
1312 // Mark the instruction as ready to commit.
1313 fromIEW->insts[inst_num]->setCanCommit();
1314 }
1315 }
1316}
1317
1318template <class Impl>
1319bool
1320DefaultCommit<Impl>::robDoneSquashing()
1321{
1322 list<ThreadID>::iterator threads = activeThreads->begin();
1323 list<ThreadID>::iterator end = activeThreads->end();
1324
1325 while (threads != end) {
1326 ThreadID tid = *threads++;
1327
1328 if (!rob->isDoneSquashing(tid))
1329 return false;
1330 }
1331
1332 return true;
1333}
1334
1335template <class Impl>
1336void
1337DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1338{
1339 ThreadID tid = inst->threadNumber;
1340
1341 //
1342 // Pick off the software prefetches
1343 //
1344#ifdef TARGET_ALPHA
1345 if (inst->isDataPrefetch()) {
1346 statComSwp[tid]++;
1347 } else {
1348 statComInst[tid]++;
1349 }
1350#else
1351 statComInst[tid]++;
1352#endif
1353
1354 //
1355 // Control Instructions
1356 //
1357 if (inst->isControl())
1358 statComBranches[tid]++;
1359
1360 //
1361 // Memory references
1362 //
1363 if (inst->isMemRef()) {
1364 statComRefs[tid]++;
1365
1366 if (inst->isLoad()) {
1367 statComLoads[tid]++;
1368 }
1369 }
1370
1371 if (inst->isMemBarrier()) {
1372 statComMembars[tid]++;
1373 }
1374
1375 // Integer Instruction
1376 if (inst->isInteger())
1377 statComInteger[tid]++;
1378
1379 // Floating Point Instruction
1380 if (inst->isFloating())
1381 statComFloating[tid]++;
1382
1383 // Function Calls
1384 if (inst->isCall())
1385 statComFunctionCalls[tid]++;
1386
1387}
1388
1389////////////////////////////////////////
1390// //
1391// SMT COMMIT POLICY MAINTAINED HERE //
1392// //
1393////////////////////////////////////////
1394template <class Impl>
1395ThreadID
1396DefaultCommit<Impl>::getCommittingThread()
1397{
1398 if (numThreads > 1) {
1399 switch (commitPolicy) {
1400
1401 case Aggressive:
1402 //If Policy is Aggressive, commit will call
1403 //this function multiple times per
1404 //cycle
1405 return oldestReady();
1406
1407 case RoundRobin:
1408 return roundRobin();
1409
1410 case OldestReady:
1411 return oldestReady();
1412
1413 default:
1414 return InvalidThreadID;
1415 }
1416 } else {
1417 assert(!activeThreads->empty());
1418 ThreadID tid = activeThreads->front();
1419
1420 if (commitStatus[tid] == Running ||
1421 commitStatus[tid] == Idle ||
1422 commitStatus[tid] == FetchTrapPending) {
1423 return tid;
1424 } else {
1425 return InvalidThreadID;
1426 }
1427 }
1428}
1429
1430template<class Impl>
1431ThreadID
1432DefaultCommit<Impl>::roundRobin()
1433{
1434 list<ThreadID>::iterator pri_iter = priority_list.begin();
1435 list<ThreadID>::iterator end = priority_list.end();
1436
1437 while (pri_iter != end) {
1438 ThreadID tid = *pri_iter;
1439
1440 if (commitStatus[tid] == Running ||
1441 commitStatus[tid] == Idle ||
1442 commitStatus[tid] == FetchTrapPending) {
1443
1444 if (rob->isHeadReady(tid)) {
1445 priority_list.erase(pri_iter);
1446 priority_list.push_back(tid);
1447
1448 return tid;
1449 }
1450 }
1451
1452 pri_iter++;
1453 }
1454
1455 return InvalidThreadID;
1456}
1457
1458template<class Impl>
1459ThreadID
1460DefaultCommit<Impl>::oldestReady()
1461{
1462 unsigned oldest = 0;
1463 bool first = true;
1464
1465 list<ThreadID>::iterator threads = activeThreads->begin();
1466 list<ThreadID>::iterator end = activeThreads->end();
1467
1468 while (threads != end) {
1469 ThreadID tid = *threads++;
1470
1471 if (!rob->isEmpty(tid) &&
1472 (commitStatus[tid] == Running ||
1473 commitStatus[tid] == Idle ||
1474 commitStatus[tid] == FetchTrapPending)) {
1475
1476 if (rob->isHeadReady(tid)) {
1477
1478 DynInstPtr head_inst = rob->readHeadInst(tid);
1479
1480 if (first) {
1481 oldest = tid;
1482 first = false;
1483 } else if (head_inst->seqNum < oldest) {
1484 oldest = tid;
1485 }
1486 }
1487 }
1488 }
1489
1490 if (!first) {
1491 return oldest;
1492 } else {
1493 return InvalidThreadID;
1494 }
1495}
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#include <algorithm>
45#include <string>
46
47#include "arch/utility.hh"
48#include "base/loader/symtab.hh"
49#include "base/cp_annotate.hh"
50#include "config/full_system.hh"
51#include "config/the_isa.hh"
52#include "config/use_checker.hh"
53#include "cpu/o3/commit.hh"
54#include "cpu/o3/thread_state.hh"
55#include "cpu/exetrace.hh"
56#include "cpu/timebuf.hh"
57#include "debug/Activity.hh"
58#include "debug/Commit.hh"
59#include "debug/CommitRate.hh"
60#include "debug/ExecFaulting.hh"
61#include "debug/O3PipeView.hh"
62#include "params/DerivO3CPU.hh"
63#include "sim/faults.hh"
64
65#if USE_CHECKER
66#include "cpu/checker/cpu.hh"
67#endif
68
69using namespace std;
70
71template <class Impl>
72DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
73 ThreadID _tid)
74 : Event(CPU_Tick_Pri), commit(_commit), tid(_tid)
75{
76 this->setFlags(AutoDelete);
77}
78
79template <class Impl>
80void
81DefaultCommit<Impl>::TrapEvent::process()
82{
83 // This will get reset by commit if it was switched out at the
84 // time of this event processing.
85 commit->trapSquash[tid] = true;
86}
87
88template <class Impl>
89const char *
90DefaultCommit<Impl>::TrapEvent::description() const
91{
92 return "Trap";
93}
94
95template <class Impl>
96DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
97 : cpu(_cpu),
98 squashCounter(0),
99 iewToCommitDelay(params->iewToCommitDelay),
100 commitToIEWDelay(params->commitToIEWDelay),
101 renameToROBDelay(params->renameToROBDelay),
102 fetchToCommitDelay(params->commitToFetchDelay),
103 renameWidth(params->renameWidth),
104 commitWidth(params->commitWidth),
105 numThreads(params->numThreads),
106 drainPending(false),
107 switchedOut(false),
108 trapLatency(params->trapLatency)
109{
110 _status = Active;
111 _nextStatus = Inactive;
112 std::string policy = params->smtCommitPolicy;
113
114 //Convert string to lowercase
115 std::transform(policy.begin(), policy.end(), policy.begin(),
116 (int(*)(int)) tolower);
117
118 //Assign commit policy
119 if (policy == "aggressive"){
120 commitPolicy = Aggressive;
121
122 DPRINTF(Commit,"Commit Policy set to Aggressive.\n");
123 } else if (policy == "roundrobin"){
124 commitPolicy = RoundRobin;
125
126 //Set-Up Priority List
127 for (ThreadID tid = 0; tid < numThreads; tid++) {
128 priority_list.push_back(tid);
129 }
130
131 DPRINTF(Commit,"Commit Policy set to Round Robin.\n");
132 } else if (policy == "oldestready"){
133 commitPolicy = OldestReady;
134
135 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
136 } else {
137 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
138 "RoundRobin,OldestReady}");
139 }
140
141 for (ThreadID tid = 0; tid < numThreads; tid++) {
142 commitStatus[tid] = Idle;
143 changedROBNumEntries[tid] = false;
144 checkEmptyROB[tid] = false;
145 trapInFlight[tid] = false;
146 committedStores[tid] = false;
147 trapSquash[tid] = false;
148 tcSquash[tid] = false;
149 pc[tid].set(0);
150 lastCommitedSeqNum[tid] = 0;
151 }
152#if FULL_SYSTEM
153 interrupt = NoFault;
154#endif
155}
156
157template <class Impl>
158std::string
159DefaultCommit<Impl>::name() const
160{
161 return cpu->name() + ".commit";
162}
163
164template <class Impl>
165void
166DefaultCommit<Impl>::regStats()
167{
168 using namespace Stats;
169 commitCommittedInsts
170 .name(name() + ".commitCommittedInsts")
171 .desc("The number of committed instructions")
172 .prereq(commitCommittedInsts);
173 commitSquashedInsts
174 .name(name() + ".commitSquashedInsts")
175 .desc("The number of squashed insts skipped by commit")
176 .prereq(commitSquashedInsts);
177 commitSquashEvents
178 .name(name() + ".commitSquashEvents")
179 .desc("The number of times commit is told to squash")
180 .prereq(commitSquashEvents);
181 commitNonSpecStalls
182 .name(name() + ".commitNonSpecStalls")
183 .desc("The number of times commit has been forced to stall to "
184 "communicate backwards")
185 .prereq(commitNonSpecStalls);
186 branchMispredicts
187 .name(name() + ".branchMispredicts")
188 .desc("The number of times a branch was mispredicted")
189 .prereq(branchMispredicts);
190 numCommittedDist
191 .init(0,commitWidth,1)
192 .name(name() + ".committed_per_cycle")
193 .desc("Number of insts commited each cycle")
194 .flags(Stats::pdf)
195 ;
196
197 statComInst
198 .init(cpu->numThreads)
199 .name(name() + ".count")
200 .desc("Number of instructions committed")
201 .flags(total)
202 ;
203
204 statComSwp
205 .init(cpu->numThreads)
206 .name(name() + ".swp_count")
207 .desc("Number of s/w prefetches committed")
208 .flags(total)
209 ;
210
211 statComRefs
212 .init(cpu->numThreads)
213 .name(name() + ".refs")
214 .desc("Number of memory references committed")
215 .flags(total)
216 ;
217
218 statComLoads
219 .init(cpu->numThreads)
220 .name(name() + ".loads")
221 .desc("Number of loads committed")
222 .flags(total)
223 ;
224
225 statComMembars
226 .init(cpu->numThreads)
227 .name(name() + ".membars")
228 .desc("Number of memory barriers committed")
229 .flags(total)
230 ;
231
232 statComBranches
233 .init(cpu->numThreads)
234 .name(name() + ".branches")
235 .desc("Number of branches committed")
236 .flags(total)
237 ;
238
239 statComFloating
240 .init(cpu->numThreads)
241 .name(name() + ".fp_insts")
242 .desc("Number of committed floating point instructions.")
243 .flags(total)
244 ;
245
246 statComInteger
247 .init(cpu->numThreads)
248 .name(name()+".int_insts")
249 .desc("Number of committed integer instructions.")
250 .flags(total)
251 ;
252
253 statComFunctionCalls
254 .init(cpu->numThreads)
255 .name(name()+".function_calls")
256 .desc("Number of function calls committed.")
257 .flags(total)
258 ;
259
260 commitEligible
261 .init(cpu->numThreads)
262 .name(name() + ".bw_limited")
263 .desc("number of insts not committed due to BW limits")
264 .flags(total)
265 ;
266
267 commitEligibleSamples
268 .name(name() + ".bw_lim_events")
269 .desc("number cycles where commit BW limit reached")
270 ;
271}
272
273template <class Impl>
274void
275DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
276{
277 thread = threads;
278}
279
280template <class Impl>
281void
282DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
283{
284 timeBuffer = tb_ptr;
285
286 // Setup wire to send information back to IEW.
287 toIEW = timeBuffer->getWire(0);
288
289 // Setup wire to read data from IEW (for the ROB).
290 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
291}
292
293template <class Impl>
294void
295DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
296{
297 fetchQueue = fq_ptr;
298
299 // Setup wire to get instructions from rename (for the ROB).
300 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
301}
302
303template <class Impl>
304void
305DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
306{
307 renameQueue = rq_ptr;
308
309 // Setup wire to get instructions from rename (for the ROB).
310 fromRename = renameQueue->getWire(-renameToROBDelay);
311}
312
313template <class Impl>
314void
315DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
316{
317 iewQueue = iq_ptr;
318
319 // Setup wire to get instructions from IEW.
320 fromIEW = iewQueue->getWire(-iewToCommitDelay);
321}
322
323template <class Impl>
324void
325DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
326{
327 iewStage = iew_stage;
328}
329
330template<class Impl>
331void
332DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
333{
334 activeThreads = at_ptr;
335}
336
337template <class Impl>
338void
339DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
340{
341 for (ThreadID tid = 0; tid < numThreads; tid++)
342 renameMap[tid] = &rm_ptr[tid];
343}
344
345template <class Impl>
346void
347DefaultCommit<Impl>::setROB(ROB *rob_ptr)
348{
349 rob = rob_ptr;
350}
351
352template <class Impl>
353void
354DefaultCommit<Impl>::initStage()
355{
356 rob->setActiveThreads(activeThreads);
357 rob->resetEntries();
358
359 // Broadcast the number of free entries.
360 for (ThreadID tid = 0; tid < numThreads; tid++) {
361 toIEW->commitInfo[tid].usedROB = true;
362 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
363 toIEW->commitInfo[tid].emptyROB = true;
364 }
365
366 // Commit must broadcast the number of free entries it has at the
367 // start of the simulation, so it starts as active.
368 cpu->activateStage(O3CPU::CommitIdx);
369
370 cpu->activityThisCycle();
371 trapLatency = cpu->ticks(trapLatency);
372}
373
374template <class Impl>
375bool
376DefaultCommit<Impl>::drain()
377{
378 drainPending = true;
379
380 return false;
381}
382
383template <class Impl>
384void
385DefaultCommit<Impl>::switchOut()
386{
387 switchedOut = true;
388 drainPending = false;
389 rob->switchOut();
390}
391
392template <class Impl>
393void
394DefaultCommit<Impl>::resume()
395{
396 drainPending = false;
397}
398
399template <class Impl>
400void
401DefaultCommit<Impl>::takeOverFrom()
402{
403 switchedOut = false;
404 _status = Active;
405 _nextStatus = Inactive;
406 for (ThreadID tid = 0; tid < numThreads; tid++) {
407 commitStatus[tid] = Idle;
408 changedROBNumEntries[tid] = false;
409 trapSquash[tid] = false;
410 tcSquash[tid] = false;
411 }
412 squashCounter = 0;
413 rob->takeOverFrom();
414}
415
416template <class Impl>
417void
418DefaultCommit<Impl>::updateStatus()
419{
420 // reset ROB changed variable
421 list<ThreadID>::iterator threads = activeThreads->begin();
422 list<ThreadID>::iterator end = activeThreads->end();
423
424 while (threads != end) {
425 ThreadID tid = *threads++;
426
427 changedROBNumEntries[tid] = false;
428
429 // Also check if any of the threads has a trap pending
430 if (commitStatus[tid] == TrapPending ||
431 commitStatus[tid] == FetchTrapPending) {
432 _nextStatus = Active;
433 }
434 }
435
436 if (_nextStatus == Inactive && _status == Active) {
437 DPRINTF(Activity, "Deactivating stage.\n");
438 cpu->deactivateStage(O3CPU::CommitIdx);
439 } else if (_nextStatus == Active && _status == Inactive) {
440 DPRINTF(Activity, "Activating stage.\n");
441 cpu->activateStage(O3CPU::CommitIdx);
442 }
443
444 _status = _nextStatus;
445}
446
447template <class Impl>
448void
449DefaultCommit<Impl>::setNextStatus()
450{
451 int squashes = 0;
452
453 list<ThreadID>::iterator threads = activeThreads->begin();
454 list<ThreadID>::iterator end = activeThreads->end();
455
456 while (threads != end) {
457 ThreadID tid = *threads++;
458
459 if (commitStatus[tid] == ROBSquashing) {
460 squashes++;
461 }
462 }
463
464 squashCounter = squashes;
465
466 // If commit is currently squashing, then it will have activity for the
467 // next cycle. Set its next status as active.
468 if (squashCounter) {
469 _nextStatus = Active;
470 }
471}
472
473template <class Impl>
474bool
475DefaultCommit<Impl>::changedROBEntries()
476{
477 list<ThreadID>::iterator threads = activeThreads->begin();
478 list<ThreadID>::iterator end = activeThreads->end();
479
480 while (threads != end) {
481 ThreadID tid = *threads++;
482
483 if (changedROBNumEntries[tid]) {
484 return true;
485 }
486 }
487
488 return false;
489}
490
491template <class Impl>
492size_t
493DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
494{
495 return rob->numFreeEntries(tid);
496}
497
498template <class Impl>
499void
500DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
501{
502 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
503
504 TrapEvent *trap = new TrapEvent(this, tid);
505
506 cpu->schedule(trap, curTick() + trapLatency);
507 trapInFlight[tid] = true;
508 thread[tid]->trapPending = true;
509}
510
511template <class Impl>
512void
513DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
514{
515 assert(!trapInFlight[tid]);
516 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
517
518 tcSquash[tid] = true;
519}
520
521template <class Impl>
522void
523DefaultCommit<Impl>::squashAll(ThreadID tid)
524{
525 // If we want to include the squashing instruction in the squash,
526 // then use one older sequence number.
527 // Hopefully this doesn't mess things up. Basically I want to squash
528 // all instructions of this thread.
529 InstSeqNum squashed_inst = rob->isEmpty() ?
530 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
531
532 // All younger instructions will be squashed. Set the sequence
533 // number as the youngest instruction in the ROB (0 in this case.
534 // Hopefully nothing breaks.)
535 youngestSeqNum[tid] = lastCommitedSeqNum[tid];
536
537 rob->squash(squashed_inst, tid);
538 changedROBNumEntries[tid] = true;
539
540 // Send back the sequence number of the squashed instruction.
541 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
542
543 // Send back the squash signal to tell stages that they should
544 // squash.
545 toIEW->commitInfo[tid].squash = true;
546
547 // Send back the rob squashing signal so other stages know that
548 // the ROB is in the process of squashing.
549 toIEW->commitInfo[tid].robSquashing = true;
550
551 toIEW->commitInfo[tid].mispredictInst = NULL;
552 toIEW->commitInfo[tid].squashInst = NULL;
553
554 toIEW->commitInfo[tid].pc = pc[tid];
555}
556
557template <class Impl>
558void
559DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
560{
561 squashAll(tid);
562
563 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
564
565 thread[tid]->trapPending = false;
566 thread[tid]->inSyscall = false;
567 trapInFlight[tid] = false;
568
569 trapSquash[tid] = false;
570
571 commitStatus[tid] = ROBSquashing;
572 cpu->activityThisCycle();
573}
574
575template <class Impl>
576void
577DefaultCommit<Impl>::squashFromTC(ThreadID tid)
578{
579 squashAll(tid);
580
581 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
582
583 thread[tid]->inSyscall = false;
584 assert(!thread[tid]->trapPending);
585
586 commitStatus[tid] = ROBSquashing;
587 cpu->activityThisCycle();
588
589 tcSquash[tid] = false;
590}
591
592template <class Impl>
593void
594DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst,
595 uint64_t squash_after_seq_num)
596{
597 youngestSeqNum[tid] = squash_after_seq_num;
598
599 rob->squash(squash_after_seq_num, tid);
600 changedROBNumEntries[tid] = true;
601
602 // Send back the sequence number of the squashed instruction.
603 toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num;
604
605 toIEW->commitInfo[tid].squashInst = head_inst;
606 // Send back the squash signal to tell stages that they should squash.
607 toIEW->commitInfo[tid].squash = true;
608
609 // Send back the rob squashing signal so other stages know that
610 // the ROB is in the process of squashing.
611 toIEW->commitInfo[tid].robSquashing = true;
612
613 toIEW->commitInfo[tid].mispredictInst = NULL;
614
615 toIEW->commitInfo[tid].pc = pc[tid];
616 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
617 tid, squash_after_seq_num);
618 commitStatus[tid] = ROBSquashing;
619}
620
621template <class Impl>
622void
623DefaultCommit<Impl>::tick()
624{
625 wroteToTimeBuffer = false;
626 _nextStatus = Inactive;
627
628 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
629 cpu->signalDrained();
630 drainPending = false;
631 return;
632 }
633
634 if (activeThreads->empty())
635 return;
636
637 list<ThreadID>::iterator threads = activeThreads->begin();
638 list<ThreadID>::iterator end = activeThreads->end();
639
640 // Check if any of the threads are done squashing. Change the
641 // status if they are done.
642 while (threads != end) {
643 ThreadID tid = *threads++;
644
645 // Clear the bit saying if the thread has committed stores
646 // this cycle.
647 committedStores[tid] = false;
648
649 if (commitStatus[tid] == ROBSquashing) {
650
651 if (rob->isDoneSquashing(tid)) {
652 commitStatus[tid] = Running;
653 } else {
654 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
655 " insts this cycle.\n", tid);
656 rob->doSquash(tid);
657 toIEW->commitInfo[tid].robSquashing = true;
658 wroteToTimeBuffer = true;
659 }
660 }
661 }
662
663 commit();
664
665 markCompletedInsts();
666
667 threads = activeThreads->begin();
668
669 while (threads != end) {
670 ThreadID tid = *threads++;
671
672 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
673 // The ROB has more instructions it can commit. Its next status
674 // will be active.
675 _nextStatus = Active;
676
677 DynInstPtr inst = rob->readHeadInst(tid);
678
679 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
680 " ROB and ready to commit\n",
681 tid, inst->seqNum, inst->pcState());
682
683 } else if (!rob->isEmpty(tid)) {
684 DynInstPtr inst = rob->readHeadInst(tid);
685
686 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
687 "%s is head of ROB and not ready\n",
688 tid, inst->seqNum, inst->pcState());
689 }
690
691 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
692 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
693 }
694
695
696 if (wroteToTimeBuffer) {
697 DPRINTF(Activity, "Activity This Cycle.\n");
698 cpu->activityThisCycle();
699 }
700
701 updateStatus();
702}
703
704#if FULL_SYSTEM
705template <class Impl>
706void
707DefaultCommit<Impl>::handleInterrupt()
708{
709 // Verify that we still have an interrupt to handle
710 if (!cpu->checkInterrupts(cpu->tcBase(0))) {
711 DPRINTF(Commit, "Pending interrupt is cleared by master before "
712 "it got handled. Restart fetching from the orig path.\n");
713 toIEW->commitInfo[0].clearInterrupt = true;
714 interrupt = NoFault;
715 return;
716 }
717
718 // Wait until all in flight instructions are finished before enterring
719 // the interrupt.
720 if (cpu->instList.empty()) {
721 // Squash or record that I need to squash this cycle if
722 // an interrupt needed to be handled.
723 DPRINTF(Commit, "Interrupt detected.\n");
724
725 // Clear the interrupt now that it's going to be handled
726 toIEW->commitInfo[0].clearInterrupt = true;
727
728 assert(!thread[0]->inSyscall);
729 thread[0]->inSyscall = true;
730
731 // CPU will handle interrupt.
732 cpu->processInterrupts(interrupt);
733
734 thread[0]->inSyscall = false;
735
736 commitStatus[0] = TrapPending;
737
738 // Generate trap squash event.
739 generateTrapEvent(0);
740
741 interrupt = NoFault;
742 } else {
743 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
744 }
745}
746
747template <class Impl>
748void
749DefaultCommit<Impl>::propagateInterrupt()
750{
751 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
752 tcSquash[0])
753 return;
754
755 // Process interrupts if interrupts are enabled, not in PAL
756 // mode, and no other traps or external squashes are currently
757 // pending.
758 // @todo: Allow other threads to handle interrupts.
759
760 // Get any interrupt that happened
761 interrupt = cpu->getInterrupts();
762
763 // Tell fetch that there is an interrupt pending. This
764 // will make fetch wait until it sees a non PAL-mode PC,
765 // at which point it stops fetching instructions.
766 if (interrupt != NoFault)
767 toIEW->commitInfo[0].interruptPending = true;
768}
769
770#endif // FULL_SYSTEM
771
772template <class Impl>
773void
774DefaultCommit<Impl>::commit()
775{
776
777#if FULL_SYSTEM
778 // Check for any interrupt that we've already squashed for and start processing it.
779 if (interrupt != NoFault)
780 handleInterrupt();
781
782 // Check if we have a interrupt and get read to handle it
783 if (cpu->checkInterrupts(cpu->tcBase(0)))
784 propagateInterrupt();
785#endif // FULL_SYSTEM
786
787 ////////////////////////////////////
788 // Check for any possible squashes, handle them first
789 ////////////////////////////////////
790 list<ThreadID>::iterator threads = activeThreads->begin();
791 list<ThreadID>::iterator end = activeThreads->end();
792
793 while (threads != end) {
794 ThreadID tid = *threads++;
795
796 // Not sure which one takes priority. I think if we have
797 // both, that's a bad sign.
798 if (trapSquash[tid] == true) {
799 assert(!tcSquash[tid]);
800 squashFromTrap(tid);
801 } else if (tcSquash[tid] == true) {
802 assert(commitStatus[tid] != TrapPending);
803 squashFromTC(tid);
804 }
805
806 // Squashed sequence number must be older than youngest valid
807 // instruction in the ROB. This prevents squashes from younger
808 // instructions overriding squashes from older instructions.
809 if (fromIEW->squash[tid] &&
810 commitStatus[tid] != TrapPending &&
811 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
812
813 if (fromIEW->mispredictInst[tid]) {
814 DPRINTF(Commit,
815 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
816 tid,
817 fromIEW->mispredictInst[tid]->instAddr(),
818 fromIEW->squashedSeqNum[tid]);
819 } else {
820 DPRINTF(Commit,
821 "[tid:%i]: Squashing due to order violation [sn:%i]\n",
822 tid, fromIEW->squashedSeqNum[tid]);
823 }
824
825 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
826 tid,
827 fromIEW->pc[tid].nextInstAddr());
828
829 commitStatus[tid] = ROBSquashing;
830
831 // If we want to include the squashing instruction in the squash,
832 // then use one older sequence number.
833 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
834
835 if (fromIEW->includeSquashInst[tid] == true) {
836 squashed_inst--;
837 }
838
839 // All younger instructions will be squashed. Set the sequence
840 // number as the youngest instruction in the ROB.
841 youngestSeqNum[tid] = squashed_inst;
842
843 rob->squash(squashed_inst, tid);
844 changedROBNumEntries[tid] = true;
845
846 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
847
848 toIEW->commitInfo[tid].squash = true;
849
850 // Send back the rob squashing signal so other stages know that
851 // the ROB is in the process of squashing.
852 toIEW->commitInfo[tid].robSquashing = true;
853
854 toIEW->commitInfo[tid].mispredictInst =
855 fromIEW->mispredictInst[tid];
856 toIEW->commitInfo[tid].branchTaken =
857 fromIEW->branchTaken[tid];
858 toIEW->commitInfo[tid].squashInst = NULL;
859
860 toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
861
862 if (toIEW->commitInfo[tid].mispredictInst) {
863 ++branchMispredicts;
864 }
865 }
866
867 }
868
869 setNextStatus();
870
871 if (squashCounter != numThreads) {
872 // If we're not currently squashing, then get instructions.
873 getInsts();
874
875 // Try to commit any instructions.
876 commitInsts();
877 }
878
879 //Check for any activity
880 threads = activeThreads->begin();
881
882 while (threads != end) {
883 ThreadID tid = *threads++;
884
885 if (changedROBNumEntries[tid]) {
886 toIEW->commitInfo[tid].usedROB = true;
887 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
888
889 wroteToTimeBuffer = true;
890 changedROBNumEntries[tid] = false;
891 if (rob->isEmpty(tid))
892 checkEmptyROB[tid] = true;
893 }
894
895 // ROB is only considered "empty" for previous stages if: a)
896 // ROB is empty, b) there are no outstanding stores, c) IEW
897 // stage has received any information regarding stores that
898 // committed.
899 // c) is checked by making sure to not consider the ROB empty
900 // on the same cycle as when stores have been committed.
901 // @todo: Make this handle multi-cycle communication between
902 // commit and IEW.
903 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
904 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
905 checkEmptyROB[tid] = false;
906 toIEW->commitInfo[tid].usedROB = true;
907 toIEW->commitInfo[tid].emptyROB = true;
908 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
909 wroteToTimeBuffer = true;
910 }
911
912 }
913}
914
915template <class Impl>
916void
917DefaultCommit<Impl>::commitInsts()
918{
919 ////////////////////////////////////
920 // Handle commit
921 // Note that commit will be handled prior to putting new
922 // instructions in the ROB so that the ROB only tries to commit
923 // instructions it has in this current cycle, and not instructions
924 // it is writing in during this cycle. Can't commit and squash
925 // things at the same time...
926 ////////////////////////////////////
927
928 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
929
930 unsigned num_committed = 0;
931
932 DynInstPtr head_inst;
933
934 // Commit as many instructions as possible until the commit bandwidth
935 // limit is reached, or it becomes impossible to commit any more.
936 while (num_committed < commitWidth) {
937 int commit_thread = getCommittingThread();
938
939 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
940 break;
941
942 head_inst = rob->readHeadInst(commit_thread);
943
944 ThreadID tid = head_inst->threadNumber;
945
946 assert(tid == commit_thread);
947
948 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
949 head_inst->seqNum, tid);
950
951 // If the head instruction is squashed, it is ready to retire
952 // (be removed from the ROB) at any time.
953 if (head_inst->isSquashed()) {
954
955 DPRINTF(Commit, "Retiring squashed instruction from "
956 "ROB.\n");
957
958 rob->retireHead(commit_thread);
959
960 ++commitSquashedInsts;
961
962 // Record that the number of ROB entries has changed.
963 changedROBNumEntries[tid] = true;
964 } else {
965 pc[tid] = head_inst->pcState();
966
967 // Increment the total number of non-speculative instructions
968 // executed.
969 // Hack for now: it really shouldn't happen until after the
970 // commit is deemed to be successful, but this count is needed
971 // for syscalls.
972 thread[tid]->funcExeInst++;
973
974 // Try to commit the head instruction.
975 bool commit_success = commitHead(head_inst, num_committed);
976
977 if (commit_success) {
978 ++num_committed;
979
980 changedROBNumEntries[tid] = true;
981
982 // Set the doneSeqNum to the youngest committed instruction.
983 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
984
985 ++commitCommittedInsts;
986
987 // To match the old model, don't count nops and instruction
988 // prefetches towards the total commit count.
989 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
990 cpu->instDone(tid);
991 }
992
993 // Updates misc. registers.
994 head_inst->updateMiscRegs();
995
996 TheISA::advancePC(pc[tid], head_inst->staticInst);
997
998 // Keep track of the last sequence number commited
999 lastCommitedSeqNum[tid] = head_inst->seqNum;
1000
1001 // If this is an instruction that doesn't play nicely with
1002 // others squash everything and restart fetch
1003 if (head_inst->isSquashAfter())
1004 squashAfter(tid, head_inst, head_inst->seqNum);
1005
1006 int count = 0;
1007 Addr oldpc;
1008 // Debug statement. Checks to make sure we're not
1009 // currently updating state while handling PC events.
1010 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
1011 do {
1012 oldpc = pc[tid].instAddr();
1013 cpu->system->pcEventQueue.service(thread[tid]->getTC());
1014 count++;
1015 } while (oldpc != pc[tid].instAddr());
1016 if (count > 1) {
1017 DPRINTF(Commit,
1018 "PC skip function event, stopping commit\n");
1019 break;
1020 }
1021 } else {
1022 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1023 "[tid:%i] [sn:%i].\n",
1024 head_inst->pcState(), tid ,head_inst->seqNum);
1025 break;
1026 }
1027 }
1028 }
1029
1030 DPRINTF(CommitRate, "%i\n", num_committed);
1031 numCommittedDist.sample(num_committed);
1032
1033 if (num_committed == commitWidth) {
1034 commitEligibleSamples++;
1035 }
1036}
1037
1038template <class Impl>
1039bool
1040DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1041{
1042 assert(head_inst);
1043
1044 ThreadID tid = head_inst->threadNumber;
1045
1046 // If the instruction is not executed yet, then it will need extra
1047 // handling. Signal backwards that it should be executed.
1048 if (!head_inst->isExecuted()) {
1049 // Keep this number correct. We have not yet actually executed
1050 // and committed this instruction.
1051 thread[tid]->funcExeInst--;
1052
1053 if (head_inst->isNonSpeculative() ||
1054 head_inst->isStoreConditional() ||
1055 head_inst->isMemBarrier() ||
1056 head_inst->isWriteBarrier()) {
1057
1058 DPRINTF(Commit, "Encountered a barrier or non-speculative "
1059 "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1060 head_inst->seqNum, head_inst->pcState());
1061
1062 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1063 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1064 return false;
1065 }
1066
1067 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1068
1069 // Change the instruction so it won't try to commit again until
1070 // it is executed.
1071 head_inst->clearCanCommit();
1072
1073 ++commitNonSpecStalls;
1074
1075 return false;
1076 } else if (head_inst->isLoad()) {
1077 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1078 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1079 return false;
1080 }
1081
1082 assert(head_inst->uncacheable());
1083 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
1084 head_inst->seqNum, head_inst->pcState());
1085
1086 // Send back the non-speculative instruction's sequence
1087 // number. Tell the lsq to re-execute the load.
1088 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1089 toIEW->commitInfo[tid].uncached = true;
1090 toIEW->commitInfo[tid].uncachedLoad = head_inst;
1091
1092 head_inst->clearCanCommit();
1093
1094 return false;
1095 } else {
1096 panic("Trying to commit un-executed instruction "
1097 "of unknown type!\n");
1098 }
1099 }
1100
1101 if (head_inst->isThreadSync()) {
1102 // Not handled for now.
1103 panic("Thread sync instructions are not handled yet.\n");
1104 }
1105
1106 // Check if the instruction caused a fault. If so, trap.
1107 Fault inst_fault = head_inst->getFault();
1108
1109 // Stores mark themselves as completed.
1110 if (!head_inst->isStore() && inst_fault == NoFault) {
1111 head_inst->setCompleted();
1112 }
1113
1114#if USE_CHECKER
1115 // Use checker prior to updating anything due to traps or PC
1116 // based events.
1117 if (cpu->checker) {
1118 cpu->checker->verify(head_inst);
1119 }
1120#endif
1121
1122 if (inst_fault != NoFault) {
1123 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1124 head_inst->seqNum, head_inst->pcState());
1125
1126 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1127 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1128 return false;
1129 }
1130
1131 head_inst->setCompleted();
1132
1133#if USE_CHECKER
1134 if (cpu->checker && head_inst->isStore()) {
1135 cpu->checker->verify(head_inst);
1136 }
1137#endif
1138
1139 assert(!thread[tid]->inSyscall);
1140
1141 // Mark that we're in state update mode so that the trap's
1142 // execution doesn't generate extra squashes.
1143 thread[tid]->inSyscall = true;
1144
1145 // Execute the trap. Although it's slightly unrealistic in
1146 // terms of timing (as it doesn't wait for the full timing of
1147 // the trap event to complete before updating state), it's
1148 // needed to update the state as soon as possible. This
1149 // prevents external agents from changing any specific state
1150 // that the trap need.
1151 cpu->trap(inst_fault, tid, head_inst->staticInst);
1152
1153 // Exit state update mode to avoid accidental updating.
1154 thread[tid]->inSyscall = false;
1155
1156 commitStatus[tid] = TrapPending;
1157
1158 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1159 head_inst->seqNum);
1160 if (head_inst->traceData) {
1161 if (DTRACE(ExecFaulting)) {
1162 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1163 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1164 head_inst->traceData->dump();
1165 }
1166 delete head_inst->traceData;
1167 head_inst->traceData = NULL;
1168 }
1169
1170 // Generate trap squash event.
1171 generateTrapEvent(tid);
1172 return false;
1173 }
1174
1175 updateComInstStats(head_inst);
1176
1177#if FULL_SYSTEM
1178 if (thread[tid]->profile) {
1179 thread[tid]->profilePC = head_inst->instAddr();
1180 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1181 head_inst->staticInst);
1182
1183 if (node)
1184 thread[tid]->profileNode = node;
1185 }
1186 if (CPA::available()) {
1187 if (head_inst->isControl()) {
1188 ThreadContext *tc = thread[tid]->getTC();
1189 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1190 }
1191 }
1192#endif
1193 DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
1194 head_inst->seqNum, head_inst->pcState());
1195 if (head_inst->traceData) {
1196 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1197 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1198 head_inst->traceData->dump();
1199 delete head_inst->traceData;
1200 head_inst->traceData = NULL;
1201 }
1202
1203 // Update the commit rename map
1204 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1205 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1206 head_inst->renamedDestRegIdx(i));
1207 }
1208
1209 // Finally clear the head ROB entry.
1210 rob->retireHead(tid);
1211
1212#if TRACING_ON
1213 // Print info needed by the pipeline activity viewer.
1214 DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
1215 head_inst->fetchTick,
1216 head_inst->instAddr(),
1217 head_inst->microPC(),
1218 head_inst->seqNum,
1219 head_inst->staticInst->disassemble(head_inst->instAddr()));
1220 DPRINTFR(O3PipeView, "O3PipeView:decode:%llu\n", head_inst->decodeTick);
1221 DPRINTFR(O3PipeView, "O3PipeView:rename:%llu\n", head_inst->renameTick);
1222 DPRINTFR(O3PipeView, "O3PipeView:dispatch:%llu\n", head_inst->dispatchTick);
1223 DPRINTFR(O3PipeView, "O3PipeView:issue:%llu\n", head_inst->issueTick);
1224 DPRINTFR(O3PipeView, "O3PipeView:complete:%llu\n", head_inst->completeTick);
1225 DPRINTFR(O3PipeView, "O3PipeView:retire:%llu\n", curTick());
1226#endif
1227
1228 // If this was a store, record it for this cycle.
1229 if (head_inst->isStore())
1230 committedStores[tid] = true;
1231
1232 // Return true to indicate that we have committed an instruction.
1233 return true;
1234}
1235
1236template <class Impl>
1237void
1238DefaultCommit<Impl>::getInsts()
1239{
1240 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1241
1242 // Read any renamed instructions and place them into the ROB.
1243 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1244
1245 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1246 DynInstPtr inst;
1247
1248 inst = fromRename->insts[inst_num];
1249 ThreadID tid = inst->threadNumber;
1250
1251 if (!inst->isSquashed() &&
1252 commitStatus[tid] != ROBSquashing &&
1253 commitStatus[tid] != TrapPending) {
1254 changedROBNumEntries[tid] = true;
1255
1256 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1257 inst->pcState(), inst->seqNum, tid);
1258
1259 rob->insertInst(inst);
1260
1261 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1262
1263 youngestSeqNum[tid] = inst->seqNum;
1264 } else {
1265 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1266 "squashed, skipping.\n",
1267 inst->pcState(), inst->seqNum, tid);
1268 }
1269 }
1270}
1271
1272template <class Impl>
1273void
1274DefaultCommit<Impl>::skidInsert()
1275{
1276 DPRINTF(Commit, "Attempting to any instructions from rename into "
1277 "skidBuffer.\n");
1278
1279 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1280 DynInstPtr inst = fromRename->insts[inst_num];
1281
1282 if (!inst->isSquashed()) {
1283 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1284 "skidBuffer.\n", inst->pcState(), inst->seqNum,
1285 inst->threadNumber);
1286 skidBuffer.push(inst);
1287 } else {
1288 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1289 "squashed, skipping.\n",
1290 inst->pcState(), inst->seqNum, inst->threadNumber);
1291 }
1292 }
1293}
1294
1295template <class Impl>
1296void
1297DefaultCommit<Impl>::markCompletedInsts()
1298{
1299 // Grab completed insts out of the IEW instruction queue, and mark
1300 // instructions completed within the ROB.
1301 for (int inst_num = 0;
1302 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1303 ++inst_num)
1304 {
1305 if (!fromIEW->insts[inst_num]->isSquashed()) {
1306 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1307 "within ROB.\n",
1308 fromIEW->insts[inst_num]->threadNumber,
1309 fromIEW->insts[inst_num]->pcState(),
1310 fromIEW->insts[inst_num]->seqNum);
1311
1312 // Mark the instruction as ready to commit.
1313 fromIEW->insts[inst_num]->setCanCommit();
1314 }
1315 }
1316}
1317
1318template <class Impl>
1319bool
1320DefaultCommit<Impl>::robDoneSquashing()
1321{
1322 list<ThreadID>::iterator threads = activeThreads->begin();
1323 list<ThreadID>::iterator end = activeThreads->end();
1324
1325 while (threads != end) {
1326 ThreadID tid = *threads++;
1327
1328 if (!rob->isDoneSquashing(tid))
1329 return false;
1330 }
1331
1332 return true;
1333}
1334
1335template <class Impl>
1336void
1337DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1338{
1339 ThreadID tid = inst->threadNumber;
1340
1341 //
1342 // Pick off the software prefetches
1343 //
1344#ifdef TARGET_ALPHA
1345 if (inst->isDataPrefetch()) {
1346 statComSwp[tid]++;
1347 } else {
1348 statComInst[tid]++;
1349 }
1350#else
1351 statComInst[tid]++;
1352#endif
1353
1354 //
1355 // Control Instructions
1356 //
1357 if (inst->isControl())
1358 statComBranches[tid]++;
1359
1360 //
1361 // Memory references
1362 //
1363 if (inst->isMemRef()) {
1364 statComRefs[tid]++;
1365
1366 if (inst->isLoad()) {
1367 statComLoads[tid]++;
1368 }
1369 }
1370
1371 if (inst->isMemBarrier()) {
1372 statComMembars[tid]++;
1373 }
1374
1375 // Integer Instruction
1376 if (inst->isInteger())
1377 statComInteger[tid]++;
1378
1379 // Floating Point Instruction
1380 if (inst->isFloating())
1381 statComFloating[tid]++;
1382
1383 // Function Calls
1384 if (inst->isCall())
1385 statComFunctionCalls[tid]++;
1386
1387}
1388
1389////////////////////////////////////////
1390// //
1391// SMT COMMIT POLICY MAINTAINED HERE //
1392// //
1393////////////////////////////////////////
1394template <class Impl>
1395ThreadID
1396DefaultCommit<Impl>::getCommittingThread()
1397{
1398 if (numThreads > 1) {
1399 switch (commitPolicy) {
1400
1401 case Aggressive:
1402 //If Policy is Aggressive, commit will call
1403 //this function multiple times per
1404 //cycle
1405 return oldestReady();
1406
1407 case RoundRobin:
1408 return roundRobin();
1409
1410 case OldestReady:
1411 return oldestReady();
1412
1413 default:
1414 return InvalidThreadID;
1415 }
1416 } else {
1417 assert(!activeThreads->empty());
1418 ThreadID tid = activeThreads->front();
1419
1420 if (commitStatus[tid] == Running ||
1421 commitStatus[tid] == Idle ||
1422 commitStatus[tid] == FetchTrapPending) {
1423 return tid;
1424 } else {
1425 return InvalidThreadID;
1426 }
1427 }
1428}
1429
1430template<class Impl>
1431ThreadID
1432DefaultCommit<Impl>::roundRobin()
1433{
1434 list<ThreadID>::iterator pri_iter = priority_list.begin();
1435 list<ThreadID>::iterator end = priority_list.end();
1436
1437 while (pri_iter != end) {
1438 ThreadID tid = *pri_iter;
1439
1440 if (commitStatus[tid] == Running ||
1441 commitStatus[tid] == Idle ||
1442 commitStatus[tid] == FetchTrapPending) {
1443
1444 if (rob->isHeadReady(tid)) {
1445 priority_list.erase(pri_iter);
1446 priority_list.push_back(tid);
1447
1448 return tid;
1449 }
1450 }
1451
1452 pri_iter++;
1453 }
1454
1455 return InvalidThreadID;
1456}
1457
1458template<class Impl>
1459ThreadID
1460DefaultCommit<Impl>::oldestReady()
1461{
1462 unsigned oldest = 0;
1463 bool first = true;
1464
1465 list<ThreadID>::iterator threads = activeThreads->begin();
1466 list<ThreadID>::iterator end = activeThreads->end();
1467
1468 while (threads != end) {
1469 ThreadID tid = *threads++;
1470
1471 if (!rob->isEmpty(tid) &&
1472 (commitStatus[tid] == Running ||
1473 commitStatus[tid] == Idle ||
1474 commitStatus[tid] == FetchTrapPending)) {
1475
1476 if (rob->isHeadReady(tid)) {
1477
1478 DynInstPtr head_inst = rob->readHeadInst(tid);
1479
1480 if (first) {
1481 oldest = tid;
1482 first = false;
1483 } else if (head_inst->seqNum < oldest) {
1484 oldest = tid;
1485 }
1486 }
1487 }
1488 }
1489
1490 if (!first) {
1491 return oldest;
1492 } else {
1493 return InvalidThreadID;
1494 }
1495}