1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#include <algorithm>
45#include <string>
46
47#include "arch/utility.hh"
48#include "base/loader/symtab.hh"
49#include "base/cp_annotate.hh"
50#include "config/full_system.hh"
51#include "config/the_isa.hh"
52#include "config/use_checker.hh"
53#include "cpu/o3/commit.hh"
54#include "cpu/o3/thread_state.hh"
55#include "cpu/exetrace.hh"
56#include "cpu/timebuf.hh"
57#include "params/DerivO3CPU.hh"
58
59#if USE_CHECKER
60#include "cpu/checker/cpu.hh"
61#endif
62
63using namespace std;
64
65template <class Impl>
66DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
67 ThreadID _tid)
68 : Event(CPU_Tick_Pri), commit(_commit), tid(_tid)
69{
70 this->setFlags(AutoDelete);
71}
72
73template <class Impl>
74void
75DefaultCommit<Impl>::TrapEvent::process()
76{
77 // This will get reset by commit if it was switched out at the
78 // time of this event processing.
79 commit->trapSquash[tid] = true;
80}
81
82template <class Impl>
83const char *
84DefaultCommit<Impl>::TrapEvent::description() const
85{
86 return "Trap";
87}
88
89template <class Impl>
90DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
91 : cpu(_cpu),
92 squashCounter(0),
93 iewToCommitDelay(params->iewToCommitDelay),
94 commitToIEWDelay(params->commitToIEWDelay),
95 renameToROBDelay(params->renameToROBDelay),
96 fetchToCommitDelay(params->commitToFetchDelay),
97 renameWidth(params->renameWidth),
98 commitWidth(params->commitWidth),
99 numThreads(params->numThreads),
100 drainPending(false),
101 switchedOut(false),
102 trapLatency(params->trapLatency)
103{
104 _status = Active;
105 _nextStatus = Inactive;
106 std::string policy = params->smtCommitPolicy;
107
108 //Convert string to lowercase
109 std::transform(policy.begin(), policy.end(), policy.begin(),
110 (int(*)(int)) tolower);
111
112 //Assign commit policy
113 if (policy == "aggressive"){
114 commitPolicy = Aggressive;
115
116 DPRINTF(Commit,"Commit Policy set to Aggressive.");
117 } else if (policy == "roundrobin"){
118 commitPolicy = RoundRobin;
119
120 //Set-Up Priority List
121 for (ThreadID tid = 0; tid < numThreads; tid++) {
122 priority_list.push_back(tid);
123 }
124
125 DPRINTF(Commit,"Commit Policy set to Round Robin.");
126 } else if (policy == "oldestready"){
127 commitPolicy = OldestReady;
128
129 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
130 } else {
131 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
132 "RoundRobin,OldestReady}");
133 }
134
135 for (ThreadID tid = 0; tid < numThreads; tid++) {
136 commitStatus[tid] = Idle;
137 changedROBNumEntries[tid] = false;
138 checkEmptyROB[tid] = false;
139 trapInFlight[tid] = false;
140 committedStores[tid] = false;
141 trapSquash[tid] = false;
142 tcSquash[tid] = false;
143 pc[tid].set(0);
144 lastCommitedSeqNum[tid] = 0;
145 }
146#if FULL_SYSTEM
147 interrupt = NoFault;
148#endif
149}
150
151template <class Impl>
152std::string
153DefaultCommit<Impl>::name() const
154{
155 return cpu->name() + ".commit";
156}
157
158template <class Impl>
159void
160DefaultCommit<Impl>::regStats()
161{
162 using namespace Stats;
163 commitCommittedInsts
164 .name(name() + ".commitCommittedInsts")
165 .desc("The number of committed instructions")
166 .prereq(commitCommittedInsts);
167 commitSquashedInsts
168 .name(name() + ".commitSquashedInsts")
169 .desc("The number of squashed insts skipped by commit")
170 .prereq(commitSquashedInsts);
171 commitSquashEvents
172 .name(name() + ".commitSquashEvents")
173 .desc("The number of times commit is told to squash")
174 .prereq(commitSquashEvents);
175 commitNonSpecStalls
176 .name(name() + ".commitNonSpecStalls")
177 .desc("The number of times commit has been forced to stall to "
178 "communicate backwards")
179 .prereq(commitNonSpecStalls);
180 branchMispredicts
181 .name(name() + ".branchMispredicts")
182 .desc("The number of times a branch was mispredicted")
183 .prereq(branchMispredicts);
184 numCommittedDist
185 .init(0,commitWidth,1)
186 .name(name() + ".COM:committed_per_cycle")
187 .desc("Number of insts commited each cycle")
188 .flags(Stats::pdf)
189 ;
190
191 statComInst
192 .init(cpu->numThreads)
193 .name(name() + ".COM:count")
194 .desc("Number of instructions committed")
195 .flags(total)
196 ;
197
198 statComSwp
199 .init(cpu->numThreads)
200 .name(name() + ".COM:swp_count")
201 .desc("Number of s/w prefetches committed")
202 .flags(total)
203 ;
204
205 statComRefs
206 .init(cpu->numThreads)
207 .name(name() + ".COM:refs")
208 .desc("Number of memory references committed")
209 .flags(total)
210 ;
211
212 statComLoads
213 .init(cpu->numThreads)
214 .name(name() + ".COM:loads")
215 .desc("Number of loads committed")
216 .flags(total)
217 ;
218
219 statComMembars
220 .init(cpu->numThreads)
221 .name(name() + ".COM:membars")
222 .desc("Number of memory barriers committed")
223 .flags(total)
224 ;
225
226 statComBranches
227 .init(cpu->numThreads)
228 .name(name() + ".COM:branches")
229 .desc("Number of branches committed")
230 .flags(total)
231 ;
232
233 statComFloating
234 .init(cpu->numThreads)
235 .name(name() + ".COM:fp_insts")
236 .desc("Number of committed floating point instructions.")
237 .flags(total)
238 ;
239
240 statComInteger
241 .init(cpu->numThreads)
242 .name(name()+".COM:int_insts")
243 .desc("Number of committed integer instructions.")
244 .flags(total)
245 ;
246
247 statComFunctionCalls
248 .init(cpu->numThreads)
249 .name(name()+".COM:function_calls")
250 .desc("Number of function calls committed.")
251 .flags(total)
252 ;
253
254 commitEligible
255 .init(cpu->numThreads)
256 .name(name() + ".COM:bw_limited")
257 .desc("number of insts not committed due to BW limits")
258 .flags(total)
259 ;
260
261 commitEligibleSamples
262 .name(name() + ".COM:bw_lim_events")
263 .desc("number cycles where commit BW limit reached")
264 ;
265}
266
267template <class Impl>
268void
269DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
270{
271 thread = threads;
272}
273
274template <class Impl>
275void
276DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
277{
278 timeBuffer = tb_ptr;
279
280 // Setup wire to send information back to IEW.
281 toIEW = timeBuffer->getWire(0);
282
283 // Setup wire to read data from IEW (for the ROB).
284 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
285}
286
287template <class Impl>
288void
289DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
290{
291 fetchQueue = fq_ptr;
292
293 // Setup wire to get instructions from rename (for the ROB).
294 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
295}
296
297template <class Impl>
298void
299DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
300{
301 renameQueue = rq_ptr;
302
303 // Setup wire to get instructions from rename (for the ROB).
304 fromRename = renameQueue->getWire(-renameToROBDelay);
305}
306
307template <class Impl>
308void
309DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
310{
311 iewQueue = iq_ptr;
312
313 // Setup wire to get instructions from IEW.
314 fromIEW = iewQueue->getWire(-iewToCommitDelay);
315}
316
317template <class Impl>
318void
319DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
320{
321 iewStage = iew_stage;
322}
323
324template<class Impl>
325void
326DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
327{
328 activeThreads = at_ptr;
329}
330
331template <class Impl>
332void
333DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
334{
335 for (ThreadID tid = 0; tid < numThreads; tid++)
336 renameMap[tid] = &rm_ptr[tid];
337}
338
339template <class Impl>
340void
341DefaultCommit<Impl>::setROB(ROB *rob_ptr)
342{
343 rob = rob_ptr;
344}
345
346template <class Impl>
347void
348DefaultCommit<Impl>::initStage()
349{
350 rob->setActiveThreads(activeThreads);
351 rob->resetEntries();
352
353 // Broadcast the number of free entries.
354 for (ThreadID tid = 0; tid < numThreads; tid++) {
355 toIEW->commitInfo[tid].usedROB = true;
356 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
357 toIEW->commitInfo[tid].emptyROB = true;
358 }
359
360 // Commit must broadcast the number of free entries it has at the
361 // start of the simulation, so it starts as active.
362 cpu->activateStage(O3CPU::CommitIdx);
363
364 cpu->activityThisCycle();
365 trapLatency = cpu->ticks(trapLatency);
366}
367
368template <class Impl>
369bool
370DefaultCommit<Impl>::drain()
371{
372 drainPending = true;
373
374 return false;
375}
376
377template <class Impl>
378void
379DefaultCommit<Impl>::switchOut()
380{
381 switchedOut = true;
382 drainPending = false;
383 rob->switchOut();
384}
385
386template <class Impl>
387void
388DefaultCommit<Impl>::resume()
389{
390 drainPending = false;
391}
392
393template <class Impl>
394void
395DefaultCommit<Impl>::takeOverFrom()
396{
397 switchedOut = false;
398 _status = Active;
399 _nextStatus = Inactive;
400 for (ThreadID tid = 0; tid < numThreads; tid++) {
401 commitStatus[tid] = Idle;
402 changedROBNumEntries[tid] = false;
403 trapSquash[tid] = false;
404 tcSquash[tid] = false;
405 }
406 squashCounter = 0;
407 rob->takeOverFrom();
408}
409
410template <class Impl>
411void
412DefaultCommit<Impl>::updateStatus()
413{
414 // reset ROB changed variable
415 list<ThreadID>::iterator threads = activeThreads->begin();
416 list<ThreadID>::iterator end = activeThreads->end();
417
418 while (threads != end) {
419 ThreadID tid = *threads++;
420
421 changedROBNumEntries[tid] = false;
422
423 // Also check if any of the threads has a trap pending
424 if (commitStatus[tid] == TrapPending ||
425 commitStatus[tid] == FetchTrapPending) {
426 _nextStatus = Active;
427 }
428 }
429
430 if (_nextStatus == Inactive && _status == Active) {
431 DPRINTF(Activity, "Deactivating stage.\n");
432 cpu->deactivateStage(O3CPU::CommitIdx);
433 } else if (_nextStatus == Active && _status == Inactive) {
434 DPRINTF(Activity, "Activating stage.\n");
435 cpu->activateStage(O3CPU::CommitIdx);
436 }
437
438 _status = _nextStatus;
439}
440
441template <class Impl>
442void
443DefaultCommit<Impl>::setNextStatus()
444{
445 int squashes = 0;
446
447 list<ThreadID>::iterator threads = activeThreads->begin();
448 list<ThreadID>::iterator end = activeThreads->end();
449
450 while (threads != end) {
451 ThreadID tid = *threads++;
452
453 if (commitStatus[tid] == ROBSquashing) {
454 squashes++;
455 }
456 }
457
458 squashCounter = squashes;
459
460 // If commit is currently squashing, then it will have activity for the
461 // next cycle. Set its next status as active.
462 if (squashCounter) {
463 _nextStatus = Active;
464 }
465}
466
467template <class Impl>
468bool
469DefaultCommit<Impl>::changedROBEntries()
470{
471 list<ThreadID>::iterator threads = activeThreads->begin();
472 list<ThreadID>::iterator end = activeThreads->end();
473
474 while (threads != end) {
475 ThreadID tid = *threads++;
476
477 if (changedROBNumEntries[tid]) {
478 return true;
479 }
480 }
481
482 return false;
483}
484
485template <class Impl>
486size_t
487DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
488{
489 return rob->numFreeEntries(tid);
490}
491
492template <class Impl>
493void
494DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
495{
496 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
497
498 TrapEvent *trap = new TrapEvent(this, tid);
499
500 cpu->schedule(trap, curTick() + trapLatency);
501 trapInFlight[tid] = true;
502}
503
504template <class Impl>
505void
506DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
507{
508 assert(!trapInFlight[tid]);
509 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
510
511 tcSquash[tid] = true;
512}
513
514template <class Impl>
515void
516DefaultCommit<Impl>::squashAll(ThreadID tid)
517{
518 // If we want to include the squashing instruction in the squash,
519 // then use one older sequence number.
520 // Hopefully this doesn't mess things up. Basically I want to squash
521 // all instructions of this thread.
522 InstSeqNum squashed_inst = rob->isEmpty() ?
523 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
524
525 // All younger instructions will be squashed. Set the sequence
526 // number as the youngest instruction in the ROB (0 in this case.
527 // Hopefully nothing breaks.)
528 youngestSeqNum[tid] = lastCommitedSeqNum[tid];
529
530 rob->squash(squashed_inst, tid);
531 changedROBNumEntries[tid] = true;
532
533 // Send back the sequence number of the squashed instruction.
534 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
535
536 // Send back the squash signal to tell stages that they should
537 // squash.
538 toIEW->commitInfo[tid].squash = true;
539
540 // Send back the rob squashing signal so other stages know that
541 // the ROB is in the process of squashing.
542 toIEW->commitInfo[tid].robSquashing = true;
543
544 toIEW->commitInfo[tid].mispredictInst = NULL;
545 toIEW->commitInfo[tid].squashInst = NULL;
546
547 toIEW->commitInfo[tid].pc = pc[tid];
548}
549
550template <class Impl>
551void
552DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
553{
554 squashAll(tid);
555
556 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
557
558 thread[tid]->trapPending = false;
559 thread[tid]->inSyscall = false;
560 trapInFlight[tid] = false;
561
562 trapSquash[tid] = false;
563
564 commitStatus[tid] = ROBSquashing;
565 cpu->activityThisCycle();
566}
567
568template <class Impl>
569void
570DefaultCommit<Impl>::squashFromTC(ThreadID tid)
571{
572 squashAll(tid);
573
574 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
575
576 thread[tid]->inSyscall = false;
577 assert(!thread[tid]->trapPending);
578
579 commitStatus[tid] = ROBSquashing;
580 cpu->activityThisCycle();
581
582 tcSquash[tid] = false;
583}
584
585template <class Impl>
586void
587DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst,
588 uint64_t squash_after_seq_num)
589{
590 youngestSeqNum[tid] = squash_after_seq_num;
591
592 rob->squash(squash_after_seq_num, tid);
593 changedROBNumEntries[tid] = true;
594
595 // Send back the sequence number of the squashed instruction.
596 toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num;
597
598 toIEW->commitInfo[tid].squashInst = head_inst;
599 // Send back the squash signal to tell stages that they should squash.
600 toIEW->commitInfo[tid].squash = true;
601
602 // Send back the rob squashing signal so other stages know that
603 // the ROB is in the process of squashing.
604 toIEW->commitInfo[tid].robSquashing = true;
605
606 toIEW->commitInfo[tid].mispredictInst = NULL;
607
608 toIEW->commitInfo[tid].pc = pc[tid];
609 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
610 tid, squash_after_seq_num);
611 commitStatus[tid] = ROBSquashing;
612}
613
614template <class Impl>
615void
616DefaultCommit<Impl>::tick()
617{
618 wroteToTimeBuffer = false;
619 _nextStatus = Inactive;
620
621 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
622 cpu->signalDrained();
623 drainPending = false;
624 return;
625 }
626
627 if (activeThreads->empty())
628 return;
629
630 list<ThreadID>::iterator threads = activeThreads->begin();
631 list<ThreadID>::iterator end = activeThreads->end();
632
633 // Check if any of the threads are done squashing. Change the
634 // status if they are done.
635 while (threads != end) {
636 ThreadID tid = *threads++;
637
638 // Clear the bit saying if the thread has committed stores
639 // this cycle.
640 committedStores[tid] = false;
641
642 if (commitStatus[tid] == ROBSquashing) {
643
644 if (rob->isDoneSquashing(tid)) {
645 commitStatus[tid] = Running;
646 } else {
647 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
648 " insts this cycle.\n", tid);
649 rob->doSquash(tid);
650 toIEW->commitInfo[tid].robSquashing = true;
651 wroteToTimeBuffer = true;
652 }
653 }
654 }
655
656 commit();
657
658 markCompletedInsts();
659
660 threads = activeThreads->begin();
661
662 while (threads != end) {
663 ThreadID tid = *threads++;
664
665 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
666 // The ROB has more instructions it can commit. Its next status
667 // will be active.
668 _nextStatus = Active;
669
670 DynInstPtr inst = rob->readHeadInst(tid);
671
672 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
673 " ROB and ready to commit\n",
674 tid, inst->seqNum, inst->pcState());
675
676 } else if (!rob->isEmpty(tid)) {
677 DynInstPtr inst = rob->readHeadInst(tid);
678
679 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
680 "%s is head of ROB and not ready\n",
681 tid, inst->seqNum, inst->pcState());
682 }
683
684 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
685 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
686 }
687
688
689 if (wroteToTimeBuffer) {
690 DPRINTF(Activity, "Activity This Cycle.\n");
691 cpu->activityThisCycle();
692 }
693
694 updateStatus();
695}
696
697#if FULL_SYSTEM
698template <class Impl>
699void
700DefaultCommit<Impl>::handleInterrupt()
701{
702 // Verify that we still have an interrupt to handle
703 if (!cpu->checkInterrupts(cpu->tcBase(0))) {
704 DPRINTF(Commit, "Pending interrupt is cleared by master before "
705 "it got handled. Restart fetching from the orig path.\n");
706 toIEW->commitInfo[0].clearInterrupt = true;
707 interrupt = NoFault;
708 return;
709 }
710
711 // Wait until the ROB is empty and all stores have drained in
712 // order to enter the interrupt.
713 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
714 // Squash or record that I need to squash this cycle if
715 // an interrupt needed to be handled.
716 DPRINTF(Commit, "Interrupt detected.\n");
717
718 // Clear the interrupt now that it's going to be handled
719 toIEW->commitInfo[0].clearInterrupt = true;
720
721 assert(!thread[0]->inSyscall);
722 thread[0]->inSyscall = true;
723
724 // CPU will handle interrupt.
725 cpu->processInterrupts(interrupt);
726
727 thread[0]->inSyscall = false;
728
729 commitStatus[0] = TrapPending;
730
731 // Generate trap squash event.
732 generateTrapEvent(0);
733
734 interrupt = NoFault;
735 } else {
736 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
737 }
738}
739
740template <class Impl>
741void
742DefaultCommit<Impl>::propagateInterrupt()
743{
744 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
745 tcSquash[0])
746 return;
747
748 // Process interrupts if interrupts are enabled, not in PAL
749 // mode, and no other traps or external squashes are currently
750 // pending.
751 // @todo: Allow other threads to handle interrupts.
752
753 // Get any interrupt that happened
754 interrupt = cpu->getInterrupts();
755
756 // Tell fetch that there is an interrupt pending. This
757 // will make fetch wait until it sees a non PAL-mode PC,
758 // at which point it stops fetching instructions.
759 if (interrupt != NoFault)
760 toIEW->commitInfo[0].interruptPending = true;
761}
762
763#endif // FULL_SYSTEM
764
765template <class Impl>
766void
767DefaultCommit<Impl>::commit()
768{
769
770#if FULL_SYSTEM
771 // Check for any interrupt that we've already squashed for and start processing it.
772 if (interrupt != NoFault)
773 handleInterrupt();
774
775 // Check if we have a interrupt and get read to handle it
776 if (cpu->checkInterrupts(cpu->tcBase(0)))
777 propagateInterrupt();
778#endif // FULL_SYSTEM
779
780 ////////////////////////////////////
781 // Check for any possible squashes, handle them first
782 ////////////////////////////////////
783 list<ThreadID>::iterator threads = activeThreads->begin();
784 list<ThreadID>::iterator end = activeThreads->end();
785
786 while (threads != end) {
787 ThreadID tid = *threads++;
788
789 // Not sure which one takes priority. I think if we have
790 // both, that's a bad sign.
791 if (trapSquash[tid] == true) {
792 assert(!tcSquash[tid]);
793 squashFromTrap(tid);
794 } else if (tcSquash[tid] == true) {
795 assert(commitStatus[tid] != TrapPending);
796 squashFromTC(tid);
797 }
798
799 // Squashed sequence number must be older than youngest valid
800 // instruction in the ROB. This prevents squashes from younger
801 // instructions overriding squashes from older instructions.
802 if (fromIEW->squash[tid] &&
803 commitStatus[tid] != TrapPending &&
804 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
805
806 if (fromIEW->mispredictInst[tid]) {
807 DPRINTF(Commit,
808 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
809 tid,
810 fromIEW->mispredictInst[tid]->instAddr(),
811 fromIEW->squashedSeqNum[tid]);
812 } else {
813 DPRINTF(Commit,
814 "[tid:%i]: Squashing due to order violation [sn:%i]\n",
815 tid, fromIEW->squashedSeqNum[tid]);
816 }
817
818 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
819 tid,
820 fromIEW->pc[tid].nextInstAddr());
821
822 commitStatus[tid] = ROBSquashing;
823
824 // If we want to include the squashing instruction in the squash,
825 // then use one older sequence number.
826 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
827
828 if (fromIEW->includeSquashInst[tid] == true) {
829 squashed_inst--;
830 }
831
832 // All younger instructions will be squashed. Set the sequence
833 // number as the youngest instruction in the ROB.
834 youngestSeqNum[tid] = squashed_inst;
835
836 rob->squash(squashed_inst, tid);
837 changedROBNumEntries[tid] = true;
838
839 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
840
841 toIEW->commitInfo[tid].squash = true;
842
843 // Send back the rob squashing signal so other stages know that
844 // the ROB is in the process of squashing.
845 toIEW->commitInfo[tid].robSquashing = true;
846
847 toIEW->commitInfo[tid].mispredictInst =
848 fromIEW->mispredictInst[tid];
849 toIEW->commitInfo[tid].branchTaken =
850 fromIEW->branchTaken[tid];
851 toIEW->commitInfo[tid].squashInst = NULL;
852
853 toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
854
855 if (toIEW->commitInfo[tid].mispredictInst) {
856 ++branchMispredicts;
857 }
858 }
859
860 }
861
862 setNextStatus();
863
864 if (squashCounter != numThreads) {
865 // If we're not currently squashing, then get instructions.
866 getInsts();
867
868 // Try to commit any instructions.
869 commitInsts();
870 }
871
872 //Check for any activity
873 threads = activeThreads->begin();
874
875 while (threads != end) {
876 ThreadID tid = *threads++;
877
878 if (changedROBNumEntries[tid]) {
879 toIEW->commitInfo[tid].usedROB = true;
880 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
881
882 wroteToTimeBuffer = true;
883 changedROBNumEntries[tid] = false;
884 if (rob->isEmpty(tid))
885 checkEmptyROB[tid] = true;
886 }
887
888 // ROB is only considered "empty" for previous stages if: a)
889 // ROB is empty, b) there are no outstanding stores, c) IEW
890 // stage has received any information regarding stores that
891 // committed.
892 // c) is checked by making sure to not consider the ROB empty
893 // on the same cycle as when stores have been committed.
894 // @todo: Make this handle multi-cycle communication between
895 // commit and IEW.
896 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
897 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
898 checkEmptyROB[tid] = false;
899 toIEW->commitInfo[tid].usedROB = true;
900 toIEW->commitInfo[tid].emptyROB = true;
901 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
902 wroteToTimeBuffer = true;
903 }
904
905 }
906}
907
908template <class Impl>
909void
910DefaultCommit<Impl>::commitInsts()
911{
912 ////////////////////////////////////
913 // Handle commit
914 // Note that commit will be handled prior to putting new
915 // instructions in the ROB so that the ROB only tries to commit
916 // instructions it has in this current cycle, and not instructions
917 // it is writing in during this cycle. Can't commit and squash
918 // things at the same time...
919 ////////////////////////////////////
920
921 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
922
923 unsigned num_committed = 0;
924
925 DynInstPtr head_inst;
926
927 // Commit as many instructions as possible until the commit bandwidth
928 // limit is reached, or it becomes impossible to commit any more.
929 while (num_committed < commitWidth) {
930 int commit_thread = getCommittingThread();
931
932 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
933 break;
934
935 head_inst = rob->readHeadInst(commit_thread);
936
937 ThreadID tid = head_inst->threadNumber;
938
939 assert(tid == commit_thread);
940
941 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
942 head_inst->seqNum, tid);
943
944 // If the head instruction is squashed, it is ready to retire
945 // (be removed from the ROB) at any time.
946 if (head_inst->isSquashed()) {
947
948 DPRINTF(Commit, "Retiring squashed instruction from "
949 "ROB.\n");
950
951 rob->retireHead(commit_thread);
952
953 ++commitSquashedInsts;
954
955 // Record that the number of ROB entries has changed.
956 changedROBNumEntries[tid] = true;
957 } else {
958 pc[tid] = head_inst->pcState();
959
960 // Increment the total number of non-speculative instructions
961 // executed.
962 // Hack for now: it really shouldn't happen until after the
963 // commit is deemed to be successful, but this count is needed
964 // for syscalls.
965 thread[tid]->funcExeInst++;
966
967 // Try to commit the head instruction.
968 bool commit_success = commitHead(head_inst, num_committed);
969
970 if (commit_success) {
971 ++num_committed;
972
973 changedROBNumEntries[tid] = true;
974
975 // Set the doneSeqNum to the youngest committed instruction.
976 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
977
978 ++commitCommittedInsts;
979
980 // To match the old model, don't count nops and instruction
981 // prefetches towards the total commit count.
982 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
983 cpu->instDone(tid);
984 }
985
986 // Updates misc. registers.
987 head_inst->updateMiscRegs();
988
989 TheISA::advancePC(pc[tid], head_inst->staticInst);
990
991 // Keep track of the last sequence number commited
992 lastCommitedSeqNum[tid] = head_inst->seqNum;
993
994 // If this is an instruction that doesn't play nicely with
995 // others squash everything and restart fetch
996 if (head_inst->isSquashAfter())
997 squashAfter(tid, head_inst, head_inst->seqNum);
998
999 int count = 0;
1000 Addr oldpc;
1001 // Debug statement. Checks to make sure we're not
1002 // currently updating state while handling PC events.
1003 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
1004 do {
1005 oldpc = pc[tid].instAddr();
1006 cpu->system->pcEventQueue.service(thread[tid]->getTC());
1007 count++;
1008 } while (oldpc != pc[tid].instAddr());
1009 if (count > 1) {
1010 DPRINTF(Commit,
1011 "PC skip function event, stopping commit\n");
1012 break;
1013 }
1014 } else {
1015 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1016 "[tid:%i] [sn:%i].\n",
1017 head_inst->pcState(), tid ,head_inst->seqNum);
1018 break;
1019 }
1020 }
1021 }
1022
1023 DPRINTF(CommitRate, "%i\n", num_committed);
1024 numCommittedDist.sample(num_committed);
1025
1026 if (num_committed == commitWidth) {
1027 commitEligibleSamples++;
1028 }
1029}
1030
1031template <class Impl>
1032bool
1033DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1034{
1035 assert(head_inst);
1036
1037 ThreadID tid = head_inst->threadNumber;
1038
1039 // If the instruction is not executed yet, then it will need extra
1040 // handling. Signal backwards that it should be executed.
1041 if (!head_inst->isExecuted()) {
1042 // Keep this number correct. We have not yet actually executed
1043 // and committed this instruction.
1044 thread[tid]->funcExeInst--;
1045
1046 if (head_inst->isNonSpeculative() ||
1047 head_inst->isStoreConditional() ||
1048 head_inst->isMemBarrier() ||
1049 head_inst->isWriteBarrier()) {
1050
1051 DPRINTF(Commit, "Encountered a barrier or non-speculative "
1052 "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1053 head_inst->seqNum, head_inst->pcState());
1054
1055 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1056 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1057 return false;
1058 }
1059
1060 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1061
1062 // Change the instruction so it won't try to commit again until
1063 // it is executed.
1064 head_inst->clearCanCommit();
1065
1066 ++commitNonSpecStalls;
1067
1068 return false;
1069 } else if (head_inst->isLoad()) {
1070 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1071 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1072 return false;
1073 }
1074
1075 assert(head_inst->uncacheable());
1076 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
1077 head_inst->seqNum, head_inst->pcState());
1078
1079 // Send back the non-speculative instruction's sequence
1080 // number. Tell the lsq to re-execute the load.
1081 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1082 toIEW->commitInfo[tid].uncached = true;
1083 toIEW->commitInfo[tid].uncachedLoad = head_inst;
1084
1085 head_inst->clearCanCommit();
1086
1087 return false;
1088 } else {
1089 panic("Trying to commit un-executed instruction "
1090 "of unknown type!\n");
1091 }
1092 }
1093
1094 if (head_inst->isThreadSync()) {
1095 // Not handled for now.
1096 panic("Thread sync instructions are not handled yet.\n");
1097 }
1098
1099 // Check if the instruction caused a fault. If so, trap.
1100 Fault inst_fault = head_inst->getFault();
1101
1102 // Stores mark themselves as completed.
1103 if (!head_inst->isStore() && inst_fault == NoFault) {
1104 head_inst->setCompleted();
1105 }
1106
1107#if USE_CHECKER
1108 // Use checker prior to updating anything due to traps or PC
1109 // based events.
1110 if (cpu->checker) {
1111 cpu->checker->verify(head_inst);
1112 }
1113#endif
1114
1115 if (inst_fault != NoFault) {
1116 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1117 head_inst->seqNum, head_inst->pcState());
1118
1119 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1120 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1121 return false;
1122 }
1123
1124 head_inst->setCompleted();
1125
1126#if USE_CHECKER
1127 if (cpu->checker && head_inst->isStore()) {
1128 cpu->checker->verify(head_inst);
1129 }
1130#endif
1131
1132 assert(!thread[tid]->inSyscall);
1133
1134 // Mark that we're in state update mode so that the trap's
1135 // execution doesn't generate extra squashes.
1136 thread[tid]->inSyscall = true;
1137
1138 // Execute the trap. Although it's slightly unrealistic in
1139 // terms of timing (as it doesn't wait for the full timing of
1140 // the trap event to complete before updating state), it's
1141 // needed to update the state as soon as possible. This
1142 // prevents external agents from changing any specific state
1143 // that the trap need.
1144 cpu->trap(inst_fault, tid, head_inst->staticInst);
1145
1146 // Exit state update mode to avoid accidental updating.
1147 thread[tid]->inSyscall = false;
1148
1149 commitStatus[tid] = TrapPending;
1150
1151 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1152 head_inst->seqNum);
1153 if (head_inst->traceData) {
1154 if (DTRACE(ExecFaulting)) {
1155 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1156 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1157 head_inst->traceData->dump();
1158 }
1159 delete head_inst->traceData;
1160 head_inst->traceData = NULL;
1161 }
1162
1163 // Generate trap squash event.
1164 generateTrapEvent(tid);
1165 return false;
1166 }
1167
1168 updateComInstStats(head_inst);
1169
1170#if FULL_SYSTEM
1171 if (thread[tid]->profile) {
1172 thread[tid]->profilePC = head_inst->instAddr();
1173 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1174 head_inst->staticInst);
1175
1176 if (node)
1177 thread[tid]->profileNode = node;
1178 }
1179 if (CPA::available()) {
1180 if (head_inst->isControl()) {
1181 ThreadContext *tc = thread[tid]->getTC();
1182 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1183 }
1184 }
1185#endif
1186 DPRINTF(Commit, "Committing instruction with [sn:%lli]\n",
1187 head_inst->seqNum);
1188 if (head_inst->traceData) {
1189 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1190 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1191 head_inst->traceData->dump();
1192 delete head_inst->traceData;
1193 head_inst->traceData = NULL;
1194 }
1195
1196 // Update the commit rename map
1197 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1198 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1199 head_inst->renamedDestRegIdx(i));
1200 }
1201
1202 // Finally clear the head ROB entry.
1203 rob->retireHead(tid);
1204
1205 // If this was a store, record it for this cycle.
1206 if (head_inst->isStore())
1207 committedStores[tid] = true;
1208
1209 // Return true to indicate that we have committed an instruction.
1210 return true;
1211}
1212
1213template <class Impl>
1214void
1215DefaultCommit<Impl>::getInsts()
1216{
1217 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1218
1219 // Read any renamed instructions and place them into the ROB.
1220 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1221
1222 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1223 DynInstPtr inst;
1224
1225 inst = fromRename->insts[inst_num];
1226 ThreadID tid = inst->threadNumber;
1227
1228 if (!inst->isSquashed() &&
1229 commitStatus[tid] != ROBSquashing &&
1230 commitStatus[tid] != TrapPending) {
1231 changedROBNumEntries[tid] = true;
1232
1233 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1234 inst->pcState(), inst->seqNum, tid);
1235
1236 rob->insertInst(inst);
1237
1238 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1239
1240 youngestSeqNum[tid] = inst->seqNum;
1241 } else {
1242 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1243 "squashed, skipping.\n",
1244 inst->pcState(), inst->seqNum, tid);
1245 }
1246 }
1247}
1248
1249template <class Impl>
1250void
1251DefaultCommit<Impl>::skidInsert()
1252{
1253 DPRINTF(Commit, "Attempting to any instructions from rename into "
1254 "skidBuffer.\n");
1255
1256 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1257 DynInstPtr inst = fromRename->insts[inst_num];
1258
1259 if (!inst->isSquashed()) {
1260 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1261 "skidBuffer.\n", inst->pcState(), inst->seqNum,
1262 inst->threadNumber);
1263 skidBuffer.push(inst);
1264 } else {
1265 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1266 "squashed, skipping.\n",
1267 inst->pcState(), inst->seqNum, inst->threadNumber);
1268 }
1269 }
1270}
1271
1272template <class Impl>
1273void
1274DefaultCommit<Impl>::markCompletedInsts()
1275{
1276 // Grab completed insts out of the IEW instruction queue, and mark
1277 // instructions completed within the ROB.
1278 for (int inst_num = 0;
1279 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1280 ++inst_num)
1281 {
1282 if (!fromIEW->insts[inst_num]->isSquashed()) {
1283 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1284 "within ROB.\n",
1285 fromIEW->insts[inst_num]->threadNumber,
1286 fromIEW->insts[inst_num]->pcState(),
1287 fromIEW->insts[inst_num]->seqNum);
1288
1289 // Mark the instruction as ready to commit.
1290 fromIEW->insts[inst_num]->setCanCommit();
1291 }
1292 }
1293}
1294
1295template <class Impl>
1296bool
1297DefaultCommit<Impl>::robDoneSquashing()
1298{
1299 list<ThreadID>::iterator threads = activeThreads->begin();
1300 list<ThreadID>::iterator end = activeThreads->end();
1301
1302 while (threads != end) {
1303 ThreadID tid = *threads++;
1304
1305 if (!rob->isDoneSquashing(tid))
1306 return false;
1307 }
1308
1309 return true;
1310}
1311
1312template <class Impl>
1313void
1314DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1315{
1316 ThreadID tid = inst->threadNumber;
1317
1318 //
1319 // Pick off the software prefetches
1320 //
1321#ifdef TARGET_ALPHA
1322 if (inst->isDataPrefetch()) {
1323 statComSwp[tid]++;
1324 } else {
1325 statComInst[tid]++;
1326 }
1327#else
1328 statComInst[tid]++;
1329#endif
1330
1331 //
1332 // Control Instructions
1333 //
1334 if (inst->isControl())
1335 statComBranches[tid]++;
1336
1337 //
1338 // Memory references
1339 //
1340 if (inst->isMemRef()) {
1341 statComRefs[tid]++;
1342
1343 if (inst->isLoad()) {
1344 statComLoads[tid]++;
1345 }
1346 }
1347
1348 if (inst->isMemBarrier()) {
1349 statComMembars[tid]++;
1350 }
1351
1352 // Integer Instruction
1353 if (inst->isInteger())
1354 statComInteger[tid]++;
1355
1356 // Floating Point Instruction
1357 if (inst->isFloating())
1358 statComFloating[tid]++;
1359
1360 // Function Calls
1361 if (inst->isCall())
1362 statComFunctionCalls[tid]++;
1363
1364}
1365
1366////////////////////////////////////////
1367// //
1368// SMT COMMIT POLICY MAINTAINED HERE //
1369// //
1370////////////////////////////////////////
1371template <class Impl>
1372ThreadID
1373DefaultCommit<Impl>::getCommittingThread()
1374{
1375 if (numThreads > 1) {
1376 switch (commitPolicy) {
1377
1378 case Aggressive:
1379 //If Policy is Aggressive, commit will call
1380 //this function multiple times per
1381 //cycle
1382 return oldestReady();
1383
1384 case RoundRobin:
1385 return roundRobin();
1386
1387 case OldestReady:
1388 return oldestReady();
1389
1390 default:
1391 return InvalidThreadID;
1392 }
1393 } else {
1394 assert(!activeThreads->empty());
1395 ThreadID tid = activeThreads->front();
1396
1397 if (commitStatus[tid] == Running ||
1398 commitStatus[tid] == Idle ||
1399 commitStatus[tid] == FetchTrapPending) {
1400 return tid;
1401 } else {
1402 return InvalidThreadID;
1403 }
1404 }
1405}
1406
1407template<class Impl>
1408ThreadID
1409DefaultCommit<Impl>::roundRobin()
1410{
1411 list<ThreadID>::iterator pri_iter = priority_list.begin();
1412 list<ThreadID>::iterator end = priority_list.end();
1413
1414 while (pri_iter != end) {
1415 ThreadID tid = *pri_iter;
1416
1417 if (commitStatus[tid] == Running ||
1418 commitStatus[tid] == Idle ||
1419 commitStatus[tid] == FetchTrapPending) {
1420
1421 if (rob->isHeadReady(tid)) {
1422 priority_list.erase(pri_iter);
1423 priority_list.push_back(tid);
1424
1425 return tid;
1426 }
1427 }
1428
1429 pri_iter++;
1430 }
1431
1432 return InvalidThreadID;
1433}
1434
1435template<class Impl>
1436ThreadID
1437DefaultCommit<Impl>::oldestReady()
1438{
1439 unsigned oldest = 0;
1440 bool first = true;
1441
1442 list<ThreadID>::iterator threads = activeThreads->begin();
1443 list<ThreadID>::iterator end = activeThreads->end();
1444
1445 while (threads != end) {
1446 ThreadID tid = *threads++;
1447
1448 if (!rob->isEmpty(tid) &&
1449 (commitStatus[tid] == Running ||
1450 commitStatus[tid] == Idle ||
1451 commitStatus[tid] == FetchTrapPending)) {
1452
1453 if (rob->isHeadReady(tid)) {
1454
1455 DynInstPtr head_inst = rob->readHeadInst(tid);
1456
1457 if (first) {
1458 oldest = tid;
1459 first = false;
1460 } else if (head_inst->seqNum < oldest) {
1461 oldest = tid;
1462 }
1463 }
1464 }
1465 }
1466
1467 if (!first) {
1468 return oldest;
1469 } else {
1470 return InvalidThreadID;
1471 }
1472}
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#include <algorithm>
45#include <string>
46
47#include "arch/utility.hh"
48#include "base/loader/symtab.hh"
49#include "base/cp_annotate.hh"
50#include "config/full_system.hh"
51#include "config/the_isa.hh"
52#include "config/use_checker.hh"
53#include "cpu/o3/commit.hh"
54#include "cpu/o3/thread_state.hh"
55#include "cpu/exetrace.hh"
56#include "cpu/timebuf.hh"
57#include "params/DerivO3CPU.hh"
58
59#if USE_CHECKER
60#include "cpu/checker/cpu.hh"
61#endif
62
63using namespace std;
64
65template <class Impl>
66DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
67 ThreadID _tid)
68 : Event(CPU_Tick_Pri), commit(_commit), tid(_tid)
69{
70 this->setFlags(AutoDelete);
71}
72
73template <class Impl>
74void
75DefaultCommit<Impl>::TrapEvent::process()
76{
77 // This will get reset by commit if it was switched out at the
78 // time of this event processing.
79 commit->trapSquash[tid] = true;
80}
81
82template <class Impl>
83const char *
84DefaultCommit<Impl>::TrapEvent::description() const
85{
86 return "Trap";
87}
88
89template <class Impl>
90DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
91 : cpu(_cpu),
92 squashCounter(0),
93 iewToCommitDelay(params->iewToCommitDelay),
94 commitToIEWDelay(params->commitToIEWDelay),
95 renameToROBDelay(params->renameToROBDelay),
96 fetchToCommitDelay(params->commitToFetchDelay),
97 renameWidth(params->renameWidth),
98 commitWidth(params->commitWidth),
99 numThreads(params->numThreads),
100 drainPending(false),
101 switchedOut(false),
102 trapLatency(params->trapLatency)
103{
104 _status = Active;
105 _nextStatus = Inactive;
106 std::string policy = params->smtCommitPolicy;
107
108 //Convert string to lowercase
109 std::transform(policy.begin(), policy.end(), policy.begin(),
110 (int(*)(int)) tolower);
111
112 //Assign commit policy
113 if (policy == "aggressive"){
114 commitPolicy = Aggressive;
115
116 DPRINTF(Commit,"Commit Policy set to Aggressive.");
117 } else if (policy == "roundrobin"){
118 commitPolicy = RoundRobin;
119
120 //Set-Up Priority List
121 for (ThreadID tid = 0; tid < numThreads; tid++) {
122 priority_list.push_back(tid);
123 }
124
125 DPRINTF(Commit,"Commit Policy set to Round Robin.");
126 } else if (policy == "oldestready"){
127 commitPolicy = OldestReady;
128
129 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
130 } else {
131 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
132 "RoundRobin,OldestReady}");
133 }
134
135 for (ThreadID tid = 0; tid < numThreads; tid++) {
136 commitStatus[tid] = Idle;
137 changedROBNumEntries[tid] = false;
138 checkEmptyROB[tid] = false;
139 trapInFlight[tid] = false;
140 committedStores[tid] = false;
141 trapSquash[tid] = false;
142 tcSquash[tid] = false;
143 pc[tid].set(0);
144 lastCommitedSeqNum[tid] = 0;
145 }
146#if FULL_SYSTEM
147 interrupt = NoFault;
148#endif
149}
150
151template <class Impl>
152std::string
153DefaultCommit<Impl>::name() const
154{
155 return cpu->name() + ".commit";
156}
157
158template <class Impl>
159void
160DefaultCommit<Impl>::regStats()
161{
162 using namespace Stats;
163 commitCommittedInsts
164 .name(name() + ".commitCommittedInsts")
165 .desc("The number of committed instructions")
166 .prereq(commitCommittedInsts);
167 commitSquashedInsts
168 .name(name() + ".commitSquashedInsts")
169 .desc("The number of squashed insts skipped by commit")
170 .prereq(commitSquashedInsts);
171 commitSquashEvents
172 .name(name() + ".commitSquashEvents")
173 .desc("The number of times commit is told to squash")
174 .prereq(commitSquashEvents);
175 commitNonSpecStalls
176 .name(name() + ".commitNonSpecStalls")
177 .desc("The number of times commit has been forced to stall to "
178 "communicate backwards")
179 .prereq(commitNonSpecStalls);
180 branchMispredicts
181 .name(name() + ".branchMispredicts")
182 .desc("The number of times a branch was mispredicted")
183 .prereq(branchMispredicts);
184 numCommittedDist
185 .init(0,commitWidth,1)
186 .name(name() + ".COM:committed_per_cycle")
187 .desc("Number of insts commited each cycle")
188 .flags(Stats::pdf)
189 ;
190
191 statComInst
192 .init(cpu->numThreads)
193 .name(name() + ".COM:count")
194 .desc("Number of instructions committed")
195 .flags(total)
196 ;
197
198 statComSwp
199 .init(cpu->numThreads)
200 .name(name() + ".COM:swp_count")
201 .desc("Number of s/w prefetches committed")
202 .flags(total)
203 ;
204
205 statComRefs
206 .init(cpu->numThreads)
207 .name(name() + ".COM:refs")
208 .desc("Number of memory references committed")
209 .flags(total)
210 ;
211
212 statComLoads
213 .init(cpu->numThreads)
214 .name(name() + ".COM:loads")
215 .desc("Number of loads committed")
216 .flags(total)
217 ;
218
219 statComMembars
220 .init(cpu->numThreads)
221 .name(name() + ".COM:membars")
222 .desc("Number of memory barriers committed")
223 .flags(total)
224 ;
225
226 statComBranches
227 .init(cpu->numThreads)
228 .name(name() + ".COM:branches")
229 .desc("Number of branches committed")
230 .flags(total)
231 ;
232
233 statComFloating
234 .init(cpu->numThreads)
235 .name(name() + ".COM:fp_insts")
236 .desc("Number of committed floating point instructions.")
237 .flags(total)
238 ;
239
240 statComInteger
241 .init(cpu->numThreads)
242 .name(name()+".COM:int_insts")
243 .desc("Number of committed integer instructions.")
244 .flags(total)
245 ;
246
247 statComFunctionCalls
248 .init(cpu->numThreads)
249 .name(name()+".COM:function_calls")
250 .desc("Number of function calls committed.")
251 .flags(total)
252 ;
253
254 commitEligible
255 .init(cpu->numThreads)
256 .name(name() + ".COM:bw_limited")
257 .desc("number of insts not committed due to BW limits")
258 .flags(total)
259 ;
260
261 commitEligibleSamples
262 .name(name() + ".COM:bw_lim_events")
263 .desc("number cycles where commit BW limit reached")
264 ;
265}
266
267template <class Impl>
268void
269DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
270{
271 thread = threads;
272}
273
274template <class Impl>
275void
276DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
277{
278 timeBuffer = tb_ptr;
279
280 // Setup wire to send information back to IEW.
281 toIEW = timeBuffer->getWire(0);
282
283 // Setup wire to read data from IEW (for the ROB).
284 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
285}
286
287template <class Impl>
288void
289DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
290{
291 fetchQueue = fq_ptr;
292
293 // Setup wire to get instructions from rename (for the ROB).
294 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
295}
296
297template <class Impl>
298void
299DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
300{
301 renameQueue = rq_ptr;
302
303 // Setup wire to get instructions from rename (for the ROB).
304 fromRename = renameQueue->getWire(-renameToROBDelay);
305}
306
307template <class Impl>
308void
309DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
310{
311 iewQueue = iq_ptr;
312
313 // Setup wire to get instructions from IEW.
314 fromIEW = iewQueue->getWire(-iewToCommitDelay);
315}
316
317template <class Impl>
318void
319DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
320{
321 iewStage = iew_stage;
322}
323
324template<class Impl>
325void
326DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
327{
328 activeThreads = at_ptr;
329}
330
331template <class Impl>
332void
333DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
334{
335 for (ThreadID tid = 0; tid < numThreads; tid++)
336 renameMap[tid] = &rm_ptr[tid];
337}
338
339template <class Impl>
340void
341DefaultCommit<Impl>::setROB(ROB *rob_ptr)
342{
343 rob = rob_ptr;
344}
345
346template <class Impl>
347void
348DefaultCommit<Impl>::initStage()
349{
350 rob->setActiveThreads(activeThreads);
351 rob->resetEntries();
352
353 // Broadcast the number of free entries.
354 for (ThreadID tid = 0; tid < numThreads; tid++) {
355 toIEW->commitInfo[tid].usedROB = true;
356 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
357 toIEW->commitInfo[tid].emptyROB = true;
358 }
359
360 // Commit must broadcast the number of free entries it has at the
361 // start of the simulation, so it starts as active.
362 cpu->activateStage(O3CPU::CommitIdx);
363
364 cpu->activityThisCycle();
365 trapLatency = cpu->ticks(trapLatency);
366}
367
368template <class Impl>
369bool
370DefaultCommit<Impl>::drain()
371{
372 drainPending = true;
373
374 return false;
375}
376
377template <class Impl>
378void
379DefaultCommit<Impl>::switchOut()
380{
381 switchedOut = true;
382 drainPending = false;
383 rob->switchOut();
384}
385
386template <class Impl>
387void
388DefaultCommit<Impl>::resume()
389{
390 drainPending = false;
391}
392
393template <class Impl>
394void
395DefaultCommit<Impl>::takeOverFrom()
396{
397 switchedOut = false;
398 _status = Active;
399 _nextStatus = Inactive;
400 for (ThreadID tid = 0; tid < numThreads; tid++) {
401 commitStatus[tid] = Idle;
402 changedROBNumEntries[tid] = false;
403 trapSquash[tid] = false;
404 tcSquash[tid] = false;
405 }
406 squashCounter = 0;
407 rob->takeOverFrom();
408}
409
410template <class Impl>
411void
412DefaultCommit<Impl>::updateStatus()
413{
414 // reset ROB changed variable
415 list<ThreadID>::iterator threads = activeThreads->begin();
416 list<ThreadID>::iterator end = activeThreads->end();
417
418 while (threads != end) {
419 ThreadID tid = *threads++;
420
421 changedROBNumEntries[tid] = false;
422
423 // Also check if any of the threads has a trap pending
424 if (commitStatus[tid] == TrapPending ||
425 commitStatus[tid] == FetchTrapPending) {
426 _nextStatus = Active;
427 }
428 }
429
430 if (_nextStatus == Inactive && _status == Active) {
431 DPRINTF(Activity, "Deactivating stage.\n");
432 cpu->deactivateStage(O3CPU::CommitIdx);
433 } else if (_nextStatus == Active && _status == Inactive) {
434 DPRINTF(Activity, "Activating stage.\n");
435 cpu->activateStage(O3CPU::CommitIdx);
436 }
437
438 _status = _nextStatus;
439}
440
441template <class Impl>
442void
443DefaultCommit<Impl>::setNextStatus()
444{
445 int squashes = 0;
446
447 list<ThreadID>::iterator threads = activeThreads->begin();
448 list<ThreadID>::iterator end = activeThreads->end();
449
450 while (threads != end) {
451 ThreadID tid = *threads++;
452
453 if (commitStatus[tid] == ROBSquashing) {
454 squashes++;
455 }
456 }
457
458 squashCounter = squashes;
459
460 // If commit is currently squashing, then it will have activity for the
461 // next cycle. Set its next status as active.
462 if (squashCounter) {
463 _nextStatus = Active;
464 }
465}
466
467template <class Impl>
468bool
469DefaultCommit<Impl>::changedROBEntries()
470{
471 list<ThreadID>::iterator threads = activeThreads->begin();
472 list<ThreadID>::iterator end = activeThreads->end();
473
474 while (threads != end) {
475 ThreadID tid = *threads++;
476
477 if (changedROBNumEntries[tid]) {
478 return true;
479 }
480 }
481
482 return false;
483}
484
485template <class Impl>
486size_t
487DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
488{
489 return rob->numFreeEntries(tid);
490}
491
492template <class Impl>
493void
494DefaultCommit<Impl>::generateTrapEvent(ThreadID tid)
495{
496 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
497
498 TrapEvent *trap = new TrapEvent(this, tid);
499
500 cpu->schedule(trap, curTick() + trapLatency);
501 trapInFlight[tid] = true;
502}
503
504template <class Impl>
505void
506DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
507{
508 assert(!trapInFlight[tid]);
509 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
510
511 tcSquash[tid] = true;
512}
513
514template <class Impl>
515void
516DefaultCommit<Impl>::squashAll(ThreadID tid)
517{
518 // If we want to include the squashing instruction in the squash,
519 // then use one older sequence number.
520 // Hopefully this doesn't mess things up. Basically I want to squash
521 // all instructions of this thread.
522 InstSeqNum squashed_inst = rob->isEmpty() ?
523 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
524
525 // All younger instructions will be squashed. Set the sequence
526 // number as the youngest instruction in the ROB (0 in this case.
527 // Hopefully nothing breaks.)
528 youngestSeqNum[tid] = lastCommitedSeqNum[tid];
529
530 rob->squash(squashed_inst, tid);
531 changedROBNumEntries[tid] = true;
532
533 // Send back the sequence number of the squashed instruction.
534 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
535
536 // Send back the squash signal to tell stages that they should
537 // squash.
538 toIEW->commitInfo[tid].squash = true;
539
540 // Send back the rob squashing signal so other stages know that
541 // the ROB is in the process of squashing.
542 toIEW->commitInfo[tid].robSquashing = true;
543
544 toIEW->commitInfo[tid].mispredictInst = NULL;
545 toIEW->commitInfo[tid].squashInst = NULL;
546
547 toIEW->commitInfo[tid].pc = pc[tid];
548}
549
550template <class Impl>
551void
552DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
553{
554 squashAll(tid);
555
556 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
557
558 thread[tid]->trapPending = false;
559 thread[tid]->inSyscall = false;
560 trapInFlight[tid] = false;
561
562 trapSquash[tid] = false;
563
564 commitStatus[tid] = ROBSquashing;
565 cpu->activityThisCycle();
566}
567
568template <class Impl>
569void
570DefaultCommit<Impl>::squashFromTC(ThreadID tid)
571{
572 squashAll(tid);
573
574 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
575
576 thread[tid]->inSyscall = false;
577 assert(!thread[tid]->trapPending);
578
579 commitStatus[tid] = ROBSquashing;
580 cpu->activityThisCycle();
581
582 tcSquash[tid] = false;
583}
584
585template <class Impl>
586void
587DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst,
588 uint64_t squash_after_seq_num)
589{
590 youngestSeqNum[tid] = squash_after_seq_num;
591
592 rob->squash(squash_after_seq_num, tid);
593 changedROBNumEntries[tid] = true;
594
595 // Send back the sequence number of the squashed instruction.
596 toIEW->commitInfo[tid].doneSeqNum = squash_after_seq_num;
597
598 toIEW->commitInfo[tid].squashInst = head_inst;
599 // Send back the squash signal to tell stages that they should squash.
600 toIEW->commitInfo[tid].squash = true;
601
602 // Send back the rob squashing signal so other stages know that
603 // the ROB is in the process of squashing.
604 toIEW->commitInfo[tid].robSquashing = true;
605
606 toIEW->commitInfo[tid].mispredictInst = NULL;
607
608 toIEW->commitInfo[tid].pc = pc[tid];
609 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
610 tid, squash_after_seq_num);
611 commitStatus[tid] = ROBSquashing;
612}
613
614template <class Impl>
615void
616DefaultCommit<Impl>::tick()
617{
618 wroteToTimeBuffer = false;
619 _nextStatus = Inactive;
620
621 if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
622 cpu->signalDrained();
623 drainPending = false;
624 return;
625 }
626
627 if (activeThreads->empty())
628 return;
629
630 list<ThreadID>::iterator threads = activeThreads->begin();
631 list<ThreadID>::iterator end = activeThreads->end();
632
633 // Check if any of the threads are done squashing. Change the
634 // status if they are done.
635 while (threads != end) {
636 ThreadID tid = *threads++;
637
638 // Clear the bit saying if the thread has committed stores
639 // this cycle.
640 committedStores[tid] = false;
641
642 if (commitStatus[tid] == ROBSquashing) {
643
644 if (rob->isDoneSquashing(tid)) {
645 commitStatus[tid] = Running;
646 } else {
647 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
648 " insts this cycle.\n", tid);
649 rob->doSquash(tid);
650 toIEW->commitInfo[tid].robSquashing = true;
651 wroteToTimeBuffer = true;
652 }
653 }
654 }
655
656 commit();
657
658 markCompletedInsts();
659
660 threads = activeThreads->begin();
661
662 while (threads != end) {
663 ThreadID tid = *threads++;
664
665 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
666 // The ROB has more instructions it can commit. Its next status
667 // will be active.
668 _nextStatus = Active;
669
670 DynInstPtr inst = rob->readHeadInst(tid);
671
672 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
673 " ROB and ready to commit\n",
674 tid, inst->seqNum, inst->pcState());
675
676 } else if (!rob->isEmpty(tid)) {
677 DynInstPtr inst = rob->readHeadInst(tid);
678
679 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
680 "%s is head of ROB and not ready\n",
681 tid, inst->seqNum, inst->pcState());
682 }
683
684 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
685 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
686 }
687
688
689 if (wroteToTimeBuffer) {
690 DPRINTF(Activity, "Activity This Cycle.\n");
691 cpu->activityThisCycle();
692 }
693
694 updateStatus();
695}
696
697#if FULL_SYSTEM
698template <class Impl>
699void
700DefaultCommit<Impl>::handleInterrupt()
701{
702 // Verify that we still have an interrupt to handle
703 if (!cpu->checkInterrupts(cpu->tcBase(0))) {
704 DPRINTF(Commit, "Pending interrupt is cleared by master before "
705 "it got handled. Restart fetching from the orig path.\n");
706 toIEW->commitInfo[0].clearInterrupt = true;
707 interrupt = NoFault;
708 return;
709 }
710
711 // Wait until the ROB is empty and all stores have drained in
712 // order to enter the interrupt.
713 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
714 // Squash or record that I need to squash this cycle if
715 // an interrupt needed to be handled.
716 DPRINTF(Commit, "Interrupt detected.\n");
717
718 // Clear the interrupt now that it's going to be handled
719 toIEW->commitInfo[0].clearInterrupt = true;
720
721 assert(!thread[0]->inSyscall);
722 thread[0]->inSyscall = true;
723
724 // CPU will handle interrupt.
725 cpu->processInterrupts(interrupt);
726
727 thread[0]->inSyscall = false;
728
729 commitStatus[0] = TrapPending;
730
731 // Generate trap squash event.
732 generateTrapEvent(0);
733
734 interrupt = NoFault;
735 } else {
736 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
737 }
738}
739
740template <class Impl>
741void
742DefaultCommit<Impl>::propagateInterrupt()
743{
744 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
745 tcSquash[0])
746 return;
747
748 // Process interrupts if interrupts are enabled, not in PAL
749 // mode, and no other traps or external squashes are currently
750 // pending.
751 // @todo: Allow other threads to handle interrupts.
752
753 // Get any interrupt that happened
754 interrupt = cpu->getInterrupts();
755
756 // Tell fetch that there is an interrupt pending. This
757 // will make fetch wait until it sees a non PAL-mode PC,
758 // at which point it stops fetching instructions.
759 if (interrupt != NoFault)
760 toIEW->commitInfo[0].interruptPending = true;
761}
762
763#endif // FULL_SYSTEM
764
765template <class Impl>
766void
767DefaultCommit<Impl>::commit()
768{
769
770#if FULL_SYSTEM
771 // Check for any interrupt that we've already squashed for and start processing it.
772 if (interrupt != NoFault)
773 handleInterrupt();
774
775 // Check if we have a interrupt and get read to handle it
776 if (cpu->checkInterrupts(cpu->tcBase(0)))
777 propagateInterrupt();
778#endif // FULL_SYSTEM
779
780 ////////////////////////////////////
781 // Check for any possible squashes, handle them first
782 ////////////////////////////////////
783 list<ThreadID>::iterator threads = activeThreads->begin();
784 list<ThreadID>::iterator end = activeThreads->end();
785
786 while (threads != end) {
787 ThreadID tid = *threads++;
788
789 // Not sure which one takes priority. I think if we have
790 // both, that's a bad sign.
791 if (trapSquash[tid] == true) {
792 assert(!tcSquash[tid]);
793 squashFromTrap(tid);
794 } else if (tcSquash[tid] == true) {
795 assert(commitStatus[tid] != TrapPending);
796 squashFromTC(tid);
797 }
798
799 // Squashed sequence number must be older than youngest valid
800 // instruction in the ROB. This prevents squashes from younger
801 // instructions overriding squashes from older instructions.
802 if (fromIEW->squash[tid] &&
803 commitStatus[tid] != TrapPending &&
804 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
805
806 if (fromIEW->mispredictInst[tid]) {
807 DPRINTF(Commit,
808 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
809 tid,
810 fromIEW->mispredictInst[tid]->instAddr(),
811 fromIEW->squashedSeqNum[tid]);
812 } else {
813 DPRINTF(Commit,
814 "[tid:%i]: Squashing due to order violation [sn:%i]\n",
815 tid, fromIEW->squashedSeqNum[tid]);
816 }
817
818 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
819 tid,
820 fromIEW->pc[tid].nextInstAddr());
821
822 commitStatus[tid] = ROBSquashing;
823
824 // If we want to include the squashing instruction in the squash,
825 // then use one older sequence number.
826 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
827
828 if (fromIEW->includeSquashInst[tid] == true) {
829 squashed_inst--;
830 }
831
832 // All younger instructions will be squashed. Set the sequence
833 // number as the youngest instruction in the ROB.
834 youngestSeqNum[tid] = squashed_inst;
835
836 rob->squash(squashed_inst, tid);
837 changedROBNumEntries[tid] = true;
838
839 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
840
841 toIEW->commitInfo[tid].squash = true;
842
843 // Send back the rob squashing signal so other stages know that
844 // the ROB is in the process of squashing.
845 toIEW->commitInfo[tid].robSquashing = true;
846
847 toIEW->commitInfo[tid].mispredictInst =
848 fromIEW->mispredictInst[tid];
849 toIEW->commitInfo[tid].branchTaken =
850 fromIEW->branchTaken[tid];
851 toIEW->commitInfo[tid].squashInst = NULL;
852
853 toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
854
855 if (toIEW->commitInfo[tid].mispredictInst) {
856 ++branchMispredicts;
857 }
858 }
859
860 }
861
862 setNextStatus();
863
864 if (squashCounter != numThreads) {
865 // If we're not currently squashing, then get instructions.
866 getInsts();
867
868 // Try to commit any instructions.
869 commitInsts();
870 }
871
872 //Check for any activity
873 threads = activeThreads->begin();
874
875 while (threads != end) {
876 ThreadID tid = *threads++;
877
878 if (changedROBNumEntries[tid]) {
879 toIEW->commitInfo[tid].usedROB = true;
880 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
881
882 wroteToTimeBuffer = true;
883 changedROBNumEntries[tid] = false;
884 if (rob->isEmpty(tid))
885 checkEmptyROB[tid] = true;
886 }
887
888 // ROB is only considered "empty" for previous stages if: a)
889 // ROB is empty, b) there are no outstanding stores, c) IEW
890 // stage has received any information regarding stores that
891 // committed.
892 // c) is checked by making sure to not consider the ROB empty
893 // on the same cycle as when stores have been committed.
894 // @todo: Make this handle multi-cycle communication between
895 // commit and IEW.
896 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
897 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
898 checkEmptyROB[tid] = false;
899 toIEW->commitInfo[tid].usedROB = true;
900 toIEW->commitInfo[tid].emptyROB = true;
901 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
902 wroteToTimeBuffer = true;
903 }
904
905 }
906}
907
908template <class Impl>
909void
910DefaultCommit<Impl>::commitInsts()
911{
912 ////////////////////////////////////
913 // Handle commit
914 // Note that commit will be handled prior to putting new
915 // instructions in the ROB so that the ROB only tries to commit
916 // instructions it has in this current cycle, and not instructions
917 // it is writing in during this cycle. Can't commit and squash
918 // things at the same time...
919 ////////////////////////////////////
920
921 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
922
923 unsigned num_committed = 0;
924
925 DynInstPtr head_inst;
926
927 // Commit as many instructions as possible until the commit bandwidth
928 // limit is reached, or it becomes impossible to commit any more.
929 while (num_committed < commitWidth) {
930 int commit_thread = getCommittingThread();
931
932 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
933 break;
934
935 head_inst = rob->readHeadInst(commit_thread);
936
937 ThreadID tid = head_inst->threadNumber;
938
939 assert(tid == commit_thread);
940
941 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
942 head_inst->seqNum, tid);
943
944 // If the head instruction is squashed, it is ready to retire
945 // (be removed from the ROB) at any time.
946 if (head_inst->isSquashed()) {
947
948 DPRINTF(Commit, "Retiring squashed instruction from "
949 "ROB.\n");
950
951 rob->retireHead(commit_thread);
952
953 ++commitSquashedInsts;
954
955 // Record that the number of ROB entries has changed.
956 changedROBNumEntries[tid] = true;
957 } else {
958 pc[tid] = head_inst->pcState();
959
960 // Increment the total number of non-speculative instructions
961 // executed.
962 // Hack for now: it really shouldn't happen until after the
963 // commit is deemed to be successful, but this count is needed
964 // for syscalls.
965 thread[tid]->funcExeInst++;
966
967 // Try to commit the head instruction.
968 bool commit_success = commitHead(head_inst, num_committed);
969
970 if (commit_success) {
971 ++num_committed;
972
973 changedROBNumEntries[tid] = true;
974
975 // Set the doneSeqNum to the youngest committed instruction.
976 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
977
978 ++commitCommittedInsts;
979
980 // To match the old model, don't count nops and instruction
981 // prefetches towards the total commit count.
982 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
983 cpu->instDone(tid);
984 }
985
986 // Updates misc. registers.
987 head_inst->updateMiscRegs();
988
989 TheISA::advancePC(pc[tid], head_inst->staticInst);
990
991 // Keep track of the last sequence number commited
992 lastCommitedSeqNum[tid] = head_inst->seqNum;
993
994 // If this is an instruction that doesn't play nicely with
995 // others squash everything and restart fetch
996 if (head_inst->isSquashAfter())
997 squashAfter(tid, head_inst, head_inst->seqNum);
998
999 int count = 0;
1000 Addr oldpc;
1001 // Debug statement. Checks to make sure we're not
1002 // currently updating state while handling PC events.
1003 assert(!thread[tid]->inSyscall && !thread[tid]->trapPending);
1004 do {
1005 oldpc = pc[tid].instAddr();
1006 cpu->system->pcEventQueue.service(thread[tid]->getTC());
1007 count++;
1008 } while (oldpc != pc[tid].instAddr());
1009 if (count > 1) {
1010 DPRINTF(Commit,
1011 "PC skip function event, stopping commit\n");
1012 break;
1013 }
1014 } else {
1015 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1016 "[tid:%i] [sn:%i].\n",
1017 head_inst->pcState(), tid ,head_inst->seqNum);
1018 break;
1019 }
1020 }
1021 }
1022
1023 DPRINTF(CommitRate, "%i\n", num_committed);
1024 numCommittedDist.sample(num_committed);
1025
1026 if (num_committed == commitWidth) {
1027 commitEligibleSamples++;
1028 }
1029}
1030
1031template <class Impl>
1032bool
1033DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1034{
1035 assert(head_inst);
1036
1037 ThreadID tid = head_inst->threadNumber;
1038
1039 // If the instruction is not executed yet, then it will need extra
1040 // handling. Signal backwards that it should be executed.
1041 if (!head_inst->isExecuted()) {
1042 // Keep this number correct. We have not yet actually executed
1043 // and committed this instruction.
1044 thread[tid]->funcExeInst--;
1045
1046 if (head_inst->isNonSpeculative() ||
1047 head_inst->isStoreConditional() ||
1048 head_inst->isMemBarrier() ||
1049 head_inst->isWriteBarrier()) {
1050
1051 DPRINTF(Commit, "Encountered a barrier or non-speculative "
1052 "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1053 head_inst->seqNum, head_inst->pcState());
1054
1055 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1056 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1057 return false;
1058 }
1059
1060 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1061
1062 // Change the instruction so it won't try to commit again until
1063 // it is executed.
1064 head_inst->clearCanCommit();
1065
1066 ++commitNonSpecStalls;
1067
1068 return false;
1069 } else if (head_inst->isLoad()) {
1070 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1071 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1072 return false;
1073 }
1074
1075 assert(head_inst->uncacheable());
1076 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %s.\n",
1077 head_inst->seqNum, head_inst->pcState());
1078
1079 // Send back the non-speculative instruction's sequence
1080 // number. Tell the lsq to re-execute the load.
1081 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1082 toIEW->commitInfo[tid].uncached = true;
1083 toIEW->commitInfo[tid].uncachedLoad = head_inst;
1084
1085 head_inst->clearCanCommit();
1086
1087 return false;
1088 } else {
1089 panic("Trying to commit un-executed instruction "
1090 "of unknown type!\n");
1091 }
1092 }
1093
1094 if (head_inst->isThreadSync()) {
1095 // Not handled for now.
1096 panic("Thread sync instructions are not handled yet.\n");
1097 }
1098
1099 // Check if the instruction caused a fault. If so, trap.
1100 Fault inst_fault = head_inst->getFault();
1101
1102 // Stores mark themselves as completed.
1103 if (!head_inst->isStore() && inst_fault == NoFault) {
1104 head_inst->setCompleted();
1105 }
1106
1107#if USE_CHECKER
1108 // Use checker prior to updating anything due to traps or PC
1109 // based events.
1110 if (cpu->checker) {
1111 cpu->checker->verify(head_inst);
1112 }
1113#endif
1114
1115 if (inst_fault != NoFault) {
1116 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1117 head_inst->seqNum, head_inst->pcState());
1118
1119 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1120 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1121 return false;
1122 }
1123
1124 head_inst->setCompleted();
1125
1126#if USE_CHECKER
1127 if (cpu->checker && head_inst->isStore()) {
1128 cpu->checker->verify(head_inst);
1129 }
1130#endif
1131
1132 assert(!thread[tid]->inSyscall);
1133
1134 // Mark that we're in state update mode so that the trap's
1135 // execution doesn't generate extra squashes.
1136 thread[tid]->inSyscall = true;
1137
1138 // Execute the trap. Although it's slightly unrealistic in
1139 // terms of timing (as it doesn't wait for the full timing of
1140 // the trap event to complete before updating state), it's
1141 // needed to update the state as soon as possible. This
1142 // prevents external agents from changing any specific state
1143 // that the trap need.
1144 cpu->trap(inst_fault, tid, head_inst->staticInst);
1145
1146 // Exit state update mode to avoid accidental updating.
1147 thread[tid]->inSyscall = false;
1148
1149 commitStatus[tid] = TrapPending;
1150
1151 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1152 head_inst->seqNum);
1153 if (head_inst->traceData) {
1154 if (DTRACE(ExecFaulting)) {
1155 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1156 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1157 head_inst->traceData->dump();
1158 }
1159 delete head_inst->traceData;
1160 head_inst->traceData = NULL;
1161 }
1162
1163 // Generate trap squash event.
1164 generateTrapEvent(tid);
1165 return false;
1166 }
1167
1168 updateComInstStats(head_inst);
1169
1170#if FULL_SYSTEM
1171 if (thread[tid]->profile) {
1172 thread[tid]->profilePC = head_inst->instAddr();
1173 ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(),
1174 head_inst->staticInst);
1175
1176 if (node)
1177 thread[tid]->profileNode = node;
1178 }
1179 if (CPA::available()) {
1180 if (head_inst->isControl()) {
1181 ThreadContext *tc = thread[tid]->getTC();
1182 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1183 }
1184 }
1185#endif
1186 DPRINTF(Commit, "Committing instruction with [sn:%lli]\n",
1187 head_inst->seqNum);
1188 if (head_inst->traceData) {
1189 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1190 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1191 head_inst->traceData->dump();
1192 delete head_inst->traceData;
1193 head_inst->traceData = NULL;
1194 }
1195
1196 // Update the commit rename map
1197 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1198 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1199 head_inst->renamedDestRegIdx(i));
1200 }
1201
1202 // Finally clear the head ROB entry.
1203 rob->retireHead(tid);
1204
1205 // If this was a store, record it for this cycle.
1206 if (head_inst->isStore())
1207 committedStores[tid] = true;
1208
1209 // Return true to indicate that we have committed an instruction.
1210 return true;
1211}
1212
1213template <class Impl>
1214void
1215DefaultCommit<Impl>::getInsts()
1216{
1217 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1218
1219 // Read any renamed instructions and place them into the ROB.
1220 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1221
1222 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1223 DynInstPtr inst;
1224
1225 inst = fromRename->insts[inst_num];
1226 ThreadID tid = inst->threadNumber;
1227
1228 if (!inst->isSquashed() &&
1229 commitStatus[tid] != ROBSquashing &&
1230 commitStatus[tid] != TrapPending) {
1231 changedROBNumEntries[tid] = true;
1232
1233 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1234 inst->pcState(), inst->seqNum, tid);
1235
1236 rob->insertInst(inst);
1237
1238 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1239
1240 youngestSeqNum[tid] = inst->seqNum;
1241 } else {
1242 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1243 "squashed, skipping.\n",
1244 inst->pcState(), inst->seqNum, tid);
1245 }
1246 }
1247}
1248
1249template <class Impl>
1250void
1251DefaultCommit<Impl>::skidInsert()
1252{
1253 DPRINTF(Commit, "Attempting to any instructions from rename into "
1254 "skidBuffer.\n");
1255
1256 for (int inst_num = 0; inst_num < fromRename->size; ++inst_num) {
1257 DynInstPtr inst = fromRename->insts[inst_num];
1258
1259 if (!inst->isSquashed()) {
1260 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ",
1261 "skidBuffer.\n", inst->pcState(), inst->seqNum,
1262 inst->threadNumber);
1263 skidBuffer.push(inst);
1264 } else {
1265 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1266 "squashed, skipping.\n",
1267 inst->pcState(), inst->seqNum, inst->threadNumber);
1268 }
1269 }
1270}
1271
1272template <class Impl>
1273void
1274DefaultCommit<Impl>::markCompletedInsts()
1275{
1276 // Grab completed insts out of the IEW instruction queue, and mark
1277 // instructions completed within the ROB.
1278 for (int inst_num = 0;
1279 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1280 ++inst_num)
1281 {
1282 if (!fromIEW->insts[inst_num]->isSquashed()) {
1283 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1284 "within ROB.\n",
1285 fromIEW->insts[inst_num]->threadNumber,
1286 fromIEW->insts[inst_num]->pcState(),
1287 fromIEW->insts[inst_num]->seqNum);
1288
1289 // Mark the instruction as ready to commit.
1290 fromIEW->insts[inst_num]->setCanCommit();
1291 }
1292 }
1293}
1294
1295template <class Impl>
1296bool
1297DefaultCommit<Impl>::robDoneSquashing()
1298{
1299 list<ThreadID>::iterator threads = activeThreads->begin();
1300 list<ThreadID>::iterator end = activeThreads->end();
1301
1302 while (threads != end) {
1303 ThreadID tid = *threads++;
1304
1305 if (!rob->isDoneSquashing(tid))
1306 return false;
1307 }
1308
1309 return true;
1310}
1311
1312template <class Impl>
1313void
1314DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1315{
1316 ThreadID tid = inst->threadNumber;
1317
1318 //
1319 // Pick off the software prefetches
1320 //
1321#ifdef TARGET_ALPHA
1322 if (inst->isDataPrefetch()) {
1323 statComSwp[tid]++;
1324 } else {
1325 statComInst[tid]++;
1326 }
1327#else
1328 statComInst[tid]++;
1329#endif
1330
1331 //
1332 // Control Instructions
1333 //
1334 if (inst->isControl())
1335 statComBranches[tid]++;
1336
1337 //
1338 // Memory references
1339 //
1340 if (inst->isMemRef()) {
1341 statComRefs[tid]++;
1342
1343 if (inst->isLoad()) {
1344 statComLoads[tid]++;
1345 }
1346 }
1347
1348 if (inst->isMemBarrier()) {
1349 statComMembars[tid]++;
1350 }
1351
1352 // Integer Instruction
1353 if (inst->isInteger())
1354 statComInteger[tid]++;
1355
1356 // Floating Point Instruction
1357 if (inst->isFloating())
1358 statComFloating[tid]++;
1359
1360 // Function Calls
1361 if (inst->isCall())
1362 statComFunctionCalls[tid]++;
1363
1364}
1365
1366////////////////////////////////////////
1367// //
1368// SMT COMMIT POLICY MAINTAINED HERE //
1369// //
1370////////////////////////////////////////
1371template <class Impl>
1372ThreadID
1373DefaultCommit<Impl>::getCommittingThread()
1374{
1375 if (numThreads > 1) {
1376 switch (commitPolicy) {
1377
1378 case Aggressive:
1379 //If Policy is Aggressive, commit will call
1380 //this function multiple times per
1381 //cycle
1382 return oldestReady();
1383
1384 case RoundRobin:
1385 return roundRobin();
1386
1387 case OldestReady:
1388 return oldestReady();
1389
1390 default:
1391 return InvalidThreadID;
1392 }
1393 } else {
1394 assert(!activeThreads->empty());
1395 ThreadID tid = activeThreads->front();
1396
1397 if (commitStatus[tid] == Running ||
1398 commitStatus[tid] == Idle ||
1399 commitStatus[tid] == FetchTrapPending) {
1400 return tid;
1401 } else {
1402 return InvalidThreadID;
1403 }
1404 }
1405}
1406
1407template<class Impl>
1408ThreadID
1409DefaultCommit<Impl>::roundRobin()
1410{
1411 list<ThreadID>::iterator pri_iter = priority_list.begin();
1412 list<ThreadID>::iterator end = priority_list.end();
1413
1414 while (pri_iter != end) {
1415 ThreadID tid = *pri_iter;
1416
1417 if (commitStatus[tid] == Running ||
1418 commitStatus[tid] == Idle ||
1419 commitStatus[tid] == FetchTrapPending) {
1420
1421 if (rob->isHeadReady(tid)) {
1422 priority_list.erase(pri_iter);
1423 priority_list.push_back(tid);
1424
1425 return tid;
1426 }
1427 }
1428
1429 pri_iter++;
1430 }
1431
1432 return InvalidThreadID;
1433}
1434
1435template<class Impl>
1436ThreadID
1437DefaultCommit<Impl>::oldestReady()
1438{
1439 unsigned oldest = 0;
1440 bool first = true;
1441
1442 list<ThreadID>::iterator threads = activeThreads->begin();
1443 list<ThreadID>::iterator end = activeThreads->end();
1444
1445 while (threads != end) {
1446 ThreadID tid = *threads++;
1447
1448 if (!rob->isEmpty(tid) &&
1449 (commitStatus[tid] == Running ||
1450 commitStatus[tid] == Idle ||
1451 commitStatus[tid] == FetchTrapPending)) {
1452
1453 if (rob->isHeadReady(tid)) {
1454
1455 DynInstPtr head_inst = rob->readHeadInst(tid);
1456
1457 if (first) {
1458 oldest = tid;
1459 first = false;
1460 } else if (head_inst->seqNum < oldest) {
1461 oldest = tid;
1462 }
1463 }
1464 }
1465 }
1466
1467 if (!first) {
1468 return oldest;
1469 } else {
1470 return InvalidThreadID;
1471 }
1472}