1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31#include <algorithm>
32#include <string>
33
34#include "base/loader/symtab.hh"
35#include "base/timebuf.hh"
36#include "cpu/checker/cpu.hh"
37#include "cpu/exetrace.hh"
38#include "cpu/o3/commit.hh"
39#include "cpu/o3/thread_state.hh"
40
41using namespace std;
42
43template <class Impl>
44DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
45 unsigned _tid)
46 : Event(&mainEventQueue, CPU_Tick_Pri), commit(_commit), tid(_tid)
47{
48 this->setFlags(Event::AutoDelete);
49}
50
51template <class Impl>
52void
53DefaultCommit<Impl>::TrapEvent::process()
54{
55 // This will get reset by commit if it was switched out at the
56 // time of this event processing.
57 commit->trapSquash[tid] = true;
58}
59
60template <class Impl>
61const char *
62DefaultCommit<Impl>::TrapEvent::description()
63{
64 return "Trap event";
65}
66
67template <class Impl>
68DefaultCommit<Impl>::DefaultCommit(Params *params)
69 : squashCounter(0),
70 iewToCommitDelay(params->iewToCommitDelay),
71 commitToIEWDelay(params->commitToIEWDelay),
72 renameToROBDelay(params->renameToROBDelay),
73 fetchToCommitDelay(params->commitToFetchDelay),
74 renameWidth(params->renameWidth),
75 commitWidth(params->commitWidth),
76 numThreads(params->numberOfThreads),
77 switchPending(false),
78 switchedOut(false),
79 trapLatency(params->trapLatency),
80 fetchTrapLatency(params->fetchTrapLatency)
81{
82 _status = Active;
83 _nextStatus = Inactive;
84 string policy = params->smtCommitPolicy;
85
86 //Convert string to lowercase
87 std::transform(policy.begin(), policy.end(), policy.begin(),
88 (int(*)(int)) tolower);
89
90 //Assign commit policy
91 if (policy == "aggressive"){
92 commitPolicy = Aggressive;
93
94 DPRINTF(Commit,"Commit Policy set to Aggressive.");
95 } else if (policy == "roundrobin"){
96 commitPolicy = RoundRobin;
97
98 //Set-Up Priority List
99 for (int tid=0; tid < numThreads; tid++) {
100 priority_list.push_back(tid);
101 }
102
103 DPRINTF(Commit,"Commit Policy set to Round Robin.");
104 } else if (policy == "oldestready"){
105 commitPolicy = OldestReady;
106
107 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
108 } else {
109 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
110 "RoundRobin,OldestReady}");
111 }
112
113 for (int i=0; i < numThreads; i++) {
114 commitStatus[i] = Idle;
115 changedROBNumEntries[i] = false;
116 trapSquash[i] = false;
117 tcSquash[i] = false;
118 PC[i] = nextPC[i] = 0;
119 }
120
121 fetchFaultTick = 0;
122 fetchTrapWait = 0;
123}
124
125template <class Impl>
126std::string
127DefaultCommit<Impl>::name() const
128{
129 return cpu->name() + ".commit";
130}
131
132template <class Impl>
133void
134DefaultCommit<Impl>::regStats()
135{
136 using namespace Stats;
137 commitCommittedInsts
138 .name(name() + ".commitCommittedInsts")
139 .desc("The number of committed instructions")
140 .prereq(commitCommittedInsts);
141 commitSquashedInsts
142 .name(name() + ".commitSquashedInsts")
143 .desc("The number of squashed insts skipped by commit")
144 .prereq(commitSquashedInsts);
145 commitSquashEvents
146 .name(name() + ".commitSquashEvents")
147 .desc("The number of times commit is told to squash")
148 .prereq(commitSquashEvents);
149 commitNonSpecStalls
150 .name(name() + ".commitNonSpecStalls")
151 .desc("The number of times commit has been forced to stall to "
152 "communicate backwards")
153 .prereq(commitNonSpecStalls);
154 branchMispredicts
155 .name(name() + ".branchMispredicts")
156 .desc("The number of times a branch was mispredicted")
157 .prereq(branchMispredicts);
158 numCommittedDist
159 .init(0,commitWidth,1)
160 .name(name() + ".COM:committed_per_cycle")
161 .desc("Number of insts commited each cycle")
162 .flags(Stats::pdf)
163 ;
164
165 statComInst
166 .init(cpu->number_of_threads)
167 .name(name() + ".COM:count")
168 .desc("Number of instructions committed")
169 .flags(total)
170 ;
171
172 statComSwp
173 .init(cpu->number_of_threads)
174 .name(name() + ".COM:swp_count")
175 .desc("Number of s/w prefetches committed")
176 .flags(total)
177 ;
178
179 statComRefs
180 .init(cpu->number_of_threads)
181 .name(name() + ".COM:refs")
182 .desc("Number of memory references committed")
183 .flags(total)
184 ;
185
186 statComLoads
187 .init(cpu->number_of_threads)
188 .name(name() + ".COM:loads")
189 .desc("Number of loads committed")
190 .flags(total)
191 ;
192
193 statComMembars
194 .init(cpu->number_of_threads)
195 .name(name() + ".COM:membars")
196 .desc("Number of memory barriers committed")
197 .flags(total)
198 ;
199
200 statComBranches
201 .init(cpu->number_of_threads)
202 .name(name() + ".COM:branches")
203 .desc("Number of branches committed")
204 .flags(total)
205 ;
206
207 //
208 // Commit-Eligible instructions...
209 //
210 // -> The number of instructions eligible to commit in those
211 // cycles where we reached our commit BW limit (less the number
212 // actually committed)
213 //
214 // -> The average value is computed over ALL CYCLES... not just
215 // the BW limited cycles
216 //
217 // -> The standard deviation is computed only over cycles where
218 // we reached the BW limit
219 //
220 commitEligible
221 .init(cpu->number_of_threads)
222 .name(name() + ".COM:bw_limited")
223 .desc("number of insts not committed due to BW limits")
224 .flags(total)
225 ;
226
227 commitEligibleSamples
228 .name(name() + ".COM:bw_lim_events")
229 .desc("number cycles where commit BW limit reached")
230 ;
231}
232
233template <class Impl>
234void
235DefaultCommit<Impl>::setCPU(FullCPU *cpu_ptr)
236{
237 DPRINTF(Commit, "Commit: Setting CPU pointer.\n");
238 cpu = cpu_ptr;
239
240 // Commit must broadcast the number of free entries it has at the start of
241 // the simulation, so it starts as active.
242 cpu->activateStage(FullCPU::CommitIdx);
243
244 trapLatency = cpu->cycles(trapLatency);
245 fetchTrapLatency = cpu->cycles(fetchTrapLatency);
246}
247
248template <class Impl>
249void
250DefaultCommit<Impl>::setThreads(vector<Thread *> &threads)
251{
252 thread = threads;
253}
254
255template <class Impl>
256void
257DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
258{
259 DPRINTF(Commit, "Commit: Setting time buffer pointer.\n");
260 timeBuffer = tb_ptr;
261
262 // Setup wire to send information back to IEW.
263 toIEW = timeBuffer->getWire(0);
264
265 // Setup wire to read data from IEW (for the ROB).
266 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
267}
268
269template <class Impl>
270void
271DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
272{
273 DPRINTF(Commit, "Commit: Setting fetch queue pointer.\n");
274 fetchQueue = fq_ptr;
275
276 // Setup wire to get instructions from rename (for the ROB).
277 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
278}
279
280template <class Impl>
281void
282DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
283{
284 DPRINTF(Commit, "Commit: Setting rename queue pointer.\n");
285 renameQueue = rq_ptr;
286
287 // Setup wire to get instructions from rename (for the ROB).
288 fromRename = renameQueue->getWire(-renameToROBDelay);
289}
290
291template <class Impl>
292void
293DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
294{
295 DPRINTF(Commit, "Commit: Setting IEW queue pointer.\n");
296 iewQueue = iq_ptr;
297
298 // Setup wire to get instructions from IEW.
299 fromIEW = iewQueue->getWire(-iewToCommitDelay);
300}
301
302template <class Impl>
303void
304DefaultCommit<Impl>::setFetchStage(Fetch *fetch_stage)
305{
306 fetchStage = fetch_stage;
307}
308
309template <class Impl>
310void
311DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
312{
313 iewStage = iew_stage;
314}
315
316template<class Impl>
317void
318DefaultCommit<Impl>::setActiveThreads(list<unsigned> *at_ptr)
319{
320 DPRINTF(Commit, "Commit: Setting active threads list pointer.\n");
321 activeThreads = at_ptr;
322}
323
324template <class Impl>
325void
326DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
327{
328 DPRINTF(Commit, "Setting rename map pointers.\n");
329
330 for (int i=0; i < numThreads; i++) {
331 renameMap[i] = &rm_ptr[i];
332 }
333}
334
335template <class Impl>
336void
337DefaultCommit<Impl>::setROB(ROB *rob_ptr)
338{
339 DPRINTF(Commit, "Commit: Setting ROB pointer.\n");
340 rob = rob_ptr;
341}
342
343template <class Impl>
344void
345DefaultCommit<Impl>::initStage()
346{
347 rob->setActiveThreads(activeThreads);
348 rob->resetEntries();
349
350 // Broadcast the number of free entries.
351 for (int i=0; i < numThreads; i++) {
352 toIEW->commitInfo[i].usedROB = true;
353 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
354 }
355
356 cpu->activityThisCycle();
357}
358
359template <class Impl>
360void
361DefaultCommit<Impl>::switchOut()
362{
363 switchPending = true;
364}
365
366template <class Impl>
367void
368DefaultCommit<Impl>::doSwitchOut()
369{
370 switchedOut = true;
371 switchPending = false;
372 rob->switchOut();
373}
374
375template <class Impl>
376void
377DefaultCommit<Impl>::takeOverFrom()
378{
379 switchedOut = false;
380 _status = Active;
381 _nextStatus = Inactive;
382 for (int i=0; i < numThreads; i++) {
383 commitStatus[i] = Idle;
384 changedROBNumEntries[i] = false;
385 trapSquash[i] = false;
386 tcSquash[i] = false;
387 }
388 squashCounter = 0;
389 rob->takeOverFrom();
390}
391
392template <class Impl>
393void
394DefaultCommit<Impl>::updateStatus()
395{
396 // reset ROB changed variable
397 list<unsigned>::iterator threads = (*activeThreads).begin();
398 while (threads != (*activeThreads).end()) {
399 unsigned tid = *threads++;
400 changedROBNumEntries[tid] = false;
401
402 // Also check if any of the threads has a trap pending
403 if (commitStatus[tid] == TrapPending ||
404 commitStatus[tid] == FetchTrapPending) {
405 _nextStatus = Active;
406 }
407 }
408
409 if (_nextStatus == Inactive && _status == Active) {
410 DPRINTF(Activity, "Deactivating stage.\n");
411 cpu->deactivateStage(FullCPU::CommitIdx);
412 } else if (_nextStatus == Active && _status == Inactive) {
413 DPRINTF(Activity, "Activating stage.\n");
414 cpu->activateStage(FullCPU::CommitIdx);
415 }
416
417 _status = _nextStatus;
418}
419
420template <class Impl>
421void
422DefaultCommit<Impl>::setNextStatus()
423{
424 int squashes = 0;
425
426 list<unsigned>::iterator threads = (*activeThreads).begin();
427
428 while (threads != (*activeThreads).end()) {
429 unsigned tid = *threads++;
430
431 if (commitStatus[tid] == ROBSquashing) {
432 squashes++;
433 }
434 }
435
436 squashCounter = squashes;
437
438 // If commit is currently squashing, then it will have activity for the
439 // next cycle. Set its next status as active.
440 if (squashCounter) {
441 _nextStatus = Active;
442 }
443}
444
445template <class Impl>
446bool
447DefaultCommit<Impl>::changedROBEntries()
448{
449 list<unsigned>::iterator threads = (*activeThreads).begin();
450
451 while (threads != (*activeThreads).end()) {
452 unsigned tid = *threads++;
453
454 if (changedROBNumEntries[tid]) {
455 return true;
456 }
457 }
458
459 return false;
460}
461
462template <class Impl>
463unsigned
464DefaultCommit<Impl>::numROBFreeEntries(unsigned tid)
465{
466 return rob->numFreeEntries(tid);
467}
468
469template <class Impl>
470void
471DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
472{
473 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
474
475 TrapEvent *trap = new TrapEvent(this, tid);
476
477 trap->schedule(curTick + trapLatency);
478
479 thread[tid]->trapPending = true;
480}
481
482template <class Impl>
483void
484DefaultCommit<Impl>::generateTCEvent(unsigned tid)
485{
486 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
487
488 tcSquash[tid] = true;
489}
490
491template <class Impl>
492void
493DefaultCommit<Impl>::squashAll(unsigned tid)
494{
495 // If we want to include the squashing instruction in the squash,
496 // then use one older sequence number.
497 // Hopefully this doesn't mess things up. Basically I want to squash
498 // all instructions of this thread.
499 InstSeqNum squashed_inst = rob->isEmpty() ?
500 0 : rob->readHeadInst(tid)->seqNum - 1;;
501
502 // All younger instructions will be squashed. Set the sequence
503 // number as the youngest instruction in the ROB (0 in this case.
504 // Hopefully nothing breaks.)
505 youngestSeqNum[tid] = 0;
506
507 rob->squash(squashed_inst, tid);
508 changedROBNumEntries[tid] = true;
509
510 // Send back the sequence number of the squashed instruction.
511 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
512
513 // Send back the squash signal to tell stages that they should
514 // squash.
515 toIEW->commitInfo[tid].squash = true;
516
517 // Send back the rob squashing signal so other stages know that
518 // the ROB is in the process of squashing.
519 toIEW->commitInfo[tid].robSquashing = true;
520
521 toIEW->commitInfo[tid].branchMispredict = false;
522
523 toIEW->commitInfo[tid].nextPC = PC[tid];
524}
525
526template <class Impl>
527void
528DefaultCommit<Impl>::squashFromTrap(unsigned tid)
529{
530 squashAll(tid);
531
532 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
533
534 thread[tid]->trapPending = false;
535 thread[tid]->inSyscall = false;
536
537 trapSquash[tid] = false;
538
539 commitStatus[tid] = ROBSquashing;
540 cpu->activityThisCycle();
541}
542
543template <class Impl>
544void
545DefaultCommit<Impl>::squashFromTC(unsigned tid)
546{
547 squashAll(tid);
548
549 DPRINTF(Commit, "Squashing from TC, restarting at PC %#x\n", PC[tid]);
550
551 thread[tid]->inSyscall = false;
552 assert(!thread[tid]->trapPending);
553
554 commitStatus[tid] = ROBSquashing;
555 cpu->activityThisCycle();
556
557 tcSquash[tid] = false;
558}
559
560template <class Impl>
561void
562DefaultCommit<Impl>::tick()
563{
564 wroteToTimeBuffer = false;
565 _nextStatus = Inactive;
566
567 if (switchPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
568 cpu->signalSwitched();
569 return;
570 }
571
572 list<unsigned>::iterator threads = (*activeThreads).begin();
573
574 // Check if any of the threads are done squashing. Change the
575 // status if they are done.
576 while (threads != (*activeThreads).end()) {
577 unsigned tid = *threads++;
578
579 if (commitStatus[tid] == ROBSquashing) {
580
581 if (rob->isDoneSquashing(tid)) {
582 commitStatus[tid] = Running;
583 } else {
584 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
585 "insts this cycle.\n", tid);
586 rob->doSquash(tid);
587 toIEW->commitInfo[tid].robSquashing = true;
588 wroteToTimeBuffer = true;
589 }
590 }
591 }
592
593 commit();
594
595 markCompletedInsts();
596
597 threads = (*activeThreads).begin();
598
599 while (threads != (*activeThreads).end()) {
600 unsigned tid = *threads++;
601
602 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
603 // The ROB has more instructions it can commit. Its next status
604 // will be active.
605 _nextStatus = Active;
606
607 DynInstPtr inst = rob->readHeadInst(tid);
608
609 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %#x is head of"
610 " ROB and ready to commit\n",
611 tid, inst->seqNum, inst->readPC());
612
613 } else if (!rob->isEmpty(tid)) {
614 DynInstPtr inst = rob->readHeadInst(tid);
615
616 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
617 "%#x is head of ROB and not ready\n",
618 tid, inst->seqNum, inst->readPC());
619 }
620
621 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
622 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
623 }
624
625
626 if (wroteToTimeBuffer) {
627 DPRINTF(Activity, "Activity This Cycle.\n");
628 cpu->activityThisCycle();
629 }
630
631 updateStatus();
632}
633
634template <class Impl>
635void
636DefaultCommit<Impl>::commit()
637{
638
639 //////////////////////////////////////
640 // Check for interrupts
641 //////////////////////////////////////
642
643#if FULL_SYSTEM
644 // Process interrupts if interrupts are enabled, not in PAL mode,
645 // and no other traps or external squashes are currently pending.
646 // @todo: Allow other threads to handle interrupts.
647 if (cpu->checkInterrupts &&
648 cpu->check_interrupts() &&
649 !cpu->inPalMode(readPC()) &&
650 !trapSquash[0] &&
651 !tcSquash[0]) {
652 // Tell fetch that there is an interrupt pending. This will
653 // make fetch wait until it sees a non PAL-mode PC, at which
654 // point it stops fetching instructions.
655 toIEW->commitInfo[0].interruptPending = true;
656
657 // Wait until the ROB is empty and all stores have drained in
658 // order to enter the interrupt.
659 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
660 // Not sure which thread should be the one to interrupt. For now
661 // always do thread 0.
662 assert(!thread[0]->inSyscall);
663 thread[0]->inSyscall = true;
664
665 // CPU will handle implementation of the interrupt.
666 cpu->processInterrupts();
667
668 // Now squash or record that I need to squash this cycle.
669 commitStatus[0] = TrapPending;
670
671 // Exit state update mode to avoid accidental updating.
672 thread[0]->inSyscall = false;
673
674 // Generate trap squash event.
675 generateTrapEvent(0);
676
677 toIEW->commitInfo[0].clearInterrupt = true;
678
679 DPRINTF(Commit, "Interrupt detected.\n");
680 } else {
681 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
682 }
683 }
684#endif // FULL_SYSTEM
685
686 ////////////////////////////////////
687 // Check for any possible squashes, handle them first
688 ////////////////////////////////////
689
690 list<unsigned>::iterator threads = (*activeThreads).begin();
691
692 while (threads != (*activeThreads).end()) {
693 unsigned tid = *threads++;
694
695 // Not sure which one takes priority. I think if we have
696 // both, that's a bad sign.
697 if (trapSquash[tid] == true) {
698 assert(!tcSquash[tid]);
699 squashFromTrap(tid);
700 } else if (tcSquash[tid] == true) {
701 squashFromTC(tid);
702 }
703
704 // Squashed sequence number must be older than youngest valid
705 // instruction in the ROB. This prevents squashes from younger
706 // instructions overriding squashes from older instructions.
707 if (fromIEW->squash[tid] &&
708 commitStatus[tid] != TrapPending &&
709 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
710
711 DPRINTF(Commit, "[tid:%i]: Squashing due to PC %#x [sn:%i]\n",
712 tid,
713 fromIEW->mispredPC[tid],
714 fromIEW->squashedSeqNum[tid]);
715
716 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
717 tid,
718 fromIEW->nextPC[tid]);
719
720 commitStatus[tid] = ROBSquashing;
721
722 // If we want to include the squashing instruction in the squash,
723 // then use one older sequence number.
724 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
725
726 if (fromIEW->includeSquashInst[tid] == true)
727 squashed_inst--;
728
729 // All younger instructions will be squashed. Set the sequence
730 // number as the youngest instruction in the ROB.
731 youngestSeqNum[tid] = squashed_inst;
732
733 rob->squash(squashed_inst, tid);
734 changedROBNumEntries[tid] = true;
735
736 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
737
738 toIEW->commitInfo[tid].squash = true;
739
740 // Send back the rob squashing signal so other stages know that
741 // the ROB is in the process of squashing.
742 toIEW->commitInfo[tid].robSquashing = true;
743
744 toIEW->commitInfo[tid].branchMispredict =
745 fromIEW->branchMispredict[tid];
746
747 toIEW->commitInfo[tid].branchTaken =
748 fromIEW->branchTaken[tid];
749
750 toIEW->commitInfo[tid].nextPC = fromIEW->nextPC[tid];
751
752 toIEW->commitInfo[tid].mispredPC = fromIEW->mispredPC[tid];
753
754 if (toIEW->commitInfo[tid].branchMispredict) {
755 ++branchMispredicts;
756 }
757 }
758
759 }
760
761 setNextStatus();
762
763 if (squashCounter != numThreads) {
764 // If we're not currently squashing, then get instructions.
765 getInsts();
766
767 // Try to commit any instructions.
768 commitInsts();
769 }
770
771 //Check for any activity
772 threads = (*activeThreads).begin();
773
774 while (threads != (*activeThreads).end()) {
775 unsigned tid = *threads++;
776
777 if (changedROBNumEntries[tid]) {
778 toIEW->commitInfo[tid].usedROB = true;
779 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
780
781 if (rob->isEmpty(tid)) {
782 toIEW->commitInfo[tid].emptyROB = true;
783 }
784
785 wroteToTimeBuffer = true;
786 changedROBNumEntries[tid] = false;
787 }
788 }
789}
790
791template <class Impl>
792void
793DefaultCommit<Impl>::commitInsts()
794{
795 ////////////////////////////////////
796 // Handle commit
797 // Note that commit will be handled prior to putting new
798 // instructions in the ROB so that the ROB only tries to commit
799 // instructions it has in this current cycle, and not instructions
800 // it is writing in during this cycle. Can't commit and squash
801 // things at the same time...
802 ////////////////////////////////////
803
804 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
805
806 unsigned num_committed = 0;
807
808 DynInstPtr head_inst;
809
810 // Commit as many instructions as possible until the commit bandwidth
811 // limit is reached, or it becomes impossible to commit any more.
812 while (num_committed < commitWidth) {
813 int commit_thread = getCommittingThread();
814
815 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
816 break;
817
818 head_inst = rob->readHeadInst(commit_thread);
819
820 int tid = head_inst->threadNumber;
821
822 assert(tid == commit_thread);
823
824 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
825 head_inst->seqNum, tid);
826
827 // If the head instruction is squashed, it is ready to retire
828 // (be removed from the ROB) at any time.
829 if (head_inst->isSquashed()) {
830
831 DPRINTF(Commit, "Retiring squashed instruction from "
832 "ROB.\n");
833
834 rob->retireHead(commit_thread);
835
836 ++commitSquashedInsts;
837
838 // Record that the number of ROB entries has changed.
839 changedROBNumEntries[tid] = true;
840 } else {
841 PC[tid] = head_inst->readPC();
842 nextPC[tid] = head_inst->readNextPC();
843
844 // Increment the total number of non-speculative instructions
845 // executed.
846 // Hack for now: it really shouldn't happen until after the
847 // commit is deemed to be successful, but this count is needed
848 // for syscalls.
849 thread[tid]->funcExeInst++;
850
851 // Try to commit the head instruction.
852 bool commit_success = commitHead(head_inst, num_committed);
853
854 if (commit_success) {
855 ++num_committed;
856
857 changedROBNumEntries[tid] = true;
858
859 // Set the doneSeqNum to the youngest committed instruction.
860 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
861
862 ++commitCommittedInsts;
863
864 // To match the old model, don't count nops and instruction
865 // prefetches towards the total commit count.
866 if (!head_inst->isNop() && !head_inst->isInstPrefetch()) {
867 cpu->instDone(tid);
868 }
869
870 PC[tid] = nextPC[tid];
871 nextPC[tid] = nextPC[tid] + sizeof(TheISA::MachInst);
872#if FULL_SYSTEM
873 int count = 0;
874 Addr oldpc;
875 do {
876 // Debug statement. Checks to make sure we're not
877 // currently updating state while handling PC events.
878 if (count == 0)
879 assert(!thread[tid]->inSyscall &&
880 !thread[tid]->trapPending);
881 oldpc = PC[tid];
882 cpu->system->pcEventQueue.service(
883 thread[tid]->getTC());
884 count++;
885 } while (oldpc != PC[tid]);
886 if (count > 1) {
887 DPRINTF(Commit, "PC skip function event, stopping commit\n");
888 break;
889 }
890#endif
891 } else {
892 DPRINTF(Commit, "Unable to commit head instruction PC:%#x "
893 "[tid:%i] [sn:%i].\n",
894 head_inst->readPC(), tid ,head_inst->seqNum);
895 break;
896 }
897 }
898 }
899
900 DPRINTF(CommitRate, "%i\n", num_committed);
901 numCommittedDist.sample(num_committed);
902
903 if (num_committed == commitWidth) {
904 commitEligibleSamples++;
905 }
906}
907
908template <class Impl>
909bool
910DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
911{
912 assert(head_inst);
913
914 int tid = head_inst->threadNumber;
915
916 // If the instruction is not executed yet, then it will need extra
917 // handling. Signal backwards that it should be executed.
918 if (!head_inst->isExecuted()) {
919 // Keep this number correct. We have not yet actually executed
920 // and committed this instruction.
921 thread[tid]->funcExeInst--;
922
923 head_inst->reachedCommit = true;
924
925 if (head_inst->isNonSpeculative() ||
926 head_inst->isStoreConditional() ||
927 head_inst->isMemBarrier() ||
928 head_inst->isWriteBarrier()) {
929
930 DPRINTF(Commit, "Encountered a barrier or non-speculative "
931 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
932 head_inst->seqNum, head_inst->readPC());
933
934#if !FULL_SYSTEM
935 // Hack to make sure syscalls/memory barriers/quiesces
936 // aren't executed until all stores write back their data.
937 // This direct communication shouldn't be used for
938 // anything other than this.
939 if (inst_num > 0 || iewStage->hasStoresToWB())
940#else
941 if ((head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
942 head_inst->isQuiesce()) &&
943 iewStage->hasStoresToWB())
944#endif
945 {
946 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
947 return false;
948 }
949
950 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
951
952 // Change the instruction so it won't try to commit again until
953 // it is executed.
954 head_inst->clearCanCommit();
955
956 ++commitNonSpecStalls;
957
958 return false;
959 } else if (head_inst->isLoad()) {
960 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
961 head_inst->seqNum, head_inst->readPC());
962
963 // Send back the non-speculative instruction's sequence
964 // number. Tell the lsq to re-execute the load.
965 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
966 toIEW->commitInfo[tid].uncached = true;
967 toIEW->commitInfo[tid].uncachedLoad = head_inst;
968
969 head_inst->clearCanCommit();
970
971 return false;
972 } else {
973 panic("Trying to commit un-executed instruction "
974 "of unknown type!\n");
975 }
976 }
977
978 if (head_inst->isThreadSync()) {
979 // Not handled for now.
980 panic("Thread sync instructions are not handled yet.\n");
981 }
982
983 // Stores mark themselves as completed.
984 if (!head_inst->isStore()) {
985 head_inst->setCompleted();
986 }
987
988 // Use checker prior to updating anything due to traps or PC
989 // based events.
990 if (cpu->checker) {
991 cpu->checker->tick(head_inst);
992 }
993
994 // Check if the instruction caused a fault. If so, trap.
995 Fault inst_fault = head_inst->getFault();
996
997 if (inst_fault != NoFault) {
998 head_inst->setCompleted();
999#if FULL_SYSTEM
1000 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1001 head_inst->seqNum, head_inst->readPC());
1002
1003 if (iewStage->hasStoresToWB() || inst_num > 0) {
1004 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1005 return false;
1006 }
1007
1008 if (cpu->checker && head_inst->isStore()) {
1009 cpu->checker->tick(head_inst);
1010 }
1011
1012 assert(!thread[tid]->inSyscall);
1013
1014 // Mark that we're in state update mode so that the trap's
1015 // execution doesn't generate extra squashes.
1016 thread[tid]->inSyscall = true;
1017
1018 // DTB will sometimes need the machine instruction for when
1019 // faults happen. So we will set it here, prior to the DTB
1020 // possibly needing it for its fault.
1021 thread[tid]->setInst(
1022 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1023
1024 // Execute the trap. Although it's slightly unrealistic in
1025 // terms of timing (as it doesn't wait for the full timing of
1026 // the trap event to complete before updating state), it's
1027 // needed to update the state as soon as possible. This
1028 // prevents external agents from changing any specific state
1029 // that the trap need.
1030 cpu->trap(inst_fault, tid);
1031
1032 // Exit state update mode to avoid accidental updating.
1033 thread[tid]->inSyscall = false;
1034
1035 commitStatus[tid] = TrapPending;
1036
1037 // Generate trap squash event.
1038 generateTrapEvent(tid);
1039
1040 return false;
1041#else // !FULL_SYSTEM
1042 panic("fault (%d) detected @ PC %08p", inst_fault,
1043 head_inst->PC);
1044#endif // FULL_SYSTEM
1045 }
1046
1047 updateComInstStats(head_inst);
1048
1049 if (head_inst->traceData) {
1050 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1051 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1052 head_inst->traceData->finalize();
1053 head_inst->traceData = NULL;
1054 }
1055
1056 // Update the commit rename map
1057 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1058 renameMap[tid]->setEntry(head_inst->destRegIdx(i),
1059 head_inst->renamedDestRegIdx(i));
1060 }
1061
1062 // Finally clear the head ROB entry.
1063 rob->retireHead(tid);
1064
1065 // Return true to indicate that we have committed an instruction.
1066 return true;
1067}
1068
1069template <class Impl>
1070void
1071DefaultCommit<Impl>::getInsts()
1072{
1073 // Read any renamed instructions and place them into the ROB.
1074 int insts_to_process = min((int)renameWidth, fromRename->size);
1075
1076 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num)
1077 {
1078 DynInstPtr inst = fromRename->insts[inst_num];
1079 int tid = inst->threadNumber;
1080
1081 if (!inst->isSquashed() &&
1082 commitStatus[tid] != ROBSquashing) {
1083 changedROBNumEntries[tid] = true;
1084
1085 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1086 inst->readPC(), inst->seqNum, tid);
1087
1088 rob->insertInst(inst);
1089
1090 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1091
1092 youngestSeqNum[tid] = inst->seqNum;
1093 } else {
1094 DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was "
1095 "squashed, skipping.\n",
1096 inst->readPC(), inst->seqNum, tid);
1097 }
1098 }
1099}
1100
1101template <class Impl>
1102void
1103DefaultCommit<Impl>::markCompletedInsts()
1104{
1105 // Grab completed insts out of the IEW instruction queue, and mark
1106 // instructions completed within the ROB.
1107 for (int inst_num = 0;
1108 inst_num < fromIEW->size && fromIEW->insts[inst_num];
1109 ++inst_num)
1110 {
1111 if (!fromIEW->insts[inst_num]->isSquashed()) {
1112 DPRINTF(Commit, "[tid:%i]: Marking PC %#x, [sn:%lli] ready "
1113 "within ROB.\n",
1114 fromIEW->insts[inst_num]->threadNumber,
1115 fromIEW->insts[inst_num]->readPC(),
1116 fromIEW->insts[inst_num]->seqNum);
1117
1118 // Mark the instruction as ready to commit.
1119 fromIEW->insts[inst_num]->setCanCommit();
1120 }
1121 }
1122}
1123
1124template <class Impl>
1125bool
1126DefaultCommit<Impl>::robDoneSquashing()
1127{
1128 list<unsigned>::iterator threads = (*activeThreads).begin();
1129
1130 while (threads != (*activeThreads).end()) {
1131 unsigned tid = *threads++;
1132
1133 if (!rob->isDoneSquashing(tid))
1134 return false;
1135 }
1136
1137 return true;
1138}
1139
1140template <class Impl>
1141void
1142DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1143{
1144 unsigned thread = inst->threadNumber;
1145
1146 //
1147 // Pick off the software prefetches
1148 //
1149#ifdef TARGET_ALPHA
1150 if (inst->isDataPrefetch()) {
1151 statComSwp[thread]++;
1152 } else {
1153 statComInst[thread]++;
1154 }
1155#else
1156 statComInst[thread]++;
1157#endif
1158
1159 //
1160 // Control Instructions
1161 //
1162 if (inst->isControl())
1163 statComBranches[thread]++;
1164
1165 //
1166 // Memory references
1167 //
1168 if (inst->isMemRef()) {
1169 statComRefs[thread]++;
1170
1171 if (inst->isLoad()) {
1172 statComLoads[thread]++;
1173 }
1174 }
1175
1176 if (inst->isMemBarrier()) {
1177 statComMembars[thread]++;
1178 }
1179}
1180
1181////////////////////////////////////////
1182// //
1183// SMT COMMIT POLICY MAINTAINED HERE //
1184// //
1185////////////////////////////////////////
1186template <class Impl>
1187int
1188DefaultCommit<Impl>::getCommittingThread()
1189{
1190 if (numThreads > 1) {
1191 switch (commitPolicy) {
1192
1193 case Aggressive:
1194 //If Policy is Aggressive, commit will call
1195 //this function multiple times per
1196 //cycle
1197 return oldestReady();
1198
1199 case RoundRobin:
1200 return roundRobin();
1201
1202 case OldestReady:
1203 return oldestReady();
1204
1205 default:
1206 return -1;
1207 }
1208 } else {
1209 int tid = (*activeThreads).front();
1210
1211 if (commitStatus[tid] == Running ||
1212 commitStatus[tid] == Idle ||
1213 commitStatus[tid] == FetchTrapPending) {
1214 return tid;
1215 } else {
1216 return -1;
1217 }
1218 }
1219}
1220
1221template<class Impl>
1222int
1223DefaultCommit<Impl>::roundRobin()
1224{
1225 list<unsigned>::iterator pri_iter = priority_list.begin();
1226 list<unsigned>::iterator end = priority_list.end();
1227
1228 while (pri_iter != end) {
1229 unsigned tid = *pri_iter;
1230
1231 if (commitStatus[tid] == Running ||
1232 commitStatus[tid] == Idle) {
1233
1234 if (rob->isHeadReady(tid)) {
1235 priority_list.erase(pri_iter);
1236 priority_list.push_back(tid);
1237
1238 return tid;
1239 }
1240 }
1241
1242 pri_iter++;
1243 }
1244
1245 return -1;
1246}
1247
1248template<class Impl>
1249int
1250DefaultCommit<Impl>::oldestReady()
1251{
1252 unsigned oldest = 0;
1253 bool first = true;
1254
1255 list<unsigned>::iterator threads = (*activeThreads).begin();
1256
1257 while (threads != (*activeThreads).end()) {
1258 unsigned tid = *threads++;
1259
1260 if (!rob->isEmpty(tid) &&
1261 (commitStatus[tid] == Running ||
1262 commitStatus[tid] == Idle ||
1263 commitStatus[tid] == FetchTrapPending)) {
1264
1265 if (rob->isHeadReady(tid)) {
1266
1267 DynInstPtr head_inst = rob->readHeadInst(tid);
1268
1269 if (first) {
1270 oldest = tid;
1271 first = false;
1272 } else if (head_inst->seqNum < oldest) {
1273 oldest = tid;
1274 }
1275 }
1276 }
1277 }
1278
1279 if (!first) {
1280 return oldest;
1281 } else {
1282 return -1;
1283 }
1284}