1/*
2 * Copyright 2014 Google, Inc.
3 * Copyright (c) 2010-2014, 2017 ARM Limited
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 */
44#ifndef __CPU_O3_COMMIT_IMPL_HH__
45#define __CPU_O3_COMMIT_IMPL_HH__
46
47#include <algorithm>
48#include <set>
49#include <string>
50
51#include "arch/utility.hh"
52#include "base/loader/symtab.hh"
53#include "base/cp_annotate.hh"
54#include "config/the_isa.hh"
55#include "cpu/checker/cpu.hh"
56#include "cpu/o3/commit.hh"
57#include "cpu/o3/thread_state.hh"
58#include "cpu/base.hh"
59#include "cpu/exetrace.hh"
60#include "cpu/timebuf.hh"
61#include "debug/Activity.hh"
62#include "debug/Commit.hh"
63#include "debug/CommitRate.hh"
64#include "debug/Drain.hh"
65#include "debug/ExecFaulting.hh"
66#include "debug/O3PipeView.hh"
67#include "params/DerivO3CPU.hh"
68#include "sim/faults.hh"
69#include "sim/full_system.hh"
70
71using namespace std;
72
73template <class Impl>
74void
75DefaultCommit<Impl>::processTrapEvent(ThreadID tid)
76{
77 // This will get reset by commit if it was switched out at the
78 // time of this event processing.
79 trapSquash[tid] = true;
80}
81
82template <class Impl>
83DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
84 : cpu(_cpu),
85 iewToCommitDelay(params->iewToCommitDelay),
86 commitToIEWDelay(params->commitToIEWDelay),
87 renameToROBDelay(params->renameToROBDelay),
88 fetchToCommitDelay(params->commitToFetchDelay),
89 renameWidth(params->renameWidth),
90 commitWidth(params->commitWidth),
91 numThreads(params->numThreads),
92 drainPending(false),
93 drainImminent(false),
94 trapLatency(params->trapLatency),
95 canHandleInterrupts(true),
96 avoidQuiesceLiveLock(false)
97{
98 if (commitWidth > Impl::MaxWidth)
99 fatal("commitWidth (%d) is larger than compiled limit (%d),\n"
100 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
101 commitWidth, static_cast<int>(Impl::MaxWidth));
102
103 _status = Active;
104 _nextStatus = Inactive;
105 std::string policy = params->smtCommitPolicy;
106
107 //Convert string to lowercase
108 std::transform(policy.begin(), policy.end(), policy.begin(),
109 (int(*)(int)) tolower);
110
111 //Assign commit policy
112 if (policy == "aggressive"){
113 commitPolicy = Aggressive;
114
115 DPRINTF(Commit,"Commit Policy set to Aggressive.\n");
116 } else if (policy == "roundrobin"){
117 commitPolicy = RoundRobin;
118
119 //Set-Up Priority List
120 for (ThreadID tid = 0; tid < numThreads; tid++) {
121 priority_list.push_back(tid);
122 }
123
124 DPRINTF(Commit,"Commit Policy set to Round Robin.\n");
125 } else if (policy == "oldestready"){
126 commitPolicy = OldestReady;
127
128 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
129 } else {
130 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
131 "RoundRobin,OldestReady}");
132 }
133
134 for (ThreadID tid = 0; tid < numThreads; tid++) {
135 commitStatus[tid] = Idle;
136 changedROBNumEntries[tid] = false;
137 checkEmptyROB[tid] = false;
138 trapInFlight[tid] = false;
139 committedStores[tid] = false;
140 trapSquash[tid] = false;
141 tcSquash[tid] = false;
142 pc[tid].set(0);
143 lastCommitedSeqNum[tid] = 0;
144 squashAfterInst[tid] = NULL;
145 }
146 interrupt = NoFault;
147}
148
149template <class Impl>
150std::string
151DefaultCommit<Impl>::name() const
152{
153 return cpu->name() + ".commit";
154}
155
156template <class Impl>
157void
158DefaultCommit<Impl>::regProbePoints()
159{
160 ppCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Commit");
161 ppCommitStall = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "CommitStall");
162 ppSquash = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Squash");
163}
164
165template <class Impl>
166void
167DefaultCommit<Impl>::regStats()
168{
169 using namespace Stats;
170 commitSquashedInsts
171 .name(name() + ".commitSquashedInsts")
172 .desc("The number of squashed insts skipped by commit")
173 .prereq(commitSquashedInsts);
174
175 commitNonSpecStalls
176 .name(name() + ".commitNonSpecStalls")
177 .desc("The number of times commit has been forced to stall to "
178 "communicate backwards")
179 .prereq(commitNonSpecStalls);
180
181 branchMispredicts
182 .name(name() + ".branchMispredicts")
183 .desc("The number of times a branch was mispredicted")
184 .prereq(branchMispredicts);
185
186 numCommittedDist
187 .init(0,commitWidth,1)
188 .name(name() + ".committed_per_cycle")
189 .desc("Number of insts commited each cycle")
190 .flags(Stats::pdf)
191 ;
192
193 instsCommitted
194 .init(cpu->numThreads)
195 .name(name() + ".committedInsts")
196 .desc("Number of instructions committed")
197 .flags(total)
198 ;
199
200 opsCommitted
201 .init(cpu->numThreads)
202 .name(name() + ".committedOps")
203 .desc("Number of ops (including micro ops) committed")
204 .flags(total)
205 ;
206
207 statComSwp
208 .init(cpu->numThreads)
209 .name(name() + ".swp_count")
210 .desc("Number of s/w prefetches committed")
211 .flags(total)
212 ;
213
214 statComRefs
215 .init(cpu->numThreads)
216 .name(name() + ".refs")
217 .desc("Number of memory references committed")
218 .flags(total)
219 ;
220
221 statComLoads
222 .init(cpu->numThreads)
223 .name(name() + ".loads")
224 .desc("Number of loads committed")
225 .flags(total)
226 ;
227
228 statComMembars
229 .init(cpu->numThreads)
230 .name(name() + ".membars")
231 .desc("Number of memory barriers committed")
232 .flags(total)
233 ;
234
235 statComBranches
236 .init(cpu->numThreads)
237 .name(name() + ".branches")
238 .desc("Number of branches committed")
239 .flags(total)
240 ;
241
242 statComFloating
243 .init(cpu->numThreads)
244 .name(name() + ".fp_insts")
245 .desc("Number of committed floating point instructions.")
246 .flags(total)
247 ;
248
249 statComVector
250 .init(cpu->numThreads)
251 .name(name() + ".vec_insts")
252 .desc("Number of committed Vector instructions.")
253 .flags(total)
254 ;
255
256 statComInteger
257 .init(cpu->numThreads)
258 .name(name()+".int_insts")
259 .desc("Number of committed integer instructions.")
260 .flags(total)
261 ;
262
263 statComFunctionCalls
264 .init(cpu->numThreads)
265 .name(name()+".function_calls")
266 .desc("Number of function calls committed.")
267 .flags(total)
268 ;
269
270 statCommittedInstType
271 .init(numThreads,Enums::Num_OpClass)
272 .name(name() + ".op_class")
273 .desc("Class of committed instruction")
274 .flags(total | pdf | dist)
275 ;
276 statCommittedInstType.ysubnames(Enums::OpClassStrings);
277
278 commitEligibleSamples
279 .name(name() + ".bw_lim_events")
280 .desc("number cycles where commit BW limit reached")
281 ;
282}
283
284template <class Impl>
285void
286DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
287{
288 thread = threads;
289}
290
291template <class Impl>
292void
293DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
294{
295 timeBuffer = tb_ptr;
296
297 // Setup wire to send information back to IEW.
298 toIEW = timeBuffer->getWire(0);
299
300 // Setup wire to read data from IEW (for the ROB).
301 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
302}
303
304template <class Impl>
305void
306DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
307{
308 fetchQueue = fq_ptr;
309
310 // Setup wire to get instructions from rename (for the ROB).
311 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
312}
313
314template <class Impl>
315void
316DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
317{
318 renameQueue = rq_ptr;
319
320 // Setup wire to get instructions from rename (for the ROB).
321 fromRename = renameQueue->getWire(-renameToROBDelay);
322}
323
324template <class Impl>
325void
326DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
327{
328 iewQueue = iq_ptr;
329
330 // Setup wire to get instructions from IEW.
331 fromIEW = iewQueue->getWire(-iewToCommitDelay);
332}
333
334template <class Impl>
335void
336DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
337{
338 iewStage = iew_stage;
339}
340
341template<class Impl>
342void
343DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
344{
345 activeThreads = at_ptr;
346}
347
348template <class Impl>
349void
350DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
351{
352 for (ThreadID tid = 0; tid < numThreads; tid++)
353 renameMap[tid] = &rm_ptr[tid];
354}
355
356template <class Impl>
357void
358DefaultCommit<Impl>::setROB(ROB *rob_ptr)
359{
360 rob = rob_ptr;
361}
362
363template <class Impl>
364void
365DefaultCommit<Impl>::startupStage()
366{
367 rob->setActiveThreads(activeThreads);
368 rob->resetEntries();
369
370 // Broadcast the number of free entries.
371 for (ThreadID tid = 0; tid < numThreads; tid++) {
372 toIEW->commitInfo[tid].usedROB = true;
373 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
374 toIEW->commitInfo[tid].emptyROB = true;
375 }
376
377 // Commit must broadcast the number of free entries it has at the
378 // start of the simulation, so it starts as active.
379 cpu->activateStage(O3CPU::CommitIdx);
380
381 cpu->activityThisCycle();
382}
383
384template <class Impl>
385void
386DefaultCommit<Impl>::drain()
387{
388 drainPending = true;
389}
390
391template <class Impl>
392void
393DefaultCommit<Impl>::drainResume()
394{
395 drainPending = false;
396 drainImminent = false;
397}
398
399template <class Impl>
400void
401DefaultCommit<Impl>::drainSanityCheck() const
402{
403 assert(isDrained());
404 rob->drainSanityCheck();
405}
406
407template <class Impl>
408bool
409DefaultCommit<Impl>::isDrained() const
410{
411 /* Make sure no one is executing microcode. There are two reasons
412 * for this:
413 * - Hardware virtualized CPUs can't switch into the middle of a
414 * microcode sequence.
415 * - The current fetch implementation will most likely get very
416 * confused if it tries to start fetching an instruction that
417 * is executing in the middle of a ucode sequence that changes
418 * address mappings. This can happen on for example x86.
419 */
420 for (ThreadID tid = 0; tid < numThreads; tid++) {
421 if (pc[tid].microPC() != 0)
422 return false;
423 }
424
425 /* Make sure that all instructions have finished committing before
426 * declaring the system as drained. We want the pipeline to be
427 * completely empty when we declare the CPU to be drained. This
428 * makes debugging easier since CPU handover and restoring from a
429 * checkpoint with a different CPU should have the same timing.
430 */
431 return rob->isEmpty() &&
432 interrupt == NoFault;
433}
434
435template <class Impl>
436void
437DefaultCommit<Impl>::takeOverFrom()
438{
439 _status = Active;
440 _nextStatus = Inactive;
441 for (ThreadID tid = 0; tid < numThreads; tid++) {
442 commitStatus[tid] = Idle;
443 changedROBNumEntries[tid] = false;
444 trapSquash[tid] = false;
445 tcSquash[tid] = false;
446 squashAfterInst[tid] = NULL;
447 }
448 rob->takeOverFrom();
449}
450
451template <class Impl>
452void
453DefaultCommit<Impl>::deactivateThread(ThreadID tid)
454{
455 list<ThreadID>::iterator thread_it = std::find(priority_list.begin(),
456 priority_list.end(), tid);
457
458 if (thread_it != priority_list.end()) {
459 priority_list.erase(thread_it);
460 }
461}
462
463
464template <class Impl>
465void
466DefaultCommit<Impl>::updateStatus()
467{
468 // reset ROB changed variable
469 list<ThreadID>::iterator threads = activeThreads->begin();
470 list<ThreadID>::iterator end = activeThreads->end();
471
472 while (threads != end) {
473 ThreadID tid = *threads++;
474
475 changedROBNumEntries[tid] = false;
476
477 // Also check if any of the threads has a trap pending
478 if (commitStatus[tid] == TrapPending ||
479 commitStatus[tid] == FetchTrapPending) {
480 _nextStatus = Active;
481 }
482 }
483
484 if (_nextStatus == Inactive && _status == Active) {
485 DPRINTF(Activity, "Deactivating stage.\n");
486 cpu->deactivateStage(O3CPU::CommitIdx);
487 } else if (_nextStatus == Active && _status == Inactive) {
488 DPRINTF(Activity, "Activating stage.\n");
489 cpu->activateStage(O3CPU::CommitIdx);
490 }
491
492 _status = _nextStatus;
493}
494
495template <class Impl>
496bool
497DefaultCommit<Impl>::changedROBEntries()
498{
499 list<ThreadID>::iterator threads = activeThreads->begin();
500 list<ThreadID>::iterator end = activeThreads->end();
501
502 while (threads != end) {
503 ThreadID tid = *threads++;
504
505 if (changedROBNumEntries[tid]) {
506 return true;
507 }
508 }
509
510 return false;
511}
512
513template <class Impl>
514size_t
515DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
516{
517 return rob->numFreeEntries(tid);
518}
519
520template <class Impl>
521void
522DefaultCommit<Impl>::generateTrapEvent(ThreadID tid, Fault inst_fault)
523{
524 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
525
526 EventFunctionWrapper *trap = new EventFunctionWrapper(
527 [this, tid]{ processTrapEvent(tid); },
528 "Trap", true, Event::CPU_Tick_Pri);
529
530 Cycles latency = dynamic_pointer_cast<SyscallRetryFault>(inst_fault) ?
531 cpu->syscallRetryLatency : trapLatency;
532
533 cpu->schedule(trap, cpu->clockEdge(latency));
534 trapInFlight[tid] = true;
535 thread[tid]->trapPending = true;
536}
537
538template <class Impl>
539void
540DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
541{
542 assert(!trapInFlight[tid]);
543 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
544
545 tcSquash[tid] = true;
546}
547
548template <class Impl>
549void
550DefaultCommit<Impl>::squashAll(ThreadID tid)
551{
552 // If we want to include the squashing instruction in the squash,
553 // then use one older sequence number.
554 // Hopefully this doesn't mess things up. Basically I want to squash
555 // all instructions of this thread.
556 InstSeqNum squashed_inst = rob->isEmpty(tid) ?
557 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
558
559 // All younger instructions will be squashed. Set the sequence
560 // number as the youngest instruction in the ROB (0 in this case.
561 // Hopefully nothing breaks.)
562 youngestSeqNum[tid] = lastCommitedSeqNum[tid];
563
564 rob->squash(squashed_inst, tid);
565 changedROBNumEntries[tid] = true;
566
567 // Send back the sequence number of the squashed instruction.
568 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
569
570 // Send back the squash signal to tell stages that they should
571 // squash.
572 toIEW->commitInfo[tid].squash = true;
573
574 // Send back the rob squashing signal so other stages know that
575 // the ROB is in the process of squashing.
576 toIEW->commitInfo[tid].robSquashing = true;
577
578 toIEW->commitInfo[tid].mispredictInst = NULL;
579 toIEW->commitInfo[tid].squashInst = NULL;
580
581 toIEW->commitInfo[tid].pc = pc[tid];
582}
583
584template <class Impl>
585void
586DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
587{
588 squashAll(tid);
589
590 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
591
592 thread[tid]->trapPending = false;
593 thread[tid]->noSquashFromTC = false;
594 trapInFlight[tid] = false;
595
596 trapSquash[tid] = false;
597
598 commitStatus[tid] = ROBSquashing;
599 cpu->activityThisCycle();
600}
601
602template <class Impl>
603void
604DefaultCommit<Impl>::squashFromTC(ThreadID tid)
605{
606 squashAll(tid);
607
608 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
609
610 thread[tid]->noSquashFromTC = false;
611 assert(!thread[tid]->trapPending);
612
613 commitStatus[tid] = ROBSquashing;
614 cpu->activityThisCycle();
615
616 tcSquash[tid] = false;
617}
618
619template <class Impl>
620void
621DefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid)
622{
623 DPRINTF(Commit, "Squashing after squash after request, "
624 "restarting at PC %s\n", pc[tid]);
625
626 squashAll(tid);
627 // Make sure to inform the fetch stage of which instruction caused
628 // the squash. It'll try to re-fetch an instruction executing in
629 // microcode unless this is set.
630 toIEW->commitInfo[tid].squashInst = squashAfterInst[tid];
631 squashAfterInst[tid] = NULL;
632
633 commitStatus[tid] = ROBSquashing;
634 cpu->activityThisCycle();
635}
636
637template <class Impl>
638void
639DefaultCommit<Impl>::squashAfter(ThreadID tid, const DynInstPtr &head_inst)
640{
641 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
642 tid, head_inst->seqNum);
643
644 assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst);
645 commitStatus[tid] = SquashAfterPending;
646 squashAfterInst[tid] = head_inst;
647}
648
649template <class Impl>
650void
651DefaultCommit<Impl>::tick()
652{
653 wroteToTimeBuffer = false;
654 _nextStatus = Inactive;
655
656 if (activeThreads->empty())
657 return;
658
659 list<ThreadID>::iterator threads = activeThreads->begin();
660 list<ThreadID>::iterator end = activeThreads->end();
661
662 // Check if any of the threads are done squashing. Change the
663 // status if they are done.
664 while (threads != end) {
665 ThreadID tid = *threads++;
666
667 // Clear the bit saying if the thread has committed stores
668 // this cycle.
669 committedStores[tid] = false;
670
671 if (commitStatus[tid] == ROBSquashing) {
672
673 if (rob->isDoneSquashing(tid)) {
674 commitStatus[tid] = Running;
675 } else {
676 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
677 " insts this cycle.\n", tid);
678 rob->doSquash(tid);
679 toIEW->commitInfo[tid].robSquashing = true;
680 wroteToTimeBuffer = true;
681 }
682 }
683 }
684
685 commit();
686
687 markCompletedInsts();
688
689 threads = activeThreads->begin();
690
691 while (threads != end) {
692 ThreadID tid = *threads++;
693
694 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
695 // The ROB has more instructions it can commit. Its next status
696 // will be active.
697 _nextStatus = Active;
698
699 const DynInstPtr &inst M5_VAR_USED = rob->readHeadInst(tid);
700
701 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
702 " ROB and ready to commit\n",
703 tid, inst->seqNum, inst->pcState());
704
705 } else if (!rob->isEmpty(tid)) {
706 const DynInstPtr &inst = rob->readHeadInst(tid);
707
708 ppCommitStall->notify(inst);
709
710 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
711 "%s is head of ROB and not ready\n",
712 tid, inst->seqNum, inst->pcState());
713 }
714
715 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
716 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
717 }
718
719
720 if (wroteToTimeBuffer) {
721 DPRINTF(Activity, "Activity This Cycle.\n");
722 cpu->activityThisCycle();
723 }
724
725 updateStatus();
726}
727
728template <class Impl>
729void
730DefaultCommit<Impl>::handleInterrupt()
731{
732 // Verify that we still have an interrupt to handle
733 if (!cpu->checkInterrupts(cpu->tcBase(0))) {
734 DPRINTF(Commit, "Pending interrupt is cleared by master before "
735 "it got handled. Restart fetching from the orig path.\n");
736 toIEW->commitInfo[0].clearInterrupt = true;
737 interrupt = NoFault;
738 avoidQuiesceLiveLock = true;
739 return;
740 }
741
742 // Wait until all in flight instructions are finished before enterring
743 // the interrupt.
744 if (canHandleInterrupts && cpu->instList.empty()) {
745 // Squash or record that I need to squash this cycle if
746 // an interrupt needed to be handled.
747 DPRINTF(Commit, "Interrupt detected.\n");
748
749 // Clear the interrupt now that it's going to be handled
750 toIEW->commitInfo[0].clearInterrupt = true;
751
752 assert(!thread[0]->noSquashFromTC);
753 thread[0]->noSquashFromTC = true;
754
755 if (cpu->checker) {
756 cpu->checker->handlePendingInt();
757 }
758
759 // CPU will handle interrupt. Note that we ignore the local copy of
760 // interrupt. This is because the local copy may no longer be the
761 // interrupt that the interrupt controller thinks is being handled.
762 cpu->processInterrupts(cpu->getInterrupts());
763
764 thread[0]->noSquashFromTC = false;
765
766 commitStatus[0] = TrapPending;
767
768 interrupt = NoFault;
769
770 // Generate trap squash event.
771 generateTrapEvent(0, interrupt);
772
773 avoidQuiesceLiveLock = false;
774 } else {
775 DPRINTF(Commit, "Interrupt pending: instruction is %sin "
776 "flight, ROB is %sempty\n",
777 canHandleInterrupts ? "not " : "",
778 cpu->instList.empty() ? "" : "not " );
779 }
780}
781
782template <class Impl>
783void
784DefaultCommit<Impl>::propagateInterrupt()
785{
786 // Don't propagate intterupts if we are currently handling a trap or
787 // in draining and the last observable instruction has been committed.
788 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
789 tcSquash[0] || drainImminent)
790 return;
791
792 // Process interrupts if interrupts are enabled, not in PAL
793 // mode, and no other traps or external squashes are currently
794 // pending.
795 // @todo: Allow other threads to handle interrupts.
796
797 // Get any interrupt that happened
798 interrupt = cpu->getInterrupts();
799
800 // Tell fetch that there is an interrupt pending. This
801 // will make fetch wait until it sees a non PAL-mode PC,
802 // at which point it stops fetching instructions.
803 if (interrupt != NoFault)
804 toIEW->commitInfo[0].interruptPending = true;
805}
806
807template <class Impl>
808void
809DefaultCommit<Impl>::commit()
810{
811 if (FullSystem) {
812 // Check if we have a interrupt and get read to handle it
813 if (cpu->checkInterrupts(cpu->tcBase(0)))
814 propagateInterrupt();
815 }
816
817 ////////////////////////////////////
818 // Check for any possible squashes, handle them first
819 ////////////////////////////////////
820 list<ThreadID>::iterator threads = activeThreads->begin();
821 list<ThreadID>::iterator end = activeThreads->end();
822
823 int num_squashing_threads = 0;
824
825 while (threads != end) {
826 ThreadID tid = *threads++;
827
828 // Not sure which one takes priority. I think if we have
829 // both, that's a bad sign.
830 if (trapSquash[tid]) {
831 assert(!tcSquash[tid]);
832 squashFromTrap(tid);
833 } else if (tcSquash[tid]) {
834 assert(commitStatus[tid] != TrapPending);
835 squashFromTC(tid);
836 } else if (commitStatus[tid] == SquashAfterPending) {
837 // A squash from the previous cycle of the commit stage (i.e.,
838 // commitInsts() called squashAfter) is pending. Squash the
839 // thread now.
840 squashFromSquashAfter(tid);
841 }
842
843 // Squashed sequence number must be older than youngest valid
844 // instruction in the ROB. This prevents squashes from younger
845 // instructions overriding squashes from older instructions.
846 if (fromIEW->squash[tid] &&
847 commitStatus[tid] != TrapPending &&
848 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
849
850 if (fromIEW->mispredictInst[tid]) {
851 DPRINTF(Commit,
852 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
853 tid,
854 fromIEW->mispredictInst[tid]->instAddr(),
855 fromIEW->squashedSeqNum[tid]);
856 } else {
857 DPRINTF(Commit,
858 "[tid:%i]: Squashing due to order violation [sn:%i]\n",
859 tid, fromIEW->squashedSeqNum[tid]);
860 }
861
862 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
863 tid,
864 fromIEW->pc[tid].nextInstAddr());
865
866 commitStatus[tid] = ROBSquashing;
867
868 // If we want to include the squashing instruction in the squash,
869 // then use one older sequence number.
870 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
871
872 if (fromIEW->includeSquashInst[tid]) {
873 squashed_inst--;
874 }
875
876 // All younger instructions will be squashed. Set the sequence
877 // number as the youngest instruction in the ROB.
878 youngestSeqNum[tid] = squashed_inst;
879
880 rob->squash(squashed_inst, tid);
881 changedROBNumEntries[tid] = true;
882
883 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
884
885 toIEW->commitInfo[tid].squash = true;
886
887 // Send back the rob squashing signal so other stages know that
888 // the ROB is in the process of squashing.
889 toIEW->commitInfo[tid].robSquashing = true;
890
891 toIEW->commitInfo[tid].mispredictInst =
892 fromIEW->mispredictInst[tid];
893 toIEW->commitInfo[tid].branchTaken =
894 fromIEW->branchTaken[tid];
895 toIEW->commitInfo[tid].squashInst =
896 rob->findInst(tid, squashed_inst);
897 if (toIEW->commitInfo[tid].mispredictInst) {
898 if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) {
899 toIEW->commitInfo[tid].branchTaken = true;
900 }
901 ++branchMispredicts;
902 }
903
904 toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
905 }
906
907 if (commitStatus[tid] == ROBSquashing) {
908 num_squashing_threads++;
909 }
910 }
911
912 // If commit is currently squashing, then it will have activity for the
913 // next cycle. Set its next status as active.
914 if (num_squashing_threads) {
915 _nextStatus = Active;
916 }
917
918 if (num_squashing_threads != numThreads) {
919 // If we're not currently squashing, then get instructions.
920 getInsts();
921
922 // Try to commit any instructions.
923 commitInsts();
924 }
925
926 //Check for any activity
927 threads = activeThreads->begin();
928
929 while (threads != end) {
930 ThreadID tid = *threads++;
931
932 if (changedROBNumEntries[tid]) {
933 toIEW->commitInfo[tid].usedROB = true;
934 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
935
936 wroteToTimeBuffer = true;
937 changedROBNumEntries[tid] = false;
938 if (rob->isEmpty(tid))
939 checkEmptyROB[tid] = true;
940 }
941
942 // ROB is only considered "empty" for previous stages if: a)
943 // ROB is empty, b) there are no outstanding stores, c) IEW
944 // stage has received any information regarding stores that
945 // committed.
946 // c) is checked by making sure to not consider the ROB empty
947 // on the same cycle as when stores have been committed.
948 // @todo: Make this handle multi-cycle communication between
949 // commit and IEW.
950 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
951 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
952 checkEmptyROB[tid] = false;
953 toIEW->commitInfo[tid].usedROB = true;
954 toIEW->commitInfo[tid].emptyROB = true;
955 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
956 wroteToTimeBuffer = true;
957 }
958
959 }
960}
961
962template <class Impl>
963void
964DefaultCommit<Impl>::commitInsts()
965{
966 ////////////////////////////////////
967 // Handle commit
968 // Note that commit will be handled prior to putting new
969 // instructions in the ROB so that the ROB only tries to commit
970 // instructions it has in this current cycle, and not instructions
971 // it is writing in during this cycle. Can't commit and squash
972 // things at the same time...
973 ////////////////////////////////////
974
975 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
976
977 unsigned num_committed = 0;
978
979 DynInstPtr head_inst;
980
981 // Commit as many instructions as possible until the commit bandwidth
982 // limit is reached, or it becomes impossible to commit any more.
983 while (num_committed < commitWidth) {
984 // Check for any interrupt that we've already squashed for
985 // and start processing it.
986 if (interrupt != NoFault)
987 handleInterrupt();
988
989 ThreadID commit_thread = getCommittingThread();
990
991 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
992 break;
993
994 head_inst = rob->readHeadInst(commit_thread);
995
996 ThreadID tid = head_inst->threadNumber;
997
998 assert(tid == commit_thread);
999
1000 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
1001 head_inst->seqNum, tid);
1002
1003 // If the head instruction is squashed, it is ready to retire
1004 // (be removed from the ROB) at any time.
1005 if (head_inst->isSquashed()) {
1006
1007 DPRINTF(Commit, "Retiring squashed instruction from "
1008 "ROB.\n");
1009
1010 rob->retireHead(commit_thread);
1011
1012 ++commitSquashedInsts;
1013 // Notify potential listeners that this instruction is squashed
1014 ppSquash->notify(head_inst);
1015
1016 // Record that the number of ROB entries has changed.
1017 changedROBNumEntries[tid] = true;
1018 } else {
1019 pc[tid] = head_inst->pcState();
1020
1021 // Increment the total number of non-speculative instructions
1022 // executed.
1023 // Hack for now: it really shouldn't happen until after the
1024 // commit is deemed to be successful, but this count is needed
1025 // for syscalls.
1026 thread[tid]->funcExeInst++;
1027
1028 // Try to commit the head instruction.
1029 bool commit_success = commitHead(head_inst, num_committed);
1030
1031 if (commit_success) {
1032 ++num_committed;
1033 statCommittedInstType[tid][head_inst->opClass()]++;
1034 ppCommit->notify(head_inst);
1035
1036 changedROBNumEntries[tid] = true;
1037
1038 // Set the doneSeqNum to the youngest committed instruction.
1039 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
1040
1041 if (tid == 0) {
1042 canHandleInterrupts = (!head_inst->isDelayedCommit()) &&
1043 ((THE_ISA != ALPHA_ISA) ||
1044 (!(pc[0].instAddr() & 0x3)));
1045 }
1046
1047 // at this point store conditionals should either have
1048 // been completed or predicated false
1049 assert(!head_inst->isStoreConditional() ||
1050 head_inst->isCompleted() ||
1051 !head_inst->readPredicate());
1052
1053 // Updates misc. registers.
1054 head_inst->updateMiscRegs();
1055
1056 // Check instruction execution if it successfully commits and
1057 // is not carrying a fault.
1058 if (cpu->checker) {
1059 cpu->checker->verify(head_inst);
1060 }
1061
1062 cpu->traceFunctions(pc[tid].instAddr());
1063
1064 TheISA::advancePC(pc[tid], head_inst->staticInst);
1065
1066 // Keep track of the last sequence number commited
1067 lastCommitedSeqNum[tid] = head_inst->seqNum;
1068
1069 // If this is an instruction that doesn't play nicely with
1070 // others squash everything and restart fetch
1071 if (head_inst->isSquashAfter())
1072 squashAfter(tid, head_inst);
1073
1074 if (drainPending) {
1075 if (pc[tid].microPC() == 0 && interrupt == NoFault &&
1076 !thread[tid]->trapPending) {
1077 // Last architectually committed instruction.
1078 // Squash the pipeline, stall fetch, and use
1079 // drainImminent to disable interrupts
1080 DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]);
1081 squashAfter(tid, head_inst);
1082 cpu->commitDrained(tid);
1083 drainImminent = true;
1084 }
1085 }
1086
1087 bool onInstBoundary = !head_inst->isMicroop() ||
1088 head_inst->isLastMicroop() ||
1089 !head_inst->isDelayedCommit();
1090
1091 if (onInstBoundary) {
1092 int count = 0;
1093 Addr oldpc;
1094 // Make sure we're not currently updating state while
1095 // handling PC events.
1096 assert(!thread[tid]->noSquashFromTC &&
1097 !thread[tid]->trapPending);
1098 do {
1099 oldpc = pc[tid].instAddr();
1100 cpu->system->pcEventQueue.service(thread[tid]->getTC());
1101 count++;
1102 } while (oldpc != pc[tid].instAddr());
1103 if (count > 1) {
1104 DPRINTF(Commit,
1105 "PC skip function event, stopping commit\n");
1106 break;
1107 }
1108 }
1109
1110 // Check if an instruction just enabled interrupts and we've
1111 // previously had an interrupt pending that was not handled
1112 // because interrupts were subsequently disabled before the
1113 // pipeline reached a place to handle the interrupt. In that
1114 // case squash now to make sure the interrupt is handled.
1115 //
1116 // If we don't do this, we might end up in a live lock situation
1117 if (!interrupt && avoidQuiesceLiveLock &&
1118 onInstBoundary && cpu->checkInterrupts(cpu->tcBase(0)))
1119 squashAfter(tid, head_inst);
1120 } else {
1121 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1122 "[tid:%i] [sn:%i].\n",
1123 head_inst->pcState(), tid ,head_inst->seqNum);
1124 break;
1125 }
1126 }
1127 }
1128
1129 DPRINTF(CommitRate, "%i\n", num_committed);
1130 numCommittedDist.sample(num_committed);
1131
1132 if (num_committed == commitWidth) {
1133 commitEligibleSamples++;
1134 }
1135}
1136
1137template <class Impl>
1138bool
1139DefaultCommit<Impl>::commitHead(const DynInstPtr &head_inst, unsigned inst_num)
1140{
1141 assert(head_inst);
1142
1143 ThreadID tid = head_inst->threadNumber;
1144
1145 // If the instruction is not executed yet, then it will need extra
1146 // handling. Signal backwards that it should be executed.
1147 if (!head_inst->isExecuted()) {
1148 // Keep this number correct. We have not yet actually executed
1149 // and committed this instruction.
1150 thread[tid]->funcExeInst--;
1151
1152 // Make sure we are only trying to commit un-executed instructions we
1153 // think are possible.
1154 assert(head_inst->isNonSpeculative() || head_inst->isStoreConditional()
1155 || head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
1156 (head_inst->isLoad() && head_inst->strictlyOrdered()));
1157
1158 DPRINTF(Commit, "Encountered a barrier or non-speculative "
1159 "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1160 head_inst->seqNum, head_inst->pcState());
1161
1162 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1163 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1164 return false;
1165 }
1166
1167 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1168
1169 // Change the instruction so it won't try to commit again until
1170 // it is executed.
1171 head_inst->clearCanCommit();
1172
1173 if (head_inst->isLoad() && head_inst->strictlyOrdered()) {
1174 DPRINTF(Commit, "[sn:%lli]: Strictly ordered load, PC %s.\n",
1175 head_inst->seqNum, head_inst->pcState());
1176 toIEW->commitInfo[tid].strictlyOrdered = true;
1177 toIEW->commitInfo[tid].strictlyOrderedLoad = head_inst;
1178 } else {
1179 ++commitNonSpecStalls;
1180 }
1181
1182 return false;
1183 }
1184
1185 if (head_inst->isThreadSync()) {
1186 // Not handled for now.
1187 panic("Thread sync instructions are not handled yet.\n");
1188 }
1189
1190 // Check if the instruction caused a fault. If so, trap.
1191 Fault inst_fault = head_inst->getFault();
1192
1193 // Stores mark themselves as completed.
1194 if (!head_inst->isStore() && inst_fault == NoFault) {
1195 head_inst->setCompleted();
1196 }
1197
1198 if (inst_fault != NoFault) {
1199 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1200 head_inst->seqNum, head_inst->pcState());
1201
1202 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1203 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1204 return false;
1205 }
1206
1207 head_inst->setCompleted();
1208
1209 // If instruction has faulted, let the checker execute it and
1210 // check if it sees the same fault and control flow.
1211 if (cpu->checker) {
1212 // Need to check the instruction before its fault is processed
1213 cpu->checker->verify(head_inst);
1214 }
1215
1216 assert(!thread[tid]->noSquashFromTC);
1217
1218 // Mark that we're in state update mode so that the trap's
1219 // execution doesn't generate extra squashes.
1220 thread[tid]->noSquashFromTC = true;
1221
1222 // Execute the trap. Although it's slightly unrealistic in
1223 // terms of timing (as it doesn't wait for the full timing of
1224 // the trap event to complete before updating state), it's
1225 // needed to update the state as soon as possible. This
1226 // prevents external agents from changing any specific state
1227 // that the trap need.
1228 cpu->trap(inst_fault, tid,
1229 head_inst->notAnInst() ?
1230 StaticInst::nullStaticInstPtr :
1231 head_inst->staticInst);
1232
1233 // Exit state update mode to avoid accidental updating.
1234 thread[tid]->noSquashFromTC = false;
1235
1236 commitStatus[tid] = TrapPending;
1237
1238 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1239 head_inst->seqNum);
1240 if (head_inst->traceData) {
1241 if (DTRACE(ExecFaulting)) {
1242 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1243 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1244 head_inst->traceData->dump();
1245 }
1246 delete head_inst->traceData;
1247 head_inst->traceData = NULL;
1248 }
1249
1250 // Generate trap squash event.
1251 generateTrapEvent(tid, inst_fault);
1252 return false;
1253 }
1254
1255 updateComInstStats(head_inst);
1256
1257 if (FullSystem) {
1258 if (thread[tid]->profile) {
1259 thread[tid]->profilePC = head_inst->instAddr();
1260 ProfileNode *node = thread[tid]->profile->consume(
1261 thread[tid]->getTC(), head_inst->staticInst);
1262
1263 if (node)
1264 thread[tid]->profileNode = node;
1265 }
1266 if (CPA::available()) {
1267 if (head_inst->isControl()) {
1268 ThreadContext *tc = thread[tid]->getTC();
1269 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1270 }
1271 }
1272 }
1273 DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
1274 head_inst->seqNum, head_inst->pcState());
1275 if (head_inst->traceData) {
1276 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1277 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1278 head_inst->traceData->dump();
1279 delete head_inst->traceData;
1280 head_inst->traceData = NULL;
1281 }
1282 if (head_inst->isReturn()) {
1283 DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n",
1284 head_inst->seqNum, head_inst->pcState());
1285 }
1286
1287 // Update the commit rename map
1288 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1289 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1290 head_inst->renamedDestRegIdx(i));
1291 }
1292
1293 // Finally clear the head ROB entry.
1294 rob->retireHead(tid);
1295
1296#if TRACING_ON
1297 if (DTRACE(O3PipeView)) {
1298 head_inst->commitTick = curTick() - head_inst->fetchTick;
1299 }
1300#endif
1301
1302 // If this was a store, record it for this cycle.
1303 if (head_inst->isStore())
1304 committedStores[tid] = true;
1305
1306 // Return true to indicate that we have committed an instruction.
1307 return true;
1308}
1309
1310template <class Impl>
1311void
1312DefaultCommit<Impl>::getInsts()
1313{
1314 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1315
1316 // Read any renamed instructions and place them into the ROB.
1317 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1318
1319 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1320 const DynInstPtr &inst = fromRename->insts[inst_num];
1321 ThreadID tid = inst->threadNumber;
1322
1323 if (!inst->isSquashed() &&
1324 commitStatus[tid] != ROBSquashing &&
1325 commitStatus[tid] != TrapPending) {
1326 changedROBNumEntries[tid] = true;
1327
1328 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1329 inst->pcState(), inst->seqNum, tid);
1330
1331 rob->insertInst(inst);
1332
1333 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1334
1335 youngestSeqNum[tid] = inst->seqNum;
1336 } else {
1337 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1338 "squashed, skipping.\n",
1339 inst->pcState(), inst->seqNum, tid);
1340 }
1341 }
1342}
1343
1344template <class Impl>
1345void
1346DefaultCommit<Impl>::markCompletedInsts()
1347{
1348 // Grab completed insts out of the IEW instruction queue, and mark
1349 // instructions completed within the ROB.
1350 for (int inst_num = 0; inst_num < fromIEW->size; ++inst_num) {
1351 assert(fromIEW->insts[inst_num]);
1352 if (!fromIEW->insts[inst_num]->isSquashed()) {
1353 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1354 "within ROB.\n",
1355 fromIEW->insts[inst_num]->threadNumber,
1356 fromIEW->insts[inst_num]->pcState(),
1357 fromIEW->insts[inst_num]->seqNum);
1358
1359 // Mark the instruction as ready to commit.
1360 fromIEW->insts[inst_num]->setCanCommit();
1361 }
1362 }
1363}
1364
1365template <class Impl>
1366void
1367DefaultCommit<Impl>::updateComInstStats(const DynInstPtr &inst)
1368{
1369 ThreadID tid = inst->threadNumber;
1370
1371 if (!inst->isMicroop() || inst->isLastMicroop())
1372 instsCommitted[tid]++;
1373 opsCommitted[tid]++;
1374
1375 // To match the old model, don't count nops and instruction
1376 // prefetches towards the total commit count.
1377 if (!inst->isNop() && !inst->isInstPrefetch()) {
1378 cpu->instDone(tid, inst);
1379 }
1380
1381 //
1382 // Control Instructions
1383 //
1384 if (inst->isControl())
1385 statComBranches[tid]++;
1386
1387 //
1388 // Memory references
1389 //
1390 if (inst->isMemRef()) {
1391 statComRefs[tid]++;
1392
1393 if (inst->isLoad()) {
1394 statComLoads[tid]++;
1395 }
1396 }
1397
1398 if (inst->isMemBarrier()) {
1399 statComMembars[tid]++;
1400 }
1401
1402 // Integer Instruction
1403 if (inst->isInteger())
1404 statComInteger[tid]++;
1405
1406 // Floating Point Instruction
1407 if (inst->isFloating())
1408 statComFloating[tid]++;
1409 // Vector Instruction
1410 if (inst->isVector())
1411 statComVector[tid]++;
1412
1413 // Function Calls
1414 if (inst->isCall())
1415 statComFunctionCalls[tid]++;
1416
1417}
1418
1419////////////////////////////////////////
1420// //
1421// SMT COMMIT POLICY MAINTAINED HERE //
1422// //
1423////////////////////////////////////////
1424template <class Impl>
1425ThreadID
1426DefaultCommit<Impl>::getCommittingThread()
1427{
1428 if (numThreads > 1) {
1429 switch (commitPolicy) {
1430
1431 case Aggressive:
1432 //If Policy is Aggressive, commit will call
1433 //this function multiple times per
1434 //cycle
1435 return oldestReady();
1436
1437 case RoundRobin:
1438 return roundRobin();
1439
1440 case OldestReady:
1441 return oldestReady();
1442
1443 default:
1444 return InvalidThreadID;
1445 }
1446 } else {
1447 assert(!activeThreads->empty());
1448 ThreadID tid = activeThreads->front();
1449
1450 if (commitStatus[tid] == Running ||
1451 commitStatus[tid] == Idle ||
1452 commitStatus[tid] == FetchTrapPending) {
1453 return tid;
1454 } else {
1455 return InvalidThreadID;
1456 }
1457 }
1458}
1459
1460template<class Impl>
1461ThreadID
1462DefaultCommit<Impl>::roundRobin()
1463{
1464 list<ThreadID>::iterator pri_iter = priority_list.begin();
1465 list<ThreadID>::iterator end = priority_list.end();
1466
1467 while (pri_iter != end) {
1468 ThreadID tid = *pri_iter;
1469
1470 if (commitStatus[tid] == Running ||
1471 commitStatus[tid] == Idle ||
1472 commitStatus[tid] == FetchTrapPending) {
1473
1474 if (rob->isHeadReady(tid)) {
1475 priority_list.erase(pri_iter);
1476 priority_list.push_back(tid);
1477
1478 return tid;
1479 }
1480 }
1481
1482 pri_iter++;
1483 }
1484
1485 return InvalidThreadID;
1486}
1487
1488template<class Impl>
1489ThreadID
1490DefaultCommit<Impl>::oldestReady()
1491{
1492 unsigned oldest = 0;
1493 bool first = true;
1494
1495 list<ThreadID>::iterator threads = activeThreads->begin();
1496 list<ThreadID>::iterator end = activeThreads->end();
1497
1498 while (threads != end) {
1499 ThreadID tid = *threads++;
1500
1501 if (!rob->isEmpty(tid) &&
1502 (commitStatus[tid] == Running ||
1503 commitStatus[tid] == Idle ||
1504 commitStatus[tid] == FetchTrapPending)) {
1505
1506 if (rob->isHeadReady(tid)) {
1507
1508 const DynInstPtr &head_inst = rob->readHeadInst(tid);
1509
1510 if (first) {
1511 oldest = tid;
1512 first = false;
1513 } else if (head_inst->seqNum < oldest) {
1514 oldest = tid;
1515 }
1516 }
1517 }
1518 }
1519
1520 if (!first) {
1521 return oldest;
1522 } else {
1523 return InvalidThreadID;
1524 }
1525}
1526
1527#endif//__CPU_O3_COMMIT_IMPL_HH__