1/*
2 * Copyright 2014 Google, Inc.
3 * Copyright (c) 2010-2014 ARM Limited
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 */
44#ifndef __CPU_O3_COMMIT_IMPL_HH__
45#define __CPU_O3_COMMIT_IMPL_HH__
46
47#include <algorithm>
48#include <set>
49#include <string>
50
51#include "arch/utility.hh"
52#include "base/loader/symtab.hh"
53#include "base/cp_annotate.hh"
54#include "config/the_isa.hh"
55#include "cpu/checker/cpu.hh"
56#include "cpu/o3/commit.hh"
57#include "cpu/o3/thread_state.hh"
58#include "cpu/base.hh"
59#include "cpu/exetrace.hh"
60#include "cpu/timebuf.hh"
61#include "debug/Activity.hh"
62#include "debug/Commit.hh"
63#include "debug/CommitRate.hh"
64#include "debug/Drain.hh"
65#include "debug/ExecFaulting.hh"
66#include "debug/O3PipeView.hh"
67#include "params/DerivO3CPU.hh"
68#include "sim/faults.hh"
69#include "sim/full_system.hh"
70
71using namespace std;
72
73template <class Impl>
74DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
75 ThreadID _tid)
76 : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid)
77{
78}
79
80template <class Impl>
81void
82DefaultCommit<Impl>::TrapEvent::process()
83{
84 // This will get reset by commit if it was switched out at the
85 // time of this event processing.
86 commit->trapSquash[tid] = true;
87}
88
89template <class Impl>
90const char *
91DefaultCommit<Impl>::TrapEvent::description() const
92{
93 return "Trap";
94}
95
96template <class Impl>
97DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
98 : cpu(_cpu),
99 iewToCommitDelay(params->iewToCommitDelay),
100 commitToIEWDelay(params->commitToIEWDelay),
101 renameToROBDelay(params->renameToROBDelay),
102 fetchToCommitDelay(params->commitToFetchDelay),
103 renameWidth(params->renameWidth),
104 commitWidth(params->commitWidth),
105 numThreads(params->numThreads),
106 drainPending(false),
107 drainImminent(false),
108 trapLatency(params->trapLatency),
109 canHandleInterrupts(true),
110 avoidQuiesceLiveLock(false)
111{
112 if (commitWidth > Impl::MaxWidth)
113 fatal("commitWidth (%d) is larger than compiled limit (%d),\n"
114 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
115 commitWidth, static_cast<int>(Impl::MaxWidth));
116
117 _status = Active;
118 _nextStatus = Inactive;
119 std::string policy = params->smtCommitPolicy;
120
121 //Convert string to lowercase
122 std::transform(policy.begin(), policy.end(), policy.begin(),
123 (int(*)(int)) tolower);
124
125 //Assign commit policy
126 if (policy == "aggressive"){
127 commitPolicy = Aggressive;
128
129 DPRINTF(Commit,"Commit Policy set to Aggressive.\n");
130 } else if (policy == "roundrobin"){
131 commitPolicy = RoundRobin;
132
133 //Set-Up Priority List
134 for (ThreadID tid = 0; tid < numThreads; tid++) {
135 priority_list.push_back(tid);
136 }
137
138 DPRINTF(Commit,"Commit Policy set to Round Robin.\n");
139 } else if (policy == "oldestready"){
140 commitPolicy = OldestReady;
141
142 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
143 } else {
144 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
145 "RoundRobin,OldestReady}");
146 }
147
148 for (ThreadID tid = 0; tid < numThreads; tid++) {
149 commitStatus[tid] = Idle;
150 changedROBNumEntries[tid] = false;
151 checkEmptyROB[tid] = false;
152 trapInFlight[tid] = false;
153 committedStores[tid] = false;
154 trapSquash[tid] = false;
155 tcSquash[tid] = false;
156 pc[tid].set(0);
157 lastCommitedSeqNum[tid] = 0;
158 squashAfterInst[tid] = NULL;
159 }
160 interrupt = NoFault;
161}
162
163template <class Impl>
164std::string
165DefaultCommit<Impl>::name() const
166{
167 return cpu->name() + ".commit";
168}
169
170template <class Impl>
171void
172DefaultCommit<Impl>::regProbePoints()
173{
174 ppCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Commit");
175 ppCommitStall = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "CommitStall");
176 ppSquash = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Squash");
177}
178
179template <class Impl>
180void
181DefaultCommit<Impl>::regStats()
182{
183 using namespace Stats;
184 commitSquashedInsts
185 .name(name() + ".commitSquashedInsts")
186 .desc("The number of squashed insts skipped by commit")
187 .prereq(commitSquashedInsts);
188
189 commitNonSpecStalls
190 .name(name() + ".commitNonSpecStalls")
191 .desc("The number of times commit has been forced to stall to "
192 "communicate backwards")
193 .prereq(commitNonSpecStalls);
194
195 branchMispredicts
196 .name(name() + ".branchMispredicts")
197 .desc("The number of times a branch was mispredicted")
198 .prereq(branchMispredicts);
199
200 numCommittedDist
201 .init(0,commitWidth,1)
202 .name(name() + ".committed_per_cycle")
203 .desc("Number of insts commited each cycle")
204 .flags(Stats::pdf)
205 ;
206
207 instsCommitted
208 .init(cpu->numThreads)
209 .name(name() + ".committedInsts")
210 .desc("Number of instructions committed")
211 .flags(total)
212 ;
213
214 opsCommitted
215 .init(cpu->numThreads)
216 .name(name() + ".committedOps")
217 .desc("Number of ops (including micro ops) committed")
218 .flags(total)
219 ;
220
221 statComSwp
222 .init(cpu->numThreads)
223 .name(name() + ".swp_count")
224 .desc("Number of s/w prefetches committed")
225 .flags(total)
226 ;
227
228 statComRefs
229 .init(cpu->numThreads)
230 .name(name() + ".refs")
231 .desc("Number of memory references committed")
232 .flags(total)
233 ;
234
235 statComLoads
236 .init(cpu->numThreads)
237 .name(name() + ".loads")
238 .desc("Number of loads committed")
239 .flags(total)
240 ;
241
242 statComMembars
243 .init(cpu->numThreads)
244 .name(name() + ".membars")
245 .desc("Number of memory barriers committed")
246 .flags(total)
247 ;
248
249 statComBranches
250 .init(cpu->numThreads)
251 .name(name() + ".branches")
252 .desc("Number of branches committed")
253 .flags(total)
254 ;
255
256 statComFloating
257 .init(cpu->numThreads)
258 .name(name() + ".fp_insts")
259 .desc("Number of committed floating point instructions.")
260 .flags(total)
261 ;
262
263 statComVector
264 .init(cpu->numThreads)
265 .name(name() + ".vec_insts")
266 .desc("Number of committed Vector instructions.")
267 .flags(total)
268 ;
269
270 statComInteger
271 .init(cpu->numThreads)
272 .name(name()+".int_insts")
273 .desc("Number of committed integer instructions.")
274 .flags(total)
275 ;
276
277 statComFunctionCalls
278 .init(cpu->numThreads)
279 .name(name()+".function_calls")
280 .desc("Number of function calls committed.")
281 .flags(total)
282 ;
283
284 statCommittedInstType
285 .init(numThreads,Enums::Num_OpClass)
286 .name(name() + ".op_class")
287 .desc("Class of committed instruction")
288 .flags(total | pdf | dist)
289 ;
290 statCommittedInstType.ysubnames(Enums::OpClassStrings);
291
292 commitEligibleSamples
293 .name(name() + ".bw_lim_events")
294 .desc("number cycles where commit BW limit reached")
295 ;
296}
297
298template <class Impl>
299void
300DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
301{
302 thread = threads;
303}
304
305template <class Impl>
306void
307DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
308{
309 timeBuffer = tb_ptr;
310
311 // Setup wire to send information back to IEW.
312 toIEW = timeBuffer->getWire(0);
313
314 // Setup wire to read data from IEW (for the ROB).
315 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
316}
317
318template <class Impl>
319void
320DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
321{
322 fetchQueue = fq_ptr;
323
324 // Setup wire to get instructions from rename (for the ROB).
325 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
326}
327
328template <class Impl>
329void
330DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
331{
332 renameQueue = rq_ptr;
333
334 // Setup wire to get instructions from rename (for the ROB).
335 fromRename = renameQueue->getWire(-renameToROBDelay);
336}
337
338template <class Impl>
339void
340DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
341{
342 iewQueue = iq_ptr;
343
344 // Setup wire to get instructions from IEW.
345 fromIEW = iewQueue->getWire(-iewToCommitDelay);
346}
347
348template <class Impl>
349void
350DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
351{
352 iewStage = iew_stage;
353}
354
355template<class Impl>
356void
357DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
358{
359 activeThreads = at_ptr;
360}
361
362template <class Impl>
363void
364DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
365{
366 for (ThreadID tid = 0; tid < numThreads; tid++)
367 renameMap[tid] = &rm_ptr[tid];
368}
369
370template <class Impl>
371void
372DefaultCommit<Impl>::setROB(ROB *rob_ptr)
373{
374 rob = rob_ptr;
375}
376
377template <class Impl>
378void
379DefaultCommit<Impl>::startupStage()
380{
381 rob->setActiveThreads(activeThreads);
382 rob->resetEntries();
383
384 // Broadcast the number of free entries.
385 for (ThreadID tid = 0; tid < numThreads; tid++) {
386 toIEW->commitInfo[tid].usedROB = true;
387 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
388 toIEW->commitInfo[tid].emptyROB = true;
389 }
390
391 // Commit must broadcast the number of free entries it has at the
392 // start of the simulation, so it starts as active.
393 cpu->activateStage(O3CPU::CommitIdx);
394
395 cpu->activityThisCycle();
396}
397
398template <class Impl>
399void
400DefaultCommit<Impl>::drain()
401{
402 drainPending = true;
403}
404
405template <class Impl>
406void
407DefaultCommit<Impl>::drainResume()
408{
409 drainPending = false;
410 drainImminent = false;
411}
412
413template <class Impl>
414void
415DefaultCommit<Impl>::drainSanityCheck() const
416{
417 assert(isDrained());
418 rob->drainSanityCheck();
419}
420
421template <class Impl>
422bool
423DefaultCommit<Impl>::isDrained() const
424{
425 /* Make sure no one is executing microcode. There are two reasons
426 * for this:
427 * - Hardware virtualized CPUs can't switch into the middle of a
428 * microcode sequence.
429 * - The current fetch implementation will most likely get very
430 * confused if it tries to start fetching an instruction that
431 * is executing in the middle of a ucode sequence that changes
432 * address mappings. This can happen on for example x86.
433 */
434 for (ThreadID tid = 0; tid < numThreads; tid++) {
435 if (pc[tid].microPC() != 0)
436 return false;
437 }
438
439 /* Make sure that all instructions have finished committing before
440 * declaring the system as drained. We want the pipeline to be
441 * completely empty when we declare the CPU to be drained. This
442 * makes debugging easier since CPU handover and restoring from a
443 * checkpoint with a different CPU should have the same timing.
444 */
445 return rob->isEmpty() &&
446 interrupt == NoFault;
447}
448
449template <class Impl>
450void
451DefaultCommit<Impl>::takeOverFrom()
452{
453 _status = Active;
454 _nextStatus = Inactive;
455 for (ThreadID tid = 0; tid < numThreads; tid++) {
456 commitStatus[tid] = Idle;
457 changedROBNumEntries[tid] = false;
458 trapSquash[tid] = false;
459 tcSquash[tid] = false;
460 squashAfterInst[tid] = NULL;
461 }
462 rob->takeOverFrom();
463}
464
465template <class Impl>
466void
467DefaultCommit<Impl>::deactivateThread(ThreadID tid)
468{
469 list<ThreadID>::iterator thread_it = std::find(priority_list.begin(),
470 priority_list.end(), tid);
471
472 if (thread_it != priority_list.end()) {
473 priority_list.erase(thread_it);
474 }
475}
476
477
478template <class Impl>
479void
480DefaultCommit<Impl>::updateStatus()
481{
482 // reset ROB changed variable
483 list<ThreadID>::iterator threads = activeThreads->begin();
484 list<ThreadID>::iterator end = activeThreads->end();
485
486 while (threads != end) {
487 ThreadID tid = *threads++;
488
489 changedROBNumEntries[tid] = false;
490
491 // Also check if any of the threads has a trap pending
492 if (commitStatus[tid] == TrapPending ||
493 commitStatus[tid] == FetchTrapPending) {
494 _nextStatus = Active;
495 }
496 }
497
498 if (_nextStatus == Inactive && _status == Active) {
499 DPRINTF(Activity, "Deactivating stage.\n");
500 cpu->deactivateStage(O3CPU::CommitIdx);
501 } else if (_nextStatus == Active && _status == Inactive) {
502 DPRINTF(Activity, "Activating stage.\n");
503 cpu->activateStage(O3CPU::CommitIdx);
504 }
505
506 _status = _nextStatus;
507}
508
509template <class Impl>
510bool
511DefaultCommit<Impl>::changedROBEntries()
512{
513 list<ThreadID>::iterator threads = activeThreads->begin();
514 list<ThreadID>::iterator end = activeThreads->end();
515
516 while (threads != end) {
517 ThreadID tid = *threads++;
518
519 if (changedROBNumEntries[tid]) {
520 return true;
521 }
522 }
523
524 return false;
525}
526
527template <class Impl>
528size_t
529DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
530{
531 return rob->numFreeEntries(tid);
532}
533
534template <class Impl>
535void
536DefaultCommit<Impl>::generateTrapEvent(ThreadID tid, Fault inst_fault)
537{
538 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
539
540 TrapEvent *trap = new TrapEvent(this, tid);
541
542 Cycles latency = dynamic_pointer_cast<SyscallRetryFault>(inst_fault) ?
543 cpu->syscallRetryLatency : trapLatency;
544
545 cpu->schedule(trap, cpu->clockEdge(latency));
546 trapInFlight[tid] = true;
547 thread[tid]->trapPending = true;
548}
549
550template <class Impl>
551void
552DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
553{
554 assert(!trapInFlight[tid]);
555 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
556
557 tcSquash[tid] = true;
558}
559
560template <class Impl>
561void
562DefaultCommit<Impl>::squashAll(ThreadID tid)
563{
564 // If we want to include the squashing instruction in the squash,
565 // then use one older sequence number.
566 // Hopefully this doesn't mess things up. Basically I want to squash
567 // all instructions of this thread.
568 InstSeqNum squashed_inst = rob->isEmpty(tid) ?
569 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
570
571 // All younger instructions will be squashed. Set the sequence
572 // number as the youngest instruction in the ROB (0 in this case.
573 // Hopefully nothing breaks.)
574 youngestSeqNum[tid] = lastCommitedSeqNum[tid];
575
576 rob->squash(squashed_inst, tid);
577 changedROBNumEntries[tid] = true;
578
579 // Send back the sequence number of the squashed instruction.
580 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
581
582 // Send back the squash signal to tell stages that they should
583 // squash.
584 toIEW->commitInfo[tid].squash = true;
585
586 // Send back the rob squashing signal so other stages know that
587 // the ROB is in the process of squashing.
588 toIEW->commitInfo[tid].robSquashing = true;
589
590 toIEW->commitInfo[tid].mispredictInst = NULL;
591 toIEW->commitInfo[tid].squashInst = NULL;
592
593 toIEW->commitInfo[tid].pc = pc[tid];
594}
595
596template <class Impl>
597void
598DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
599{
600 squashAll(tid);
601
602 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
603
604 thread[tid]->trapPending = false;
605 thread[tid]->noSquashFromTC = false;
606 trapInFlight[tid] = false;
607
608 trapSquash[tid] = false;
609
610 commitStatus[tid] = ROBSquashing;
611 cpu->activityThisCycle();
612}
613
614template <class Impl>
615void
616DefaultCommit<Impl>::squashFromTC(ThreadID tid)
617{
618 squashAll(tid);
619
620 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
621
622 thread[tid]->noSquashFromTC = false;
623 assert(!thread[tid]->trapPending);
624
625 commitStatus[tid] = ROBSquashing;
626 cpu->activityThisCycle();
627
628 tcSquash[tid] = false;
629}
630
631template <class Impl>
632void
633DefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid)
634{
635 DPRINTF(Commit, "Squashing after squash after request, "
636 "restarting at PC %s\n", pc[tid]);
637
638 squashAll(tid);
639 // Make sure to inform the fetch stage of which instruction caused
640 // the squash. It'll try to re-fetch an instruction executing in
641 // microcode unless this is set.
642 toIEW->commitInfo[tid].squashInst = squashAfterInst[tid];
643 squashAfterInst[tid] = NULL;
644
645 commitStatus[tid] = ROBSquashing;
646 cpu->activityThisCycle();
647}
648
649template <class Impl>
650void
651DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst)
652{
653 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
654 tid, head_inst->seqNum);
655
656 assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst);
657 commitStatus[tid] = SquashAfterPending;
658 squashAfterInst[tid] = head_inst;
659}
660
661template <class Impl>
662void
663DefaultCommit<Impl>::tick()
664{
665 wroteToTimeBuffer = false;
666 _nextStatus = Inactive;
667
668 if (activeThreads->empty())
669 return;
670
671 list<ThreadID>::iterator threads = activeThreads->begin();
672 list<ThreadID>::iterator end = activeThreads->end();
673
674 // Check if any of the threads are done squashing. Change the
675 // status if they are done.
676 while (threads != end) {
677 ThreadID tid = *threads++;
678
679 // Clear the bit saying if the thread has committed stores
680 // this cycle.
681 committedStores[tid] = false;
682
683 if (commitStatus[tid] == ROBSquashing) {
684
685 if (rob->isDoneSquashing(tid)) {
686 commitStatus[tid] = Running;
687 } else {
688 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
689 " insts this cycle.\n", tid);
690 rob->doSquash(tid);
691 toIEW->commitInfo[tid].robSquashing = true;
692 wroteToTimeBuffer = true;
693 }
694 }
695 }
696
697 commit();
698
699 markCompletedInsts();
700
701 threads = activeThreads->begin();
702
703 while (threads != end) {
704 ThreadID tid = *threads++;
705
706 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
707 // The ROB has more instructions it can commit. Its next status
708 // will be active.
709 _nextStatus = Active;
710
711 DynInstPtr inst = rob->readHeadInst(tid);
712
713 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
714 " ROB and ready to commit\n",
715 tid, inst->seqNum, inst->pcState());
716
717 } else if (!rob->isEmpty(tid)) {
718 DynInstPtr inst = rob->readHeadInst(tid);
719
720 ppCommitStall->notify(inst);
721
722 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
723 "%s is head of ROB and not ready\n",
724 tid, inst->seqNum, inst->pcState());
725 }
726
727 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
728 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
729 }
730
731
732 if (wroteToTimeBuffer) {
733 DPRINTF(Activity, "Activity This Cycle.\n");
734 cpu->activityThisCycle();
735 }
736
737 updateStatus();
738}
739
740template <class Impl>
741void
742DefaultCommit<Impl>::handleInterrupt()
743{
744 // Verify that we still have an interrupt to handle
745 if (!cpu->checkInterrupts(cpu->tcBase(0))) {
746 DPRINTF(Commit, "Pending interrupt is cleared by master before "
747 "it got handled. Restart fetching from the orig path.\n");
748 toIEW->commitInfo[0].clearInterrupt = true;
749 interrupt = NoFault;
750 avoidQuiesceLiveLock = true;
751 return;
752 }
753
754 // Wait until all in flight instructions are finished before enterring
755 // the interrupt.
756 if (canHandleInterrupts && cpu->instList.empty()) {
757 // Squash or record that I need to squash this cycle if
758 // an interrupt needed to be handled.
759 DPRINTF(Commit, "Interrupt detected.\n");
760
761 // Clear the interrupt now that it's going to be handled
762 toIEW->commitInfo[0].clearInterrupt = true;
763
764 assert(!thread[0]->noSquashFromTC);
765 thread[0]->noSquashFromTC = true;
766
767 if (cpu->checker) {
768 cpu->checker->handlePendingInt();
769 }
770
771 // CPU will handle interrupt. Note that we ignore the local copy of
772 // interrupt. This is because the local copy may no longer be the
773 // interrupt that the interrupt controller thinks is being handled.
774 cpu->processInterrupts(cpu->getInterrupts());
775
776 thread[0]->noSquashFromTC = false;
777
778 commitStatus[0] = TrapPending;
779
780 interrupt = NoFault;
781
782 // Generate trap squash event.
783 generateTrapEvent(0, interrupt);
784
785 avoidQuiesceLiveLock = false;
786 } else {
787 DPRINTF(Commit, "Interrupt pending: instruction is %sin "
788 "flight, ROB is %sempty\n",
789 canHandleInterrupts ? "not " : "",
790 cpu->instList.empty() ? "" : "not " );
791 }
792}
793
794template <class Impl>
795void
796DefaultCommit<Impl>::propagateInterrupt()
797{
798 // Don't propagate intterupts if we are currently handling a trap or
799 // in draining and the last observable instruction has been committed.
800 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
801 tcSquash[0] || drainImminent)
802 return;
803
804 // Process interrupts if interrupts are enabled, not in PAL
805 // mode, and no other traps or external squashes are currently
806 // pending.
807 // @todo: Allow other threads to handle interrupts.
808
809 // Get any interrupt that happened
810 interrupt = cpu->getInterrupts();
811
812 // Tell fetch that there is an interrupt pending. This
813 // will make fetch wait until it sees a non PAL-mode PC,
814 // at which point it stops fetching instructions.
815 if (interrupt != NoFault)
816 toIEW->commitInfo[0].interruptPending = true;
817}
818
819template <class Impl>
820void
821DefaultCommit<Impl>::commit()
822{
823 if (FullSystem) {
824 // Check if we have a interrupt and get read to handle it
825 if (cpu->checkInterrupts(cpu->tcBase(0)))
826 propagateInterrupt();
827 }
828
829 ////////////////////////////////////
830 // Check for any possible squashes, handle them first
831 ////////////////////////////////////
832 list<ThreadID>::iterator threads = activeThreads->begin();
833 list<ThreadID>::iterator end = activeThreads->end();
834
835 int num_squashing_threads = 0;
836
837 while (threads != end) {
838 ThreadID tid = *threads++;
839
840 // Not sure which one takes priority. I think if we have
841 // both, that's a bad sign.
842 if (trapSquash[tid]) {
843 assert(!tcSquash[tid]);
844 squashFromTrap(tid);
845 } else if (tcSquash[tid]) {
846 assert(commitStatus[tid] != TrapPending);
847 squashFromTC(tid);
848 } else if (commitStatus[tid] == SquashAfterPending) {
849 // A squash from the previous cycle of the commit stage (i.e.,
850 // commitInsts() called squashAfter) is pending. Squash the
851 // thread now.
852 squashFromSquashAfter(tid);
853 }
854
855 // Squashed sequence number must be older than youngest valid
856 // instruction in the ROB. This prevents squashes from younger
857 // instructions overriding squashes from older instructions.
858 if (fromIEW->squash[tid] &&
859 commitStatus[tid] != TrapPending &&
860 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
861
862 if (fromIEW->mispredictInst[tid]) {
863 DPRINTF(Commit,
864 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
865 tid,
866 fromIEW->mispredictInst[tid]->instAddr(),
867 fromIEW->squashedSeqNum[tid]);
868 } else {
869 DPRINTF(Commit,
870 "[tid:%i]: Squashing due to order violation [sn:%i]\n",
871 tid, fromIEW->squashedSeqNum[tid]);
872 }
873
874 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
875 tid,
876 fromIEW->pc[tid].nextInstAddr());
877
878 commitStatus[tid] = ROBSquashing;
879
880 // If we want to include the squashing instruction in the squash,
881 // then use one older sequence number.
882 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
883
884 if (fromIEW->includeSquashInst[tid]) {
885 squashed_inst--;
886 }
887
888 // All younger instructions will be squashed. Set the sequence
889 // number as the youngest instruction in the ROB.
890 youngestSeqNum[tid] = squashed_inst;
891
892 rob->squash(squashed_inst, tid);
893 changedROBNumEntries[tid] = true;
894
895 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
896
897 toIEW->commitInfo[tid].squash = true;
898
899 // Send back the rob squashing signal so other stages know that
900 // the ROB is in the process of squashing.
901 toIEW->commitInfo[tid].robSquashing = true;
902
903 toIEW->commitInfo[tid].mispredictInst =
904 fromIEW->mispredictInst[tid];
905 toIEW->commitInfo[tid].branchTaken =
906 fromIEW->branchTaken[tid];
907 toIEW->commitInfo[tid].squashInst =
908 rob->findInst(tid, squashed_inst);
909 if (toIEW->commitInfo[tid].mispredictInst) {
910 if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) {
911 toIEW->commitInfo[tid].branchTaken = true;
912 }
913 ++branchMispredicts;
914 }
915
916 toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
917 }
918
919 if (commitStatus[tid] == ROBSquashing) {
920 num_squashing_threads++;
921 }
922 }
923
924 // If commit is currently squashing, then it will have activity for the
925 // next cycle. Set its next status as active.
926 if (num_squashing_threads) {
927 _nextStatus = Active;
928 }
929
930 if (num_squashing_threads != numThreads) {
931 // If we're not currently squashing, then get instructions.
932 getInsts();
933
934 // Try to commit any instructions.
935 commitInsts();
936 }
937
938 //Check for any activity
939 threads = activeThreads->begin();
940
941 while (threads != end) {
942 ThreadID tid = *threads++;
943
944 if (changedROBNumEntries[tid]) {
945 toIEW->commitInfo[tid].usedROB = true;
946 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
947
948 wroteToTimeBuffer = true;
949 changedROBNumEntries[tid] = false;
950 if (rob->isEmpty(tid))
951 checkEmptyROB[tid] = true;
952 }
953
954 // ROB is only considered "empty" for previous stages if: a)
955 // ROB is empty, b) there are no outstanding stores, c) IEW
956 // stage has received any information regarding stores that
957 // committed.
958 // c) is checked by making sure to not consider the ROB empty
959 // on the same cycle as when stores have been committed.
960 // @todo: Make this handle multi-cycle communication between
961 // commit and IEW.
962 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
963 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
964 checkEmptyROB[tid] = false;
965 toIEW->commitInfo[tid].usedROB = true;
966 toIEW->commitInfo[tid].emptyROB = true;
967 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
968 wroteToTimeBuffer = true;
969 }
970
971 }
972}
973
974template <class Impl>
975void
976DefaultCommit<Impl>::commitInsts()
977{
978 ////////////////////////////////////
979 // Handle commit
980 // Note that commit will be handled prior to putting new
981 // instructions in the ROB so that the ROB only tries to commit
982 // instructions it has in this current cycle, and not instructions
983 // it is writing in during this cycle. Can't commit and squash
984 // things at the same time...
985 ////////////////////////////////////
986
987 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
988
989 unsigned num_committed = 0;
990
991 DynInstPtr head_inst;
992
993 // Commit as many instructions as possible until the commit bandwidth
994 // limit is reached, or it becomes impossible to commit any more.
995 while (num_committed < commitWidth) {
996 // Check for any interrupt that we've already squashed for
997 // and start processing it.
998 if (interrupt != NoFault)
999 handleInterrupt();
1000
1001 ThreadID commit_thread = getCommittingThread();
1002
1003 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
1004 break;
1005
1006 head_inst = rob->readHeadInst(commit_thread);
1007
1008 ThreadID tid = head_inst->threadNumber;
1009
1010 assert(tid == commit_thread);
1011
1012 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
1013 head_inst->seqNum, tid);
1014
1015 // If the head instruction is squashed, it is ready to retire
1016 // (be removed from the ROB) at any time.
1017 if (head_inst->isSquashed()) {
1018
1019 DPRINTF(Commit, "Retiring squashed instruction from "
1020 "ROB.\n");
1021
1022 rob->retireHead(commit_thread);
1023
1024 ++commitSquashedInsts;
1025 // Notify potential listeners that this instruction is squashed
1026 ppSquash->notify(head_inst);
1027
1028 // Record that the number of ROB entries has changed.
1029 changedROBNumEntries[tid] = true;
1030 } else {
1031 pc[tid] = head_inst->pcState();
1032
1033 // Increment the total number of non-speculative instructions
1034 // executed.
1035 // Hack for now: it really shouldn't happen until after the
1036 // commit is deemed to be successful, but this count is needed
1037 // for syscalls.
1038 thread[tid]->funcExeInst++;
1039
1040 // Try to commit the head instruction.
1041 bool commit_success = commitHead(head_inst, num_committed);
1042
1043 if (commit_success) {
1044 ++num_committed;
1045 statCommittedInstType[tid][head_inst->opClass()]++;
1046 ppCommit->notify(head_inst);
1047
1048 changedROBNumEntries[tid] = true;
1049
1050 // Set the doneSeqNum to the youngest committed instruction.
1051 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
1052
1053 if (tid == 0) {
1054 canHandleInterrupts = (!head_inst->isDelayedCommit()) &&
1055 ((THE_ISA != ALPHA_ISA) ||
1056 (!(pc[0].instAddr() & 0x3)));
1057 }
1058
1059 // Updates misc. registers.
1060 head_inst->updateMiscRegs();
1061
1062 // Check instruction execution if it successfully commits and
1063 // is not carrying a fault.
1064 if (cpu->checker) {
1065 cpu->checker->verify(head_inst);
1066 }
1067
1068 cpu->traceFunctions(pc[tid].instAddr());
1069
1070 TheISA::advancePC(pc[tid], head_inst->staticInst);
1071
1072 // Keep track of the last sequence number commited
1073 lastCommitedSeqNum[tid] = head_inst->seqNum;
1074
1075 // If this is an instruction that doesn't play nicely with
1076 // others squash everything and restart fetch
1077 if (head_inst->isSquashAfter())
1078 squashAfter(tid, head_inst);
1079
1080 if (drainPending) {
1081 if (pc[tid].microPC() == 0 && interrupt == NoFault &&
1082 !thread[tid]->trapPending) {
1083 // Last architectually committed instruction.
1084 // Squash the pipeline, stall fetch, and use
1085 // drainImminent to disable interrupts
1086 DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]);
1087 squashAfter(tid, head_inst);
1088 cpu->commitDrained(tid);
1089 drainImminent = true;
1090 }
1091 }
1092
1093 bool onInstBoundary = !head_inst->isMicroop() ||
1094 head_inst->isLastMicroop() ||
1095 !head_inst->isDelayedCommit();
1096
1097 if (onInstBoundary) {
1098 int count = 0;
1099 Addr oldpc;
1100 // Make sure we're not currently updating state while
1101 // handling PC events.
1102 assert(!thread[tid]->noSquashFromTC &&
1103 !thread[tid]->trapPending);
1104 do {
1105 oldpc = pc[tid].instAddr();
1106 cpu->system->pcEventQueue.service(thread[tid]->getTC());
1107 count++;
1108 } while (oldpc != pc[tid].instAddr());
1109 if (count > 1) {
1110 DPRINTF(Commit,
1111 "PC skip function event, stopping commit\n");
1112 break;
1113 }
1114 }
1115
1116 // Check if an instruction just enabled interrupts and we've
1117 // previously had an interrupt pending that was not handled
1118 // because interrupts were subsequently disabled before the
1119 // pipeline reached a place to handle the interrupt. In that
1120 // case squash now to make sure the interrupt is handled.
1121 //
1122 // If we don't do this, we might end up in a live lock situation
1123 if (!interrupt && avoidQuiesceLiveLock &&
1124 onInstBoundary && cpu->checkInterrupts(cpu->tcBase(0)))
1125 squashAfter(tid, head_inst);
1126 } else {
1127 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1128 "[tid:%i] [sn:%i].\n",
1129 head_inst->pcState(), tid ,head_inst->seqNum);
1130 break;
1131 }
1132 }
1133 }
1134
1135 DPRINTF(CommitRate, "%i\n", num_committed);
1136 numCommittedDist.sample(num_committed);
1137
1138 if (num_committed == commitWidth) {
1139 commitEligibleSamples++;
1140 }
1141}
1142
1143template <class Impl>
1144bool
1145DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1146{
1147 assert(head_inst);
1148
1149 ThreadID tid = head_inst->threadNumber;
1150
1151 // If the instruction is not executed yet, then it will need extra
1152 // handling. Signal backwards that it should be executed.
1153 if (!head_inst->isExecuted()) {
1154 // Keep this number correct. We have not yet actually executed
1155 // and committed this instruction.
1156 thread[tid]->funcExeInst--;
1157
1158 // Make sure we are only trying to commit un-executed instructions we
1159 // think are possible.
1160 assert(head_inst->isNonSpeculative() || head_inst->isStoreConditional()
1161 || head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
1162 (head_inst->isLoad() && head_inst->strictlyOrdered()));
1163
1164 DPRINTF(Commit, "Encountered a barrier or non-speculative "
1165 "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1166 head_inst->seqNum, head_inst->pcState());
1167
1168 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1169 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1170 return false;
1171 }
1172
1173 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1174
1175 // Change the instruction so it won't try to commit again until
1176 // it is executed.
1177 head_inst->clearCanCommit();
1178
1179 if (head_inst->isLoad() && head_inst->strictlyOrdered()) {
1180 DPRINTF(Commit, "[sn:%lli]: Strictly ordered load, PC %s.\n",
1181 head_inst->seqNum, head_inst->pcState());
1182 toIEW->commitInfo[tid].strictlyOrdered = true;
1183 toIEW->commitInfo[tid].strictlyOrderedLoad = head_inst;
1184 } else {
1185 ++commitNonSpecStalls;
1186 }
1187
1188 return false;
1189 }
1190
1191 if (head_inst->isThreadSync()) {
1192 // Not handled for now.
1193 panic("Thread sync instructions are not handled yet.\n");
1194 }
1195
1196 // Check if the instruction caused a fault. If so, trap.
1197 Fault inst_fault = head_inst->getFault();
1198
1199 // Stores mark themselves as completed.
1200 if (!head_inst->isStore() && inst_fault == NoFault) {
1201 head_inst->setCompleted();
1202 }
1203
1204 if (inst_fault != NoFault) {
1205 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1206 head_inst->seqNum, head_inst->pcState());
1207
1208 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1209 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1210 return false;
1211 }
1212
1213 head_inst->setCompleted();
1214
1215 // If instruction has faulted, let the checker execute it and
1216 // check if it sees the same fault and control flow.
1217 if (cpu->checker) {
1218 // Need to check the instruction before its fault is processed
1219 cpu->checker->verify(head_inst);
1220 }
1221
1222 assert(!thread[tid]->noSquashFromTC);
1223
1224 // Mark that we're in state update mode so that the trap's
1225 // execution doesn't generate extra squashes.
1226 thread[tid]->noSquashFromTC = true;
1227
1228 // Execute the trap. Although it's slightly unrealistic in
1229 // terms of timing (as it doesn't wait for the full timing of
1230 // the trap event to complete before updating state), it's
1231 // needed to update the state as soon as possible. This
1232 // prevents external agents from changing any specific state
1233 // that the trap need.
1234 cpu->trap(inst_fault, tid, head_inst->staticInst);
1235
1236 // Exit state update mode to avoid accidental updating.
1237 thread[tid]->noSquashFromTC = false;
1238
1239 commitStatus[tid] = TrapPending;
1240
1241 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1242 head_inst->seqNum);
1243 if (head_inst->traceData) {
1244 if (DTRACE(ExecFaulting)) {
1245 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1246 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1247 head_inst->traceData->dump();
1248 }
1249 delete head_inst->traceData;
1250 head_inst->traceData = NULL;
1251 }
1252
1253 // Generate trap squash event.
1254 generateTrapEvent(tid, inst_fault);
1255 return false;
1256 }
1257
1258 updateComInstStats(head_inst);
1259
1260 if (FullSystem) {
1261 if (thread[tid]->profile) {
1262 thread[tid]->profilePC = head_inst->instAddr();
1263 ProfileNode *node = thread[tid]->profile->consume(
1264 thread[tid]->getTC(), head_inst->staticInst);
1265
1266 if (node)
1267 thread[tid]->profileNode = node;
1268 }
1269 if (CPA::available()) {
1270 if (head_inst->isControl()) {
1271 ThreadContext *tc = thread[tid]->getTC();
1272 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1273 }
1274 }
1275 }
1276 DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
1277 head_inst->seqNum, head_inst->pcState());
1278 if (head_inst->traceData) {
1279 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1280 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1281 head_inst->traceData->dump();
1282 delete head_inst->traceData;
1283 head_inst->traceData = NULL;
1284 }
1285 if (head_inst->isReturn()) {
1286 DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n",
1287 head_inst->seqNum, head_inst->pcState());
1288 }
1289
1290 // Update the commit rename map
1291 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1292 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1293 head_inst->renamedDestRegIdx(i));
1294 }
1295
1296 // Finally clear the head ROB entry.
1297 rob->retireHead(tid);
1298
1299#if TRACING_ON
1300 if (DTRACE(O3PipeView)) {
1301 head_inst->commitTick = curTick() - head_inst->fetchTick;
1302 }
1303#endif
1304
1305 // If this was a store, record it for this cycle.
1306 if (head_inst->isStore())
1307 committedStores[tid] = true;
1308
1309 // Return true to indicate that we have committed an instruction.
1310 return true;
1311}
1312
1313template <class Impl>
1314void
1315DefaultCommit<Impl>::getInsts()
1316{
1317 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1318
1319 // Read any renamed instructions and place them into the ROB.
1320 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1321
1322 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1323 DynInstPtr inst;
1324
1325 inst = fromRename->insts[inst_num];
1326 ThreadID tid = inst->threadNumber;
1327
1328 if (!inst->isSquashed() &&
1329 commitStatus[tid] != ROBSquashing &&
1330 commitStatus[tid] != TrapPending) {
1331 changedROBNumEntries[tid] = true;
1332
1333 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1334 inst->pcState(), inst->seqNum, tid);
1335
1336 rob->insertInst(inst);
1337
1338 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1339
1340 youngestSeqNum[tid] = inst->seqNum;
1341 } else {
1342 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1343 "squashed, skipping.\n",
1344 inst->pcState(), inst->seqNum, tid);
1345 }
1346 }
1347}
1348
1349template <class Impl>
1350void
1351DefaultCommit<Impl>::markCompletedInsts()
1352{
1353 // Grab completed insts out of the IEW instruction queue, and mark
1354 // instructions completed within the ROB.
1355 for (int inst_num = 0; inst_num < fromIEW->size; ++inst_num) {
1356 assert(fromIEW->insts[inst_num]);
1357 if (!fromIEW->insts[inst_num]->isSquashed()) {
1358 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1359 "within ROB.\n",
1360 fromIEW->insts[inst_num]->threadNumber,
1361 fromIEW->insts[inst_num]->pcState(),
1362 fromIEW->insts[inst_num]->seqNum);
1363
1364 // Mark the instruction as ready to commit.
1365 fromIEW->insts[inst_num]->setCanCommit();
1366 }
1367 }
1368}
1369
1370template <class Impl>
1371void
1372DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1373{
1374 ThreadID tid = inst->threadNumber;
1375
1376 if (!inst->isMicroop() || inst->isLastMicroop())
1377 instsCommitted[tid]++;
1378 opsCommitted[tid]++;
1379
1380 // To match the old model, don't count nops and instruction
1381 // prefetches towards the total commit count.
1382 if (!inst->isNop() && !inst->isInstPrefetch()) {
1383 cpu->instDone(tid, inst);
1384 }
1385
1386 //
1387 // Control Instructions
1388 //
1389 if (inst->isControl())
1390 statComBranches[tid]++;
1391
1392 //
1393 // Memory references
1394 //
1395 if (inst->isMemRef()) {
1396 statComRefs[tid]++;
1397
1398 if (inst->isLoad()) {
1399 statComLoads[tid]++;
1400 }
1401 }
1402
1403 if (inst->isMemBarrier()) {
1404 statComMembars[tid]++;
1405 }
1406
1407 // Integer Instruction
1408 if (inst->isInteger())
1409 statComInteger[tid]++;
1410
1411 // Floating Point Instruction
1412 if (inst->isFloating())
1413 statComFloating[tid]++;
1414 // Vector Instruction
1415 if (inst->isVector())
1416 statComVector[tid]++;
1417
1418 // Function Calls
1419 if (inst->isCall())
1420 statComFunctionCalls[tid]++;
1421
1422}
1423
1424////////////////////////////////////////
1425// //
1426// SMT COMMIT POLICY MAINTAINED HERE //
1427// //
1428////////////////////////////////////////
1429template <class Impl>
1430ThreadID
1431DefaultCommit<Impl>::getCommittingThread()
1432{
1433 if (numThreads > 1) {
1434 switch (commitPolicy) {
1435
1436 case Aggressive:
1437 //If Policy is Aggressive, commit will call
1438 //this function multiple times per
1439 //cycle
1440 return oldestReady();
1441
1442 case RoundRobin:
1443 return roundRobin();
1444
1445 case OldestReady:
1446 return oldestReady();
1447
1448 default:
1449 return InvalidThreadID;
1450 }
1451 } else {
1452 assert(!activeThreads->empty());
1453 ThreadID tid = activeThreads->front();
1454
1455 if (commitStatus[tid] == Running ||
1456 commitStatus[tid] == Idle ||
1457 commitStatus[tid] == FetchTrapPending) {
1458 return tid;
1459 } else {
1460 return InvalidThreadID;
1461 }
1462 }
1463}
1464
1465template<class Impl>
1466ThreadID
1467DefaultCommit<Impl>::roundRobin()
1468{
1469 list<ThreadID>::iterator pri_iter = priority_list.begin();
1470 list<ThreadID>::iterator end = priority_list.end();
1471
1472 while (pri_iter != end) {
1473 ThreadID tid = *pri_iter;
1474
1475 if (commitStatus[tid] == Running ||
1476 commitStatus[tid] == Idle ||
1477 commitStatus[tid] == FetchTrapPending) {
1478
1479 if (rob->isHeadReady(tid)) {
1480 priority_list.erase(pri_iter);
1481 priority_list.push_back(tid);
1482
1483 return tid;
1484 }
1485 }
1486
1487 pri_iter++;
1488 }
1489
1490 return InvalidThreadID;
1491}
1492
1493template<class Impl>
1494ThreadID
1495DefaultCommit<Impl>::oldestReady()
1496{
1497 unsigned oldest = 0;
1498 bool first = true;
1499
1500 list<ThreadID>::iterator threads = activeThreads->begin();
1501 list<ThreadID>::iterator end = activeThreads->end();
1502
1503 while (threads != end) {
1504 ThreadID tid = *threads++;
1505
1506 if (!rob->isEmpty(tid) &&
1507 (commitStatus[tid] == Running ||
1508 commitStatus[tid] == Idle ||
1509 commitStatus[tid] == FetchTrapPending)) {
1510
1511 if (rob->isHeadReady(tid)) {
1512
1513 DynInstPtr head_inst = rob->readHeadInst(tid);
1514
1515 if (first) {
1516 oldest = tid;
1517 first = false;
1518 } else if (head_inst->seqNum < oldest) {
1519 oldest = tid;
1520 }
1521 }
1522 }
1523 }
1524
1525 if (!first) {
1526 return oldest;
1527 } else {
1528 return InvalidThreadID;
1529 }
1530}
1531
1532#endif//__CPU_O3_COMMIT_IMPL_HH__
2 * Copyright 2014 Google, Inc.
3 * Copyright (c) 2010-2014 ARM Limited
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 * Korey Sewell
43 */
44#ifndef __CPU_O3_COMMIT_IMPL_HH__
45#define __CPU_O3_COMMIT_IMPL_HH__
46
47#include <algorithm>
48#include <set>
49#include <string>
50
51#include "arch/utility.hh"
52#include "base/loader/symtab.hh"
53#include "base/cp_annotate.hh"
54#include "config/the_isa.hh"
55#include "cpu/checker/cpu.hh"
56#include "cpu/o3/commit.hh"
57#include "cpu/o3/thread_state.hh"
58#include "cpu/base.hh"
59#include "cpu/exetrace.hh"
60#include "cpu/timebuf.hh"
61#include "debug/Activity.hh"
62#include "debug/Commit.hh"
63#include "debug/CommitRate.hh"
64#include "debug/Drain.hh"
65#include "debug/ExecFaulting.hh"
66#include "debug/O3PipeView.hh"
67#include "params/DerivO3CPU.hh"
68#include "sim/faults.hh"
69#include "sim/full_system.hh"
70
71using namespace std;
72
73template <class Impl>
74DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
75 ThreadID _tid)
76 : Event(CPU_Tick_Pri, AutoDelete), commit(_commit), tid(_tid)
77{
78}
79
80template <class Impl>
81void
82DefaultCommit<Impl>::TrapEvent::process()
83{
84 // This will get reset by commit if it was switched out at the
85 // time of this event processing.
86 commit->trapSquash[tid] = true;
87}
88
89template <class Impl>
90const char *
91DefaultCommit<Impl>::TrapEvent::description() const
92{
93 return "Trap";
94}
95
96template <class Impl>
97DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
98 : cpu(_cpu),
99 iewToCommitDelay(params->iewToCommitDelay),
100 commitToIEWDelay(params->commitToIEWDelay),
101 renameToROBDelay(params->renameToROBDelay),
102 fetchToCommitDelay(params->commitToFetchDelay),
103 renameWidth(params->renameWidth),
104 commitWidth(params->commitWidth),
105 numThreads(params->numThreads),
106 drainPending(false),
107 drainImminent(false),
108 trapLatency(params->trapLatency),
109 canHandleInterrupts(true),
110 avoidQuiesceLiveLock(false)
111{
112 if (commitWidth > Impl::MaxWidth)
113 fatal("commitWidth (%d) is larger than compiled limit (%d),\n"
114 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
115 commitWidth, static_cast<int>(Impl::MaxWidth));
116
117 _status = Active;
118 _nextStatus = Inactive;
119 std::string policy = params->smtCommitPolicy;
120
121 //Convert string to lowercase
122 std::transform(policy.begin(), policy.end(), policy.begin(),
123 (int(*)(int)) tolower);
124
125 //Assign commit policy
126 if (policy == "aggressive"){
127 commitPolicy = Aggressive;
128
129 DPRINTF(Commit,"Commit Policy set to Aggressive.\n");
130 } else if (policy == "roundrobin"){
131 commitPolicy = RoundRobin;
132
133 //Set-Up Priority List
134 for (ThreadID tid = 0; tid < numThreads; tid++) {
135 priority_list.push_back(tid);
136 }
137
138 DPRINTF(Commit,"Commit Policy set to Round Robin.\n");
139 } else if (policy == "oldestready"){
140 commitPolicy = OldestReady;
141
142 DPRINTF(Commit,"Commit Policy set to Oldest Ready.");
143 } else {
144 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
145 "RoundRobin,OldestReady}");
146 }
147
148 for (ThreadID tid = 0; tid < numThreads; tid++) {
149 commitStatus[tid] = Idle;
150 changedROBNumEntries[tid] = false;
151 checkEmptyROB[tid] = false;
152 trapInFlight[tid] = false;
153 committedStores[tid] = false;
154 trapSquash[tid] = false;
155 tcSquash[tid] = false;
156 pc[tid].set(0);
157 lastCommitedSeqNum[tid] = 0;
158 squashAfterInst[tid] = NULL;
159 }
160 interrupt = NoFault;
161}
162
163template <class Impl>
164std::string
165DefaultCommit<Impl>::name() const
166{
167 return cpu->name() + ".commit";
168}
169
170template <class Impl>
171void
172DefaultCommit<Impl>::regProbePoints()
173{
174 ppCommit = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Commit");
175 ppCommitStall = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "CommitStall");
176 ppSquash = new ProbePointArg<DynInstPtr>(cpu->getProbeManager(), "Squash");
177}
178
179template <class Impl>
180void
181DefaultCommit<Impl>::regStats()
182{
183 using namespace Stats;
184 commitSquashedInsts
185 .name(name() + ".commitSquashedInsts")
186 .desc("The number of squashed insts skipped by commit")
187 .prereq(commitSquashedInsts);
188
189 commitNonSpecStalls
190 .name(name() + ".commitNonSpecStalls")
191 .desc("The number of times commit has been forced to stall to "
192 "communicate backwards")
193 .prereq(commitNonSpecStalls);
194
195 branchMispredicts
196 .name(name() + ".branchMispredicts")
197 .desc("The number of times a branch was mispredicted")
198 .prereq(branchMispredicts);
199
200 numCommittedDist
201 .init(0,commitWidth,1)
202 .name(name() + ".committed_per_cycle")
203 .desc("Number of insts commited each cycle")
204 .flags(Stats::pdf)
205 ;
206
207 instsCommitted
208 .init(cpu->numThreads)
209 .name(name() + ".committedInsts")
210 .desc("Number of instructions committed")
211 .flags(total)
212 ;
213
214 opsCommitted
215 .init(cpu->numThreads)
216 .name(name() + ".committedOps")
217 .desc("Number of ops (including micro ops) committed")
218 .flags(total)
219 ;
220
221 statComSwp
222 .init(cpu->numThreads)
223 .name(name() + ".swp_count")
224 .desc("Number of s/w prefetches committed")
225 .flags(total)
226 ;
227
228 statComRefs
229 .init(cpu->numThreads)
230 .name(name() + ".refs")
231 .desc("Number of memory references committed")
232 .flags(total)
233 ;
234
235 statComLoads
236 .init(cpu->numThreads)
237 .name(name() + ".loads")
238 .desc("Number of loads committed")
239 .flags(total)
240 ;
241
242 statComMembars
243 .init(cpu->numThreads)
244 .name(name() + ".membars")
245 .desc("Number of memory barriers committed")
246 .flags(total)
247 ;
248
249 statComBranches
250 .init(cpu->numThreads)
251 .name(name() + ".branches")
252 .desc("Number of branches committed")
253 .flags(total)
254 ;
255
256 statComFloating
257 .init(cpu->numThreads)
258 .name(name() + ".fp_insts")
259 .desc("Number of committed floating point instructions.")
260 .flags(total)
261 ;
262
263 statComVector
264 .init(cpu->numThreads)
265 .name(name() + ".vec_insts")
266 .desc("Number of committed Vector instructions.")
267 .flags(total)
268 ;
269
270 statComInteger
271 .init(cpu->numThreads)
272 .name(name()+".int_insts")
273 .desc("Number of committed integer instructions.")
274 .flags(total)
275 ;
276
277 statComFunctionCalls
278 .init(cpu->numThreads)
279 .name(name()+".function_calls")
280 .desc("Number of function calls committed.")
281 .flags(total)
282 ;
283
284 statCommittedInstType
285 .init(numThreads,Enums::Num_OpClass)
286 .name(name() + ".op_class")
287 .desc("Class of committed instruction")
288 .flags(total | pdf | dist)
289 ;
290 statCommittedInstType.ysubnames(Enums::OpClassStrings);
291
292 commitEligibleSamples
293 .name(name() + ".bw_lim_events")
294 .desc("number cycles where commit BW limit reached")
295 ;
296}
297
298template <class Impl>
299void
300DefaultCommit<Impl>::setThreads(std::vector<Thread *> &threads)
301{
302 thread = threads;
303}
304
305template <class Impl>
306void
307DefaultCommit<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
308{
309 timeBuffer = tb_ptr;
310
311 // Setup wire to send information back to IEW.
312 toIEW = timeBuffer->getWire(0);
313
314 // Setup wire to read data from IEW (for the ROB).
315 robInfoFromIEW = timeBuffer->getWire(-iewToCommitDelay);
316}
317
318template <class Impl>
319void
320DefaultCommit<Impl>::setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr)
321{
322 fetchQueue = fq_ptr;
323
324 // Setup wire to get instructions from rename (for the ROB).
325 fromFetch = fetchQueue->getWire(-fetchToCommitDelay);
326}
327
328template <class Impl>
329void
330DefaultCommit<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
331{
332 renameQueue = rq_ptr;
333
334 // Setup wire to get instructions from rename (for the ROB).
335 fromRename = renameQueue->getWire(-renameToROBDelay);
336}
337
338template <class Impl>
339void
340DefaultCommit<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
341{
342 iewQueue = iq_ptr;
343
344 // Setup wire to get instructions from IEW.
345 fromIEW = iewQueue->getWire(-iewToCommitDelay);
346}
347
348template <class Impl>
349void
350DefaultCommit<Impl>::setIEWStage(IEW *iew_stage)
351{
352 iewStage = iew_stage;
353}
354
355template<class Impl>
356void
357DefaultCommit<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
358{
359 activeThreads = at_ptr;
360}
361
362template <class Impl>
363void
364DefaultCommit<Impl>::setRenameMap(RenameMap rm_ptr[])
365{
366 for (ThreadID tid = 0; tid < numThreads; tid++)
367 renameMap[tid] = &rm_ptr[tid];
368}
369
370template <class Impl>
371void
372DefaultCommit<Impl>::setROB(ROB *rob_ptr)
373{
374 rob = rob_ptr;
375}
376
377template <class Impl>
378void
379DefaultCommit<Impl>::startupStage()
380{
381 rob->setActiveThreads(activeThreads);
382 rob->resetEntries();
383
384 // Broadcast the number of free entries.
385 for (ThreadID tid = 0; tid < numThreads; tid++) {
386 toIEW->commitInfo[tid].usedROB = true;
387 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
388 toIEW->commitInfo[tid].emptyROB = true;
389 }
390
391 // Commit must broadcast the number of free entries it has at the
392 // start of the simulation, so it starts as active.
393 cpu->activateStage(O3CPU::CommitIdx);
394
395 cpu->activityThisCycle();
396}
397
398template <class Impl>
399void
400DefaultCommit<Impl>::drain()
401{
402 drainPending = true;
403}
404
405template <class Impl>
406void
407DefaultCommit<Impl>::drainResume()
408{
409 drainPending = false;
410 drainImminent = false;
411}
412
413template <class Impl>
414void
415DefaultCommit<Impl>::drainSanityCheck() const
416{
417 assert(isDrained());
418 rob->drainSanityCheck();
419}
420
421template <class Impl>
422bool
423DefaultCommit<Impl>::isDrained() const
424{
425 /* Make sure no one is executing microcode. There are two reasons
426 * for this:
427 * - Hardware virtualized CPUs can't switch into the middle of a
428 * microcode sequence.
429 * - The current fetch implementation will most likely get very
430 * confused if it tries to start fetching an instruction that
431 * is executing in the middle of a ucode sequence that changes
432 * address mappings. This can happen on for example x86.
433 */
434 for (ThreadID tid = 0; tid < numThreads; tid++) {
435 if (pc[tid].microPC() != 0)
436 return false;
437 }
438
439 /* Make sure that all instructions have finished committing before
440 * declaring the system as drained. We want the pipeline to be
441 * completely empty when we declare the CPU to be drained. This
442 * makes debugging easier since CPU handover and restoring from a
443 * checkpoint with a different CPU should have the same timing.
444 */
445 return rob->isEmpty() &&
446 interrupt == NoFault;
447}
448
449template <class Impl>
450void
451DefaultCommit<Impl>::takeOverFrom()
452{
453 _status = Active;
454 _nextStatus = Inactive;
455 for (ThreadID tid = 0; tid < numThreads; tid++) {
456 commitStatus[tid] = Idle;
457 changedROBNumEntries[tid] = false;
458 trapSquash[tid] = false;
459 tcSquash[tid] = false;
460 squashAfterInst[tid] = NULL;
461 }
462 rob->takeOverFrom();
463}
464
465template <class Impl>
466void
467DefaultCommit<Impl>::deactivateThread(ThreadID tid)
468{
469 list<ThreadID>::iterator thread_it = std::find(priority_list.begin(),
470 priority_list.end(), tid);
471
472 if (thread_it != priority_list.end()) {
473 priority_list.erase(thread_it);
474 }
475}
476
477
478template <class Impl>
479void
480DefaultCommit<Impl>::updateStatus()
481{
482 // reset ROB changed variable
483 list<ThreadID>::iterator threads = activeThreads->begin();
484 list<ThreadID>::iterator end = activeThreads->end();
485
486 while (threads != end) {
487 ThreadID tid = *threads++;
488
489 changedROBNumEntries[tid] = false;
490
491 // Also check if any of the threads has a trap pending
492 if (commitStatus[tid] == TrapPending ||
493 commitStatus[tid] == FetchTrapPending) {
494 _nextStatus = Active;
495 }
496 }
497
498 if (_nextStatus == Inactive && _status == Active) {
499 DPRINTF(Activity, "Deactivating stage.\n");
500 cpu->deactivateStage(O3CPU::CommitIdx);
501 } else if (_nextStatus == Active && _status == Inactive) {
502 DPRINTF(Activity, "Activating stage.\n");
503 cpu->activateStage(O3CPU::CommitIdx);
504 }
505
506 _status = _nextStatus;
507}
508
509template <class Impl>
510bool
511DefaultCommit<Impl>::changedROBEntries()
512{
513 list<ThreadID>::iterator threads = activeThreads->begin();
514 list<ThreadID>::iterator end = activeThreads->end();
515
516 while (threads != end) {
517 ThreadID tid = *threads++;
518
519 if (changedROBNumEntries[tid]) {
520 return true;
521 }
522 }
523
524 return false;
525}
526
527template <class Impl>
528size_t
529DefaultCommit<Impl>::numROBFreeEntries(ThreadID tid)
530{
531 return rob->numFreeEntries(tid);
532}
533
534template <class Impl>
535void
536DefaultCommit<Impl>::generateTrapEvent(ThreadID tid, Fault inst_fault)
537{
538 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
539
540 TrapEvent *trap = new TrapEvent(this, tid);
541
542 Cycles latency = dynamic_pointer_cast<SyscallRetryFault>(inst_fault) ?
543 cpu->syscallRetryLatency : trapLatency;
544
545 cpu->schedule(trap, cpu->clockEdge(latency));
546 trapInFlight[tid] = true;
547 thread[tid]->trapPending = true;
548}
549
550template <class Impl>
551void
552DefaultCommit<Impl>::generateTCEvent(ThreadID tid)
553{
554 assert(!trapInFlight[tid]);
555 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
556
557 tcSquash[tid] = true;
558}
559
560template <class Impl>
561void
562DefaultCommit<Impl>::squashAll(ThreadID tid)
563{
564 // If we want to include the squashing instruction in the squash,
565 // then use one older sequence number.
566 // Hopefully this doesn't mess things up. Basically I want to squash
567 // all instructions of this thread.
568 InstSeqNum squashed_inst = rob->isEmpty(tid) ?
569 lastCommitedSeqNum[tid] : rob->readHeadInst(tid)->seqNum - 1;
570
571 // All younger instructions will be squashed. Set the sequence
572 // number as the youngest instruction in the ROB (0 in this case.
573 // Hopefully nothing breaks.)
574 youngestSeqNum[tid] = lastCommitedSeqNum[tid];
575
576 rob->squash(squashed_inst, tid);
577 changedROBNumEntries[tid] = true;
578
579 // Send back the sequence number of the squashed instruction.
580 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
581
582 // Send back the squash signal to tell stages that they should
583 // squash.
584 toIEW->commitInfo[tid].squash = true;
585
586 // Send back the rob squashing signal so other stages know that
587 // the ROB is in the process of squashing.
588 toIEW->commitInfo[tid].robSquashing = true;
589
590 toIEW->commitInfo[tid].mispredictInst = NULL;
591 toIEW->commitInfo[tid].squashInst = NULL;
592
593 toIEW->commitInfo[tid].pc = pc[tid];
594}
595
596template <class Impl>
597void
598DefaultCommit<Impl>::squashFromTrap(ThreadID tid)
599{
600 squashAll(tid);
601
602 DPRINTF(Commit, "Squashing from trap, restarting at PC %s\n", pc[tid]);
603
604 thread[tid]->trapPending = false;
605 thread[tid]->noSquashFromTC = false;
606 trapInFlight[tid] = false;
607
608 trapSquash[tid] = false;
609
610 commitStatus[tid] = ROBSquashing;
611 cpu->activityThisCycle();
612}
613
614template <class Impl>
615void
616DefaultCommit<Impl>::squashFromTC(ThreadID tid)
617{
618 squashAll(tid);
619
620 DPRINTF(Commit, "Squashing from TC, restarting at PC %s\n", pc[tid]);
621
622 thread[tid]->noSquashFromTC = false;
623 assert(!thread[tid]->trapPending);
624
625 commitStatus[tid] = ROBSquashing;
626 cpu->activityThisCycle();
627
628 tcSquash[tid] = false;
629}
630
631template <class Impl>
632void
633DefaultCommit<Impl>::squashFromSquashAfter(ThreadID tid)
634{
635 DPRINTF(Commit, "Squashing after squash after request, "
636 "restarting at PC %s\n", pc[tid]);
637
638 squashAll(tid);
639 // Make sure to inform the fetch stage of which instruction caused
640 // the squash. It'll try to re-fetch an instruction executing in
641 // microcode unless this is set.
642 toIEW->commitInfo[tid].squashInst = squashAfterInst[tid];
643 squashAfterInst[tid] = NULL;
644
645 commitStatus[tid] = ROBSquashing;
646 cpu->activityThisCycle();
647}
648
649template <class Impl>
650void
651DefaultCommit<Impl>::squashAfter(ThreadID tid, DynInstPtr &head_inst)
652{
653 DPRINTF(Commit, "Executing squash after for [tid:%i] inst [sn:%lli]\n",
654 tid, head_inst->seqNum);
655
656 assert(!squashAfterInst[tid] || squashAfterInst[tid] == head_inst);
657 commitStatus[tid] = SquashAfterPending;
658 squashAfterInst[tid] = head_inst;
659}
660
661template <class Impl>
662void
663DefaultCommit<Impl>::tick()
664{
665 wroteToTimeBuffer = false;
666 _nextStatus = Inactive;
667
668 if (activeThreads->empty())
669 return;
670
671 list<ThreadID>::iterator threads = activeThreads->begin();
672 list<ThreadID>::iterator end = activeThreads->end();
673
674 // Check if any of the threads are done squashing. Change the
675 // status if they are done.
676 while (threads != end) {
677 ThreadID tid = *threads++;
678
679 // Clear the bit saying if the thread has committed stores
680 // this cycle.
681 committedStores[tid] = false;
682
683 if (commitStatus[tid] == ROBSquashing) {
684
685 if (rob->isDoneSquashing(tid)) {
686 commitStatus[tid] = Running;
687 } else {
688 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
689 " insts this cycle.\n", tid);
690 rob->doSquash(tid);
691 toIEW->commitInfo[tid].robSquashing = true;
692 wroteToTimeBuffer = true;
693 }
694 }
695 }
696
697 commit();
698
699 markCompletedInsts();
700
701 threads = activeThreads->begin();
702
703 while (threads != end) {
704 ThreadID tid = *threads++;
705
706 if (!rob->isEmpty(tid) && rob->readHeadInst(tid)->readyToCommit()) {
707 // The ROB has more instructions it can commit. Its next status
708 // will be active.
709 _nextStatus = Active;
710
711 DynInstPtr inst = rob->readHeadInst(tid);
712
713 DPRINTF(Commit,"[tid:%i]: Instruction [sn:%lli] PC %s is head of"
714 " ROB and ready to commit\n",
715 tid, inst->seqNum, inst->pcState());
716
717 } else if (!rob->isEmpty(tid)) {
718 DynInstPtr inst = rob->readHeadInst(tid);
719
720 ppCommitStall->notify(inst);
721
722 DPRINTF(Commit,"[tid:%i]: Can't commit, Instruction [sn:%lli] PC "
723 "%s is head of ROB and not ready\n",
724 tid, inst->seqNum, inst->pcState());
725 }
726
727 DPRINTF(Commit, "[tid:%i]: ROB has %d insts & %d free entries.\n",
728 tid, rob->countInsts(tid), rob->numFreeEntries(tid));
729 }
730
731
732 if (wroteToTimeBuffer) {
733 DPRINTF(Activity, "Activity This Cycle.\n");
734 cpu->activityThisCycle();
735 }
736
737 updateStatus();
738}
739
740template <class Impl>
741void
742DefaultCommit<Impl>::handleInterrupt()
743{
744 // Verify that we still have an interrupt to handle
745 if (!cpu->checkInterrupts(cpu->tcBase(0))) {
746 DPRINTF(Commit, "Pending interrupt is cleared by master before "
747 "it got handled. Restart fetching from the orig path.\n");
748 toIEW->commitInfo[0].clearInterrupt = true;
749 interrupt = NoFault;
750 avoidQuiesceLiveLock = true;
751 return;
752 }
753
754 // Wait until all in flight instructions are finished before enterring
755 // the interrupt.
756 if (canHandleInterrupts && cpu->instList.empty()) {
757 // Squash or record that I need to squash this cycle if
758 // an interrupt needed to be handled.
759 DPRINTF(Commit, "Interrupt detected.\n");
760
761 // Clear the interrupt now that it's going to be handled
762 toIEW->commitInfo[0].clearInterrupt = true;
763
764 assert(!thread[0]->noSquashFromTC);
765 thread[0]->noSquashFromTC = true;
766
767 if (cpu->checker) {
768 cpu->checker->handlePendingInt();
769 }
770
771 // CPU will handle interrupt. Note that we ignore the local copy of
772 // interrupt. This is because the local copy may no longer be the
773 // interrupt that the interrupt controller thinks is being handled.
774 cpu->processInterrupts(cpu->getInterrupts());
775
776 thread[0]->noSquashFromTC = false;
777
778 commitStatus[0] = TrapPending;
779
780 interrupt = NoFault;
781
782 // Generate trap squash event.
783 generateTrapEvent(0, interrupt);
784
785 avoidQuiesceLiveLock = false;
786 } else {
787 DPRINTF(Commit, "Interrupt pending: instruction is %sin "
788 "flight, ROB is %sempty\n",
789 canHandleInterrupts ? "not " : "",
790 cpu->instList.empty() ? "" : "not " );
791 }
792}
793
794template <class Impl>
795void
796DefaultCommit<Impl>::propagateInterrupt()
797{
798 // Don't propagate intterupts if we are currently handling a trap or
799 // in draining and the last observable instruction has been committed.
800 if (commitStatus[0] == TrapPending || interrupt || trapSquash[0] ||
801 tcSquash[0] || drainImminent)
802 return;
803
804 // Process interrupts if interrupts are enabled, not in PAL
805 // mode, and no other traps or external squashes are currently
806 // pending.
807 // @todo: Allow other threads to handle interrupts.
808
809 // Get any interrupt that happened
810 interrupt = cpu->getInterrupts();
811
812 // Tell fetch that there is an interrupt pending. This
813 // will make fetch wait until it sees a non PAL-mode PC,
814 // at which point it stops fetching instructions.
815 if (interrupt != NoFault)
816 toIEW->commitInfo[0].interruptPending = true;
817}
818
819template <class Impl>
820void
821DefaultCommit<Impl>::commit()
822{
823 if (FullSystem) {
824 // Check if we have a interrupt and get read to handle it
825 if (cpu->checkInterrupts(cpu->tcBase(0)))
826 propagateInterrupt();
827 }
828
829 ////////////////////////////////////
830 // Check for any possible squashes, handle them first
831 ////////////////////////////////////
832 list<ThreadID>::iterator threads = activeThreads->begin();
833 list<ThreadID>::iterator end = activeThreads->end();
834
835 int num_squashing_threads = 0;
836
837 while (threads != end) {
838 ThreadID tid = *threads++;
839
840 // Not sure which one takes priority. I think if we have
841 // both, that's a bad sign.
842 if (trapSquash[tid]) {
843 assert(!tcSquash[tid]);
844 squashFromTrap(tid);
845 } else if (tcSquash[tid]) {
846 assert(commitStatus[tid] != TrapPending);
847 squashFromTC(tid);
848 } else if (commitStatus[tid] == SquashAfterPending) {
849 // A squash from the previous cycle of the commit stage (i.e.,
850 // commitInsts() called squashAfter) is pending. Squash the
851 // thread now.
852 squashFromSquashAfter(tid);
853 }
854
855 // Squashed sequence number must be older than youngest valid
856 // instruction in the ROB. This prevents squashes from younger
857 // instructions overriding squashes from older instructions.
858 if (fromIEW->squash[tid] &&
859 commitStatus[tid] != TrapPending &&
860 fromIEW->squashedSeqNum[tid] <= youngestSeqNum[tid]) {
861
862 if (fromIEW->mispredictInst[tid]) {
863 DPRINTF(Commit,
864 "[tid:%i]: Squashing due to branch mispred PC:%#x [sn:%i]\n",
865 tid,
866 fromIEW->mispredictInst[tid]->instAddr(),
867 fromIEW->squashedSeqNum[tid]);
868 } else {
869 DPRINTF(Commit,
870 "[tid:%i]: Squashing due to order violation [sn:%i]\n",
871 tid, fromIEW->squashedSeqNum[tid]);
872 }
873
874 DPRINTF(Commit, "[tid:%i]: Redirecting to PC %#x\n",
875 tid,
876 fromIEW->pc[tid].nextInstAddr());
877
878 commitStatus[tid] = ROBSquashing;
879
880 // If we want to include the squashing instruction in the squash,
881 // then use one older sequence number.
882 InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid];
883
884 if (fromIEW->includeSquashInst[tid]) {
885 squashed_inst--;
886 }
887
888 // All younger instructions will be squashed. Set the sequence
889 // number as the youngest instruction in the ROB.
890 youngestSeqNum[tid] = squashed_inst;
891
892 rob->squash(squashed_inst, tid);
893 changedROBNumEntries[tid] = true;
894
895 toIEW->commitInfo[tid].doneSeqNum = squashed_inst;
896
897 toIEW->commitInfo[tid].squash = true;
898
899 // Send back the rob squashing signal so other stages know that
900 // the ROB is in the process of squashing.
901 toIEW->commitInfo[tid].robSquashing = true;
902
903 toIEW->commitInfo[tid].mispredictInst =
904 fromIEW->mispredictInst[tid];
905 toIEW->commitInfo[tid].branchTaken =
906 fromIEW->branchTaken[tid];
907 toIEW->commitInfo[tid].squashInst =
908 rob->findInst(tid, squashed_inst);
909 if (toIEW->commitInfo[tid].mispredictInst) {
910 if (toIEW->commitInfo[tid].mispredictInst->isUncondCtrl()) {
911 toIEW->commitInfo[tid].branchTaken = true;
912 }
913 ++branchMispredicts;
914 }
915
916 toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
917 }
918
919 if (commitStatus[tid] == ROBSquashing) {
920 num_squashing_threads++;
921 }
922 }
923
924 // If commit is currently squashing, then it will have activity for the
925 // next cycle. Set its next status as active.
926 if (num_squashing_threads) {
927 _nextStatus = Active;
928 }
929
930 if (num_squashing_threads != numThreads) {
931 // If we're not currently squashing, then get instructions.
932 getInsts();
933
934 // Try to commit any instructions.
935 commitInsts();
936 }
937
938 //Check for any activity
939 threads = activeThreads->begin();
940
941 while (threads != end) {
942 ThreadID tid = *threads++;
943
944 if (changedROBNumEntries[tid]) {
945 toIEW->commitInfo[tid].usedROB = true;
946 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
947
948 wroteToTimeBuffer = true;
949 changedROBNumEntries[tid] = false;
950 if (rob->isEmpty(tid))
951 checkEmptyROB[tid] = true;
952 }
953
954 // ROB is only considered "empty" for previous stages if: a)
955 // ROB is empty, b) there are no outstanding stores, c) IEW
956 // stage has received any information regarding stores that
957 // committed.
958 // c) is checked by making sure to not consider the ROB empty
959 // on the same cycle as when stores have been committed.
960 // @todo: Make this handle multi-cycle communication between
961 // commit and IEW.
962 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
963 !iewStage->hasStoresToWB(tid) && !committedStores[tid]) {
964 checkEmptyROB[tid] = false;
965 toIEW->commitInfo[tid].usedROB = true;
966 toIEW->commitInfo[tid].emptyROB = true;
967 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
968 wroteToTimeBuffer = true;
969 }
970
971 }
972}
973
974template <class Impl>
975void
976DefaultCommit<Impl>::commitInsts()
977{
978 ////////////////////////////////////
979 // Handle commit
980 // Note that commit will be handled prior to putting new
981 // instructions in the ROB so that the ROB only tries to commit
982 // instructions it has in this current cycle, and not instructions
983 // it is writing in during this cycle. Can't commit and squash
984 // things at the same time...
985 ////////////////////////////////////
986
987 DPRINTF(Commit, "Trying to commit instructions in the ROB.\n");
988
989 unsigned num_committed = 0;
990
991 DynInstPtr head_inst;
992
993 // Commit as many instructions as possible until the commit bandwidth
994 // limit is reached, or it becomes impossible to commit any more.
995 while (num_committed < commitWidth) {
996 // Check for any interrupt that we've already squashed for
997 // and start processing it.
998 if (interrupt != NoFault)
999 handleInterrupt();
1000
1001 ThreadID commit_thread = getCommittingThread();
1002
1003 if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
1004 break;
1005
1006 head_inst = rob->readHeadInst(commit_thread);
1007
1008 ThreadID tid = head_inst->threadNumber;
1009
1010 assert(tid == commit_thread);
1011
1012 DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",
1013 head_inst->seqNum, tid);
1014
1015 // If the head instruction is squashed, it is ready to retire
1016 // (be removed from the ROB) at any time.
1017 if (head_inst->isSquashed()) {
1018
1019 DPRINTF(Commit, "Retiring squashed instruction from "
1020 "ROB.\n");
1021
1022 rob->retireHead(commit_thread);
1023
1024 ++commitSquashedInsts;
1025 // Notify potential listeners that this instruction is squashed
1026 ppSquash->notify(head_inst);
1027
1028 // Record that the number of ROB entries has changed.
1029 changedROBNumEntries[tid] = true;
1030 } else {
1031 pc[tid] = head_inst->pcState();
1032
1033 // Increment the total number of non-speculative instructions
1034 // executed.
1035 // Hack for now: it really shouldn't happen until after the
1036 // commit is deemed to be successful, but this count is needed
1037 // for syscalls.
1038 thread[tid]->funcExeInst++;
1039
1040 // Try to commit the head instruction.
1041 bool commit_success = commitHead(head_inst, num_committed);
1042
1043 if (commit_success) {
1044 ++num_committed;
1045 statCommittedInstType[tid][head_inst->opClass()]++;
1046 ppCommit->notify(head_inst);
1047
1048 changedROBNumEntries[tid] = true;
1049
1050 // Set the doneSeqNum to the youngest committed instruction.
1051 toIEW->commitInfo[tid].doneSeqNum = head_inst->seqNum;
1052
1053 if (tid == 0) {
1054 canHandleInterrupts = (!head_inst->isDelayedCommit()) &&
1055 ((THE_ISA != ALPHA_ISA) ||
1056 (!(pc[0].instAddr() & 0x3)));
1057 }
1058
1059 // Updates misc. registers.
1060 head_inst->updateMiscRegs();
1061
1062 // Check instruction execution if it successfully commits and
1063 // is not carrying a fault.
1064 if (cpu->checker) {
1065 cpu->checker->verify(head_inst);
1066 }
1067
1068 cpu->traceFunctions(pc[tid].instAddr());
1069
1070 TheISA::advancePC(pc[tid], head_inst->staticInst);
1071
1072 // Keep track of the last sequence number commited
1073 lastCommitedSeqNum[tid] = head_inst->seqNum;
1074
1075 // If this is an instruction that doesn't play nicely with
1076 // others squash everything and restart fetch
1077 if (head_inst->isSquashAfter())
1078 squashAfter(tid, head_inst);
1079
1080 if (drainPending) {
1081 if (pc[tid].microPC() == 0 && interrupt == NoFault &&
1082 !thread[tid]->trapPending) {
1083 // Last architectually committed instruction.
1084 // Squash the pipeline, stall fetch, and use
1085 // drainImminent to disable interrupts
1086 DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]);
1087 squashAfter(tid, head_inst);
1088 cpu->commitDrained(tid);
1089 drainImminent = true;
1090 }
1091 }
1092
1093 bool onInstBoundary = !head_inst->isMicroop() ||
1094 head_inst->isLastMicroop() ||
1095 !head_inst->isDelayedCommit();
1096
1097 if (onInstBoundary) {
1098 int count = 0;
1099 Addr oldpc;
1100 // Make sure we're not currently updating state while
1101 // handling PC events.
1102 assert(!thread[tid]->noSquashFromTC &&
1103 !thread[tid]->trapPending);
1104 do {
1105 oldpc = pc[tid].instAddr();
1106 cpu->system->pcEventQueue.service(thread[tid]->getTC());
1107 count++;
1108 } while (oldpc != pc[tid].instAddr());
1109 if (count > 1) {
1110 DPRINTF(Commit,
1111 "PC skip function event, stopping commit\n");
1112 break;
1113 }
1114 }
1115
1116 // Check if an instruction just enabled interrupts and we've
1117 // previously had an interrupt pending that was not handled
1118 // because interrupts were subsequently disabled before the
1119 // pipeline reached a place to handle the interrupt. In that
1120 // case squash now to make sure the interrupt is handled.
1121 //
1122 // If we don't do this, we might end up in a live lock situation
1123 if (!interrupt && avoidQuiesceLiveLock &&
1124 onInstBoundary && cpu->checkInterrupts(cpu->tcBase(0)))
1125 squashAfter(tid, head_inst);
1126 } else {
1127 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1128 "[tid:%i] [sn:%i].\n",
1129 head_inst->pcState(), tid ,head_inst->seqNum);
1130 break;
1131 }
1132 }
1133 }
1134
1135 DPRINTF(CommitRate, "%i\n", num_committed);
1136 numCommittedDist.sample(num_committed);
1137
1138 if (num_committed == commitWidth) {
1139 commitEligibleSamples++;
1140 }
1141}
1142
1143template <class Impl>
1144bool
1145DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
1146{
1147 assert(head_inst);
1148
1149 ThreadID tid = head_inst->threadNumber;
1150
1151 // If the instruction is not executed yet, then it will need extra
1152 // handling. Signal backwards that it should be executed.
1153 if (!head_inst->isExecuted()) {
1154 // Keep this number correct. We have not yet actually executed
1155 // and committed this instruction.
1156 thread[tid]->funcExeInst--;
1157
1158 // Make sure we are only trying to commit un-executed instructions we
1159 // think are possible.
1160 assert(head_inst->isNonSpeculative() || head_inst->isStoreConditional()
1161 || head_inst->isMemBarrier() || head_inst->isWriteBarrier() ||
1162 (head_inst->isLoad() && head_inst->strictlyOrdered()));
1163
1164 DPRINTF(Commit, "Encountered a barrier or non-speculative "
1165 "instruction [sn:%lli] at the head of the ROB, PC %s.\n",
1166 head_inst->seqNum, head_inst->pcState());
1167
1168 if (inst_num > 0 || iewStage->hasStoresToWB(tid)) {
1169 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1170 return false;
1171 }
1172
1173 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1174
1175 // Change the instruction so it won't try to commit again until
1176 // it is executed.
1177 head_inst->clearCanCommit();
1178
1179 if (head_inst->isLoad() && head_inst->strictlyOrdered()) {
1180 DPRINTF(Commit, "[sn:%lli]: Strictly ordered load, PC %s.\n",
1181 head_inst->seqNum, head_inst->pcState());
1182 toIEW->commitInfo[tid].strictlyOrdered = true;
1183 toIEW->commitInfo[tid].strictlyOrderedLoad = head_inst;
1184 } else {
1185 ++commitNonSpecStalls;
1186 }
1187
1188 return false;
1189 }
1190
1191 if (head_inst->isThreadSync()) {
1192 // Not handled for now.
1193 panic("Thread sync instructions are not handled yet.\n");
1194 }
1195
1196 // Check if the instruction caused a fault. If so, trap.
1197 Fault inst_fault = head_inst->getFault();
1198
1199 // Stores mark themselves as completed.
1200 if (!head_inst->isStore() && inst_fault == NoFault) {
1201 head_inst->setCompleted();
1202 }
1203
1204 if (inst_fault != NoFault) {
1205 DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n",
1206 head_inst->seqNum, head_inst->pcState());
1207
1208 if (iewStage->hasStoresToWB(tid) || inst_num > 0) {
1209 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1210 return false;
1211 }
1212
1213 head_inst->setCompleted();
1214
1215 // If instruction has faulted, let the checker execute it and
1216 // check if it sees the same fault and control flow.
1217 if (cpu->checker) {
1218 // Need to check the instruction before its fault is processed
1219 cpu->checker->verify(head_inst);
1220 }
1221
1222 assert(!thread[tid]->noSquashFromTC);
1223
1224 // Mark that we're in state update mode so that the trap's
1225 // execution doesn't generate extra squashes.
1226 thread[tid]->noSquashFromTC = true;
1227
1228 // Execute the trap. Although it's slightly unrealistic in
1229 // terms of timing (as it doesn't wait for the full timing of
1230 // the trap event to complete before updating state), it's
1231 // needed to update the state as soon as possible. This
1232 // prevents external agents from changing any specific state
1233 // that the trap need.
1234 cpu->trap(inst_fault, tid, head_inst->staticInst);
1235
1236 // Exit state update mode to avoid accidental updating.
1237 thread[tid]->noSquashFromTC = false;
1238
1239 commitStatus[tid] = TrapPending;
1240
1241 DPRINTF(Commit, "Committing instruction with fault [sn:%lli]\n",
1242 head_inst->seqNum);
1243 if (head_inst->traceData) {
1244 if (DTRACE(ExecFaulting)) {
1245 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1246 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1247 head_inst->traceData->dump();
1248 }
1249 delete head_inst->traceData;
1250 head_inst->traceData = NULL;
1251 }
1252
1253 // Generate trap squash event.
1254 generateTrapEvent(tid, inst_fault);
1255 return false;
1256 }
1257
1258 updateComInstStats(head_inst);
1259
1260 if (FullSystem) {
1261 if (thread[tid]->profile) {
1262 thread[tid]->profilePC = head_inst->instAddr();
1263 ProfileNode *node = thread[tid]->profile->consume(
1264 thread[tid]->getTC(), head_inst->staticInst);
1265
1266 if (node)
1267 thread[tid]->profileNode = node;
1268 }
1269 if (CPA::available()) {
1270 if (head_inst->isControl()) {
1271 ThreadContext *tc = thread[tid]->getTC();
1272 CPA::cpa()->swAutoBegin(tc, head_inst->nextInstAddr());
1273 }
1274 }
1275 }
1276 DPRINTF(Commit, "Committing instruction with [sn:%lli] PC %s\n",
1277 head_inst->seqNum, head_inst->pcState());
1278 if (head_inst->traceData) {
1279 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1280 head_inst->traceData->setCPSeq(thread[tid]->numOp);
1281 head_inst->traceData->dump();
1282 delete head_inst->traceData;
1283 head_inst->traceData = NULL;
1284 }
1285 if (head_inst->isReturn()) {
1286 DPRINTF(Commit,"Return Instruction Committed [sn:%lli] PC %s \n",
1287 head_inst->seqNum, head_inst->pcState());
1288 }
1289
1290 // Update the commit rename map
1291 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1292 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1293 head_inst->renamedDestRegIdx(i));
1294 }
1295
1296 // Finally clear the head ROB entry.
1297 rob->retireHead(tid);
1298
1299#if TRACING_ON
1300 if (DTRACE(O3PipeView)) {
1301 head_inst->commitTick = curTick() - head_inst->fetchTick;
1302 }
1303#endif
1304
1305 // If this was a store, record it for this cycle.
1306 if (head_inst->isStore())
1307 committedStores[tid] = true;
1308
1309 // Return true to indicate that we have committed an instruction.
1310 return true;
1311}
1312
1313template <class Impl>
1314void
1315DefaultCommit<Impl>::getInsts()
1316{
1317 DPRINTF(Commit, "Getting instructions from Rename stage.\n");
1318
1319 // Read any renamed instructions and place them into the ROB.
1320 int insts_to_process = std::min((int)renameWidth, fromRename->size);
1321
1322 for (int inst_num = 0; inst_num < insts_to_process; ++inst_num) {
1323 DynInstPtr inst;
1324
1325 inst = fromRename->insts[inst_num];
1326 ThreadID tid = inst->threadNumber;
1327
1328 if (!inst->isSquashed() &&
1329 commitStatus[tid] != ROBSquashing &&
1330 commitStatus[tid] != TrapPending) {
1331 changedROBNumEntries[tid] = true;
1332
1333 DPRINTF(Commit, "Inserting PC %s [sn:%i] [tid:%i] into ROB.\n",
1334 inst->pcState(), inst->seqNum, tid);
1335
1336 rob->insertInst(inst);
1337
1338 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));
1339
1340 youngestSeqNum[tid] = inst->seqNum;
1341 } else {
1342 DPRINTF(Commit, "Instruction PC %s [sn:%i] [tid:%i] was "
1343 "squashed, skipping.\n",
1344 inst->pcState(), inst->seqNum, tid);
1345 }
1346 }
1347}
1348
1349template <class Impl>
1350void
1351DefaultCommit<Impl>::markCompletedInsts()
1352{
1353 // Grab completed insts out of the IEW instruction queue, and mark
1354 // instructions completed within the ROB.
1355 for (int inst_num = 0; inst_num < fromIEW->size; ++inst_num) {
1356 assert(fromIEW->insts[inst_num]);
1357 if (!fromIEW->insts[inst_num]->isSquashed()) {
1358 DPRINTF(Commit, "[tid:%i]: Marking PC %s, [sn:%lli] ready "
1359 "within ROB.\n",
1360 fromIEW->insts[inst_num]->threadNumber,
1361 fromIEW->insts[inst_num]->pcState(),
1362 fromIEW->insts[inst_num]->seqNum);
1363
1364 // Mark the instruction as ready to commit.
1365 fromIEW->insts[inst_num]->setCanCommit();
1366 }
1367 }
1368}
1369
1370template <class Impl>
1371void
1372DefaultCommit<Impl>::updateComInstStats(DynInstPtr &inst)
1373{
1374 ThreadID tid = inst->threadNumber;
1375
1376 if (!inst->isMicroop() || inst->isLastMicroop())
1377 instsCommitted[tid]++;
1378 opsCommitted[tid]++;
1379
1380 // To match the old model, don't count nops and instruction
1381 // prefetches towards the total commit count.
1382 if (!inst->isNop() && !inst->isInstPrefetch()) {
1383 cpu->instDone(tid, inst);
1384 }
1385
1386 //
1387 // Control Instructions
1388 //
1389 if (inst->isControl())
1390 statComBranches[tid]++;
1391
1392 //
1393 // Memory references
1394 //
1395 if (inst->isMemRef()) {
1396 statComRefs[tid]++;
1397
1398 if (inst->isLoad()) {
1399 statComLoads[tid]++;
1400 }
1401 }
1402
1403 if (inst->isMemBarrier()) {
1404 statComMembars[tid]++;
1405 }
1406
1407 // Integer Instruction
1408 if (inst->isInteger())
1409 statComInteger[tid]++;
1410
1411 // Floating Point Instruction
1412 if (inst->isFloating())
1413 statComFloating[tid]++;
1414 // Vector Instruction
1415 if (inst->isVector())
1416 statComVector[tid]++;
1417
1418 // Function Calls
1419 if (inst->isCall())
1420 statComFunctionCalls[tid]++;
1421
1422}
1423
1424////////////////////////////////////////
1425// //
1426// SMT COMMIT POLICY MAINTAINED HERE //
1427// //
1428////////////////////////////////////////
1429template <class Impl>
1430ThreadID
1431DefaultCommit<Impl>::getCommittingThread()
1432{
1433 if (numThreads > 1) {
1434 switch (commitPolicy) {
1435
1436 case Aggressive:
1437 //If Policy is Aggressive, commit will call
1438 //this function multiple times per
1439 //cycle
1440 return oldestReady();
1441
1442 case RoundRobin:
1443 return roundRobin();
1444
1445 case OldestReady:
1446 return oldestReady();
1447
1448 default:
1449 return InvalidThreadID;
1450 }
1451 } else {
1452 assert(!activeThreads->empty());
1453 ThreadID tid = activeThreads->front();
1454
1455 if (commitStatus[tid] == Running ||
1456 commitStatus[tid] == Idle ||
1457 commitStatus[tid] == FetchTrapPending) {
1458 return tid;
1459 } else {
1460 return InvalidThreadID;
1461 }
1462 }
1463}
1464
1465template<class Impl>
1466ThreadID
1467DefaultCommit<Impl>::roundRobin()
1468{
1469 list<ThreadID>::iterator pri_iter = priority_list.begin();
1470 list<ThreadID>::iterator end = priority_list.end();
1471
1472 while (pri_iter != end) {
1473 ThreadID tid = *pri_iter;
1474
1475 if (commitStatus[tid] == Running ||
1476 commitStatus[tid] == Idle ||
1477 commitStatus[tid] == FetchTrapPending) {
1478
1479 if (rob->isHeadReady(tid)) {
1480 priority_list.erase(pri_iter);
1481 priority_list.push_back(tid);
1482
1483 return tid;
1484 }
1485 }
1486
1487 pri_iter++;
1488 }
1489
1490 return InvalidThreadID;
1491}
1492
1493template<class Impl>
1494ThreadID
1495DefaultCommit<Impl>::oldestReady()
1496{
1497 unsigned oldest = 0;
1498 bool first = true;
1499
1500 list<ThreadID>::iterator threads = activeThreads->begin();
1501 list<ThreadID>::iterator end = activeThreads->end();
1502
1503 while (threads != end) {
1504 ThreadID tid = *threads++;
1505
1506 if (!rob->isEmpty(tid) &&
1507 (commitStatus[tid] == Running ||
1508 commitStatus[tid] == Idle ||
1509 commitStatus[tid] == FetchTrapPending)) {
1510
1511 if (rob->isHeadReady(tid)) {
1512
1513 DynInstPtr head_inst = rob->readHeadInst(tid);
1514
1515 if (first) {
1516 oldest = tid;
1517 first = false;
1518 } else if (head_inst->seqNum < oldest) {
1519 oldest = tid;
1520 }
1521 }
1522 }
1523 }
1524
1525 if (!first) {
1526 return oldest;
1527 } else {
1528 return InvalidThreadID;
1529 }
1530}
1531
1532#endif//__CPU_O3_COMMIT_IMPL_HH__