1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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53#include "cpu/o3/commit.hh"
54#include "cpu/o3/thread_state.hh"
55#include "cpu/exetrace.hh"
56#include "cpu/timebuf.hh"
57#include "debug/Activity.hh"
58#include "debug/Commit.hh"
59#include "debug/CommitRate.hh"
60#include "debug/ExecFaulting.hh"
61#include "params/DerivO3CPU.hh"
62#include "sim/faults.hh"
63
64#if USE_CHECKER
65#include "cpu/checker/cpu.hh"
66#endif
67
68using namespace std;

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1202 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1203 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1204 head_inst->renamedDestRegIdx(i));
1205 }
1206
1207 // Finally clear the head ROB entry.
1208 rob->retireHead(tid);
1209
1210 // If this was a store, record it for this cycle.
1211 if (head_inst->isStore())
1212 committedStores[tid] = true;
1213
1214 // Return true to indicate that we have committed an instruction.
1215 return true;
1216}
1217

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