1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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1137 // that the trap need.
1138 cpu->trap(inst_fault, tid, head_inst->staticInst);
1139
1140 // Exit state update mode to avoid accidental updating.
1141 thread[tid]->inSyscall = false;
1142
1143 commitStatus[tid] = TrapPending;
1144
1145 if (head_inst->traceData) {
1146 if (DTRACE(ExecFaulting)) {
1147 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1148 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1149 head_inst->traceData->dump();
1150 }
1151 delete head_inst->traceData;
1152 head_inst->traceData = NULL;

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