1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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113 } else {
114 assert(0 && "Invalid SMT Commit Policy. Options Are: {Aggressive,"
115 "RoundRobin,OldestReady}");
116 }
117
118 for (int i=0; i < numThreads; i++) {
119 commitStatus[i] = Idle;
120 changedROBNumEntries[i] = false;
121 checkEmptyROB[i] = false;
122 trapInFlight[i] = false;
123 committedStores[i] = false;
124 trapSquash[i] = false;
125 tcSquash[i] = false;
126 PC[i] = nextPC[i] = nextNPC[i] = 0;
127 }
128#if FULL_SYSTEM
129 interrupt = NoFault;
130#endif
131}

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333{
334 rob->setActiveThreads(activeThreads);
335 rob->resetEntries();
336
337 // Broadcast the number of free entries.
338 for (int i=0; i < numThreads; i++) {
339 toIEW->commitInfo[i].usedROB = true;
340 toIEW->commitInfo[i].freeROBEntries = rob->numFreeEntries(i);
341 toIEW->commitInfo[i].emptyROB = true;
342 }
343
344 cpu->activityThisCycle();
345}
346
347template <class Impl>
348bool
349DefaultCommit<Impl>::drain()

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472void
473DefaultCommit<Impl>::generateTrapEvent(unsigned tid)
474{
475 DPRINTF(Commit, "Generating trap event for [tid:%i]\n", tid);
476
477 TrapEvent *trap = new TrapEvent(this, tid);
478
479 trap->schedule(curTick + trapLatency);
480 trapInFlight[tid] = true;
481}
482
483template <class Impl>
484void
485DefaultCommit<Impl>::generateTCEvent(unsigned tid)
486{
487 assert(!trapInFlight[tid]);
488 DPRINTF(Commit, "Generating TC squash event for [tid:%i]\n", tid);
489
490 tcSquash[tid] = true;
491}
492
493template <class Impl>
494void
495DefaultCommit<Impl>::squashAll(unsigned tid)
496{
497 // If we want to include the squashing instruction in the squash,
498 // then use one older sequence number.
499 // Hopefully this doesn't mess things up. Basically I want to squash
500 // all instructions of this thread.
501 InstSeqNum squashed_inst = rob->isEmpty() ?
502 0 : rob->readHeadInst(tid)->seqNum - 1;
503
504 // All younger instructions will be squashed. Set the sequence
505 // number as the youngest instruction in the ROB (0 in this case.
506 // Hopefully nothing breaks.)
507 youngestSeqNum[tid] = 0;
508
509 rob->squash(squashed_inst, tid);
510 changedROBNumEntries[tid] = true;

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531DefaultCommit<Impl>::squashFromTrap(unsigned tid)
532{
533 squashAll(tid);
534
535 DPRINTF(Commit, "Squashing from trap, restarting at PC %#x\n", PC[tid]);
536
537 thread[tid]->trapPending = false;
538 thread[tid]->inSyscall = false;
539 trapInFlight[tid] = false;
540
541 trapSquash[tid] = false;
542
543 commitStatus[tid] = ROBSquashing;
544 cpu->activityThisCycle();
545}
546
547template <class Impl>

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580 std::list<unsigned>::iterator threads = activeThreads->begin();
581 std::list<unsigned>::iterator end = activeThreads->end();
582
583 // Check if any of the threads are done squashing. Change the
584 // status if they are done.
585 while (threads != end) {
586 unsigned tid = *threads++;
587
588 // Clear the bit saying if the thread has committed stores
589 // this cycle.
590 committedStores[tid] = false;
591
592 if (commitStatus[tid] == ROBSquashing) {
593
594 if (rob->isDoneSquashing(tid)) {
595 commitStatus[tid] = Running;
596 } else {
597 DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any"
598 " insts this cycle.\n", tid);
599 rob->doSquash(tid);

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639 if (wroteToTimeBuffer) {
640 DPRINTF(Activity, "Activity This Cycle.\n");
641 cpu->activityThisCycle();
642 }
643
644 updateStatus();
645}
646
647#if FULL_SYSTEM
648template <class Impl>
649void
650DefaultCommit<Impl>::handleInterrupt()
651{
652 if (interrupt != NoFault) {
653 // Wait until the ROB is empty and all stores have drained in
654 // order to enter the interrupt.
655 if (rob->isEmpty() && !iewStage->hasStoresToWB()) {
656 // Squash or record that I need to squash this cycle if
657 // an interrupt needed to be handled.
658 DPRINTF(Commit, "Interrupt detected.\n");
659
660 Fault new_interrupt = cpu->getInterrupts();
661 assert(new_interrupt == interrupt);
662
663 // Clear the interrupt now that it's going to be handled
664 toIEW->commitInfo[0].clearInterrupt = true;
665
666 assert(!thread[0]->inSyscall);
667 thread[0]->inSyscall = true;
668
669 // CPU will handle interrupt.
670 cpu->processInterrupts(interrupt);
671
672 thread[0]->inSyscall = false;
673
674 commitStatus[0] = TrapPending;
675
676 // Generate trap squash event.
677 generateTrapEvent(0);
678
679 interrupt = NoFault;
680 } else {
681 DPRINTF(Commit, "Interrupt pending, waiting for ROB to empty.\n");
682 }
683 } else if (commitStatus[0] != TrapPending &&
684 cpu->check_interrupts(cpu->tcBase(0)) &&
685 !trapSquash[0] &&
686 !tcSquash[0]) {
687 // Process interrupts if interrupts are enabled, not in PAL
688 // mode, and no other traps or external squashes are currently
689 // pending.
690 // @todo: Allow other threads to handle interrupts.
691
692 // Get any interrupt that happened
693 interrupt = cpu->getInterrupts();
694
695 if (interrupt != NoFault) {
696 // Tell fetch that there is an interrupt pending. This
697 // will make fetch wait until it sees a non PAL-mode PC,
698 // at which point it stops fetching instructions.
699 toIEW->commitInfo[0].interruptPending = true;
700 }
701 }
702}
703#endif // FULL_SYSTEM
704
705template <class Impl>
706void
707DefaultCommit<Impl>::commit()
708{
709
710#if FULL_SYSTEM
711 // Check for any interrupt, and start processing it. Or if we
712 // have an outstanding interrupt and are at a point when it is
713 // valid to take an interrupt, process it.
714 if (cpu->check_interrupts(cpu->tcBase(0))) {
715 handleInterrupt();
716 }
717#endif // FULL_SYSTEM
718
719 ////////////////////////////////////
720 // Check for any possible squashes, handle them first
721 ////////////////////////////////////
722 std::list<unsigned>::iterator threads = activeThreads->begin();
723 std::list<unsigned>::iterator end = activeThreads->end();
724
725 while (threads != end) {
726 unsigned tid = *threads++;
727
728 // Not sure which one takes priority. I think if we have
729 // both, that's a bad sign.
730 if (trapSquash[tid] == true) {
731 assert(!tcSquash[tid]);
732 squashFromTrap(tid);
733 } else if (tcSquash[tid] == true) {
734 assert(commitStatus[tid] != TrapPending);
735 squashFromTC(tid);
736 }
737
738 // Squashed sequence number must be older than youngest valid
739 // instruction in the ROB. This prevents squashes from younger
740 // instructions overriding squashes from older instructions.
741 if (fromIEW->squash[tid] &&
742 commitStatus[tid] != TrapPending &&

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771#endif
772
773 if (fromIEW->includeSquashInst[tid] == true) {
774 squashed_inst--;
775#if ISA_HAS_DELAY_SLOT
776 bdelay_done_seq_num--;
777#endif
778 }
779
780 // All younger instructions will be squashed. Set the sequence
781 // number as the youngest instruction in the ROB.
782 youngestSeqNum[tid] = squashed_inst;
783
784#if ISA_HAS_DELAY_SLOT
785 rob->squash(bdelay_done_seq_num, tid);
786 toIEW->commitInfo[tid].squashDelaySlot = squash_bdelay_slot;
787 toIEW->commitInfo[tid].bdelayDoneSeqNum = bdelay_done_seq_num;

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836
837 while (threads != end) {
838 unsigned tid = *threads++;
839
840 if (changedROBNumEntries[tid]) {
841 toIEW->commitInfo[tid].usedROB = true;
842 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
843
844 wroteToTimeBuffer = true;
845 changedROBNumEntries[tid] = false;
846 if (rob->isEmpty(tid))
847 checkEmptyROB[tid] = true;
848 }
849
850 // ROB is only considered "empty" for previous stages if: a)
851 // ROB is empty, b) there are no outstanding stores, c) IEW
852 // stage has received any information regarding stores that
853 // committed.
854 // c) is checked by making sure to not consider the ROB empty
855 // on the same cycle as when stores have been committed.
856 // @todo: Make this handle multi-cycle communication between
857 // commit and IEW.
858 if (checkEmptyROB[tid] && rob->isEmpty(tid) &&
859 !iewStage->hasStoresToWB() && !committedStores[tid]) {
860 checkEmptyROB[tid] = false;
861 toIEW->commitInfo[tid].usedROB = true;
862 toIEW->commitInfo[tid].emptyROB = true;
863 toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
864 wroteToTimeBuffer = true;
865 }
866
867 }
868}
869
870template <class Impl>
871void
872DefaultCommit<Impl>::commitInsts()
873{
874 ////////////////////////////////////

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1001
1002 // If the instruction is not executed yet, then it will need extra
1003 // handling. Signal backwards that it should be executed.
1004 if (!head_inst->isExecuted()) {
1005 // Keep this number correct. We have not yet actually executed
1006 // and committed this instruction.
1007 thread[tid]->funcExeInst--;
1008
1009 if (head_inst->isNonSpeculative() ||
1010 head_inst->isStoreConditional() ||
1011 head_inst->isMemBarrier() ||
1012 head_inst->isWriteBarrier()) {
1013
1014 DPRINTF(Commit, "Encountered a barrier or non-speculative "
1015 "instruction [sn:%lli] at the head of the ROB, PC %#x.\n",
1016 head_inst->seqNum, head_inst->readPC());
1017
1018 if (inst_num > 0 || iewStage->hasStoresToWB()) {
1019 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1020 return false;
1021 }
1022
1023 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1024
1025 // Change the instruction so it won't try to commit again until
1026 // it is executed.
1027 head_inst->clearCanCommit();
1028
1029 ++commitNonSpecStalls;
1030
1031 return false;
1032 } else if (head_inst->isLoad()) {
1033 if (inst_num > 0 || iewStage->hasStoresToWB()) {
1034 DPRINTF(Commit, "Waiting for all stores to writeback.\n");
1035 return false;
1036 }
1037
1038 assert(head_inst->uncacheable());
1039 DPRINTF(Commit, "[sn:%lli]: Uncached load, PC %#x.\n",
1040 head_inst->seqNum, head_inst->readPC());
1041
1042 // Send back the non-speculative instruction's sequence
1043 // number. Tell the lsq to re-execute the load.
1044 toIEW->commitInfo[tid].nonSpecSeqNum = head_inst->seqNum;
1045 toIEW->commitInfo[tid].uncached = true;
1046 toIEW->commitInfo[tid].uncachedLoad = head_inst;

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1054 }
1055 }
1056
1057 if (head_inst->isThreadSync()) {
1058 // Not handled for now.
1059 panic("Thread sync instructions are not handled yet.\n");
1060 }
1061
1062 // Check if the instruction caused a fault. If so, trap.
1063 Fault inst_fault = head_inst->getFault();
1064
1065 // Stores mark themselves as completed.
1066 if (!head_inst->isStore() && inst_fault == NoFault) {
1067 head_inst->setCompleted();
1068 }
1069
1070#if USE_CHECKER
1071 // Use checker prior to updating anything due to traps or PC
1072 // based events.
1073 if (cpu->checker) {
1074 cpu->checker->verify(head_inst);
1075 }
1076#endif
1077
1078 // DTB will sometimes need the machine instruction for when
1079 // faults happen. So we will set it here, prior to the DTB
1080 // possibly needing it for its fault.
1081 thread[tid]->setInst(
1082 static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
1083
1084 if (inst_fault != NoFault) {
1085 DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
1086 head_inst->seqNum, head_inst->readPC());
1087
1088 if (iewStage->hasStoresToWB() || inst_num > 0) {
1089 DPRINTF(Commit, "Stores outstanding, fault must wait.\n");
1090 return false;
1091 }
1092
1093 head_inst->setCompleted();
1094
1095#if USE_CHECKER
1096 if (cpu->checker && head_inst->isStore()) {
1097 cpu->checker->verify(head_inst);
1098 }
1099#endif
1100
1101 assert(!thread[tid]->inSyscall);
1102

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1112 // that the trap need.
1113 cpu->trap(inst_fault, tid);
1114
1115 // Exit state update mode to avoid accidental updating.
1116 thread[tid]->inSyscall = false;
1117
1118 commitStatus[tid] = TrapPending;
1119
1120 if (head_inst->traceData) {
1121 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1122 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1123 head_inst->traceData->finalize();
1124 head_inst->traceData = NULL;
1125 }
1126
1127 // Generate trap squash event.
1128 generateTrapEvent(tid);
1129// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC());
1130 return false;
1131 }
1132
1133 updateComInstStats(head_inst);
1134

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1143 if (node)
1144 thread[tid]->profileNode = node;
1145 }
1146#endif
1147
1148 if (head_inst->traceData) {
1149 head_inst->traceData->setFetchSeq(head_inst->seqNum);
1150 head_inst->traceData->setCPSeq(thread[tid]->numInst);
1151 head_inst->traceData->finalize();
1152 head_inst->traceData = NULL;
1153 }
1154
1155 // Update the commit rename map
1156 for (int i = 0; i < head_inst->numDestRegs(); i++) {
1157 renameMap[tid]->setEntry(head_inst->flattenedDestRegIdx(i),
1158 head_inst->renamedDestRegIdx(i));
1159 }
1160
1161 if (head_inst->isCopy())
1162 panic("Should not commit any copy instructions!");
1163
1164 // Finally clear the head ROB entry.
1165 rob->retireHead(tid);
1166
1167 // If this was a store, record it for this cycle.
1168 if (head_inst->isStore())
1169 committedStores[tid] = true;
1170
1171 // Return true to indicate that we have committed an instruction.
1172 return true;
1173}
1174
1175template <class Impl>
1176void
1177DefaultCommit<Impl>::getInsts()
1178{

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1207 inst = fromRename->insts[rename_idx++];
1208 }
1209#else
1210 inst = fromRename->insts[inst_num];
1211#endif
1212 int tid = inst->threadNumber;
1213
1214 if (!inst->isSquashed() &&
1215 commitStatus[tid] != ROBSquashing &&
1216 commitStatus[tid] != TrapPending) {
1217 changedROBNumEntries[tid] = true;
1218
1219 DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ROB.\n",
1220 inst->readPC(), inst->seqNum, tid);
1221
1222 rob->insertInst(inst);
1223
1224 assert(rob->getThreadEntries(tid) <= rob->getMaxEntries(tid));

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