1/*
2 * Copyright (c) 2010-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license

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1100 // drainImminent to disable interrupts
1101 DPRINTF(Drain, "Draining: %i:%s\n", tid, pc[tid]);
1102 squashAfter(tid, head_inst);
1103 cpu->commitDrained(tid);
1104 drainImminent = true;
1105 }
1106 }
1107
1108 int count = 0;
1109 Addr oldpc;
1110 // Debug statement. Checks to make sure we're not
1111 // currently updating state while handling PC events.
1112 assert(!thread[tid]->noSquashFromTC && !thread[tid]->trapPending);
1113 do {
1114 oldpc = pc[tid].instAddr();
1115 cpu->system->pcEventQueue.service(thread[tid]->getTC());
1116 count++;
1117 } while (oldpc != pc[tid].instAddr());
1118 if (count > 1) {
1119 DPRINTF(Commit,
1120 "PC skip function event, stopping commit\n");
1121 break;
1122 }
1123
1124 // Check if an instruction just enabled interrupts and we've
1125 // previously had an interrupt pending that was not handled
1126 // because interrupts were subsequently disabled before the
1127 // pipeline reached a place to handle the interrupt. In that
1128 // case squash now to make sure the interrupt is handled.
1129 //
1130 // If we don't do this, we might end up in a live lock situation
1131 if (!interrupt && avoidQuiesceLiveLock &&
1132 (!head_inst->isMicroop() || head_inst->isLastMicroop()) &&
1133 cpu->checkInterrupts(cpu->tcBase(0)))
1134 squashAfter(tid, head_inst);
1135 } else {
1136 DPRINTF(Commit, "Unable to commit head instruction PC:%s "
1137 "[tid:%i] [sn:%i].\n",
1138 head_inst->pcState(), tid ,head_inst->seqNum);
1139 break;
1140 }
1141 }

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