commit.hh (8737:770ccf3af571) commit.hh (8793:5f25086326ac)
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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46
47#include <queue>
48
49#include "base/statistics.hh"
50#include "cpu/exetrace.hh"
51#include "cpu/inst_seq.hh"
52#include "cpu/timebuf.hh"
53
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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46
47#include <queue>
48
49#include "base/statistics.hh"
50#include "cpu/exetrace.hh"
51#include "cpu/inst_seq.hh"
52#include "cpu/timebuf.hh"
53
54struct DerivO3CPUParams;
54class DerivO3CPUParams;
55
56template <class>
55
56template <class>
57struct O3ThreadState;
57class O3ThreadState;
58
59/**
60 * DefaultCommit handles single threaded and SMT commit. Its width is
61 * specified by the parameters; each cycle it tries to commit that
62 * many instructions. The SMT policy decides which thread it tries to
63 * commit instructions from. Non- speculative instructions must reach
64 * the head of the ROB before they are ready to execute; once they
65 * reach the head, commit will broadcast the instruction's sequence

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262 /** Handles squashing from instruction with SquashAfter set.
263 * This differs from the other squashes as it squashes following
264 * instructions instead of the current instruction and doesn't
265 * clean up various status bits about traps/tc writes pending.
266 */
267 void squashAfter(ThreadID tid, DynInstPtr &head_inst,
268 uint64_t squash_after_seq_num);
269
58
59/**
60 * DefaultCommit handles single threaded and SMT commit. Its width is
61 * specified by the parameters; each cycle it tries to commit that
62 * many instructions. The SMT policy decides which thread it tries to
63 * commit instructions from. Non- speculative instructions must reach
64 * the head of the ROB before they are ready to execute; once they
65 * reach the head, commit will broadcast the instruction's sequence

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262 /** Handles squashing from instruction with SquashAfter set.
263 * This differs from the other squashes as it squashes following
264 * instructions instead of the current instruction and doesn't
265 * clean up various status bits about traps/tc writes pending.
266 */
267 void squashAfter(ThreadID tid, DynInstPtr &head_inst,
268 uint64_t squash_after_seq_num);
269
270#if FULL_SYSTEM
271 /** Handles processing an interrupt. */
272 void handleInterrupt();
273
274 /** Get fetch redirecting so we can handle an interrupt */
275 void propagateInterrupt();
270 /** Handles processing an interrupt. */
271 void handleInterrupt();
272
273 /** Get fetch redirecting so we can handle an interrupt */
274 void propagateInterrupt();
276#endif // FULL_SYSTEM
277
278 /** Commits as many instructions as possible. */
279 void commitInsts();
280
281 /** Tries to commit the head ROB instruction passed in.
282 * @param head_inst The instruction to be committed.
283 */
284 bool commitHead(DynInstPtr &head_inst, unsigned inst_num);

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276 /** Commits as many instructions as possible. */
277 void commitInsts();
278
279 /** Tries to commit the head ROB instruction passed in.
280 * @param head_inst The instruction to be committed.
281 */
282 bool commitHead(DynInstPtr &head_inst, unsigned inst_num);

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