commit.hh (2980:eab855f06b79) | commit.hh (3640:3a2f7b451641) |
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1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 378 unchanged lines hidden (view full) --- 387 /** Is commit switched out. */ 388 bool switchedOut; 389 390 /** The latency to handle a trap. Used when scheduling trap 391 * squash event. 392 */ 393 Tick trapLatency; 394 | 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 378 unchanged lines hidden (view full) --- 387 /** Is commit switched out. */ 388 bool switchedOut; 389 390 /** The latency to handle a trap. Used when scheduling trap 391 * squash event. 392 */ 393 Tick trapLatency; 394 |
395 /** The interrupt fault. */ 396 Fault interrupt; 397 |
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395 /** The commit PC of each thread. Refers to the instruction that 396 * is currently being processed/committed. 397 */ 398 Addr PC[Impl::MaxThreads]; 399 400 /** The next PC of each thread. */ 401 Addr nextPC[Impl::MaxThreads]; 402 --- 53 unchanged lines hidden --- | 398 /** The commit PC of each thread. Refers to the instruction that 399 * is currently being processed/committed. 400 */ 401 Addr PC[Impl::MaxThreads]; 402 403 /** The next PC of each thread. */ 404 Addr nextPC[Impl::MaxThreads]; 405 --- 53 unchanged lines hidden --- |