commit.hh (2733:e0eac8fc5774) commit.hh (2756:7bf0d6481df9)
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 12 unchanged lines hidden (view full) ---

21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 12 unchanged lines hidden (view full) ---

21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
29 */
30
31#ifndef __CPU_O3_COMMIT_HH__
32#define __CPU_O3_COMMIT_HH__
33
34#include "arch/faults.hh"
35#include "base/statistics.hh"
36#include "base/timebuf.hh"

--- 25 unchanged lines hidden (view full) ---

62 * supports multiple cycle squashing, to model a ROB that can only
63 * remove a certain number of instructions per cycle.
64 */
65template<class Impl>
66class DefaultCommit
67{
68 public:
69 // Typedefs from the Impl.
30 */
31
32#ifndef __CPU_O3_COMMIT_HH__
33#define __CPU_O3_COMMIT_HH__
34
35#include "arch/faults.hh"
36#include "base/statistics.hh"
37#include "base/timebuf.hh"

--- 25 unchanged lines hidden (view full) ---

63 * supports multiple cycle squashing, to model a ROB that can only
64 * remove a certain number of instructions per cycle.
65 */
66template<class Impl>
67class DefaultCommit
68{
69 public:
70 // Typedefs from the Impl.
70 typedef typename Impl::O3CPU O3CPU;
71 typedef typename Impl::FullCPU FullCPU;
71 typedef typename Impl::DynInstPtr DynInstPtr;
72 typedef typename Impl::Params Params;
73 typedef typename Impl::CPUPol CPUPol;
74
75 typedef typename CPUPol::RenameMap RenameMap;
76 typedef typename CPUPol::ROB ROB;
77
78 typedef typename CPUPol::TimeStruct TimeStruct;

--- 61 unchanged lines hidden (view full) ---

140
141 /** Returns the name of the DefaultCommit. */
142 std::string name() const;
143
144 /** Registers statistics. */
145 void regStats();
146
147 /** Sets the CPU pointer. */
72 typedef typename Impl::DynInstPtr DynInstPtr;
73 typedef typename Impl::Params Params;
74 typedef typename Impl::CPUPol CPUPol;
75
76 typedef typename CPUPol::RenameMap RenameMap;
77 typedef typename CPUPol::ROB ROB;
78
79 typedef typename CPUPol::TimeStruct TimeStruct;

--- 61 unchanged lines hidden (view full) ---

141
142 /** Returns the name of the DefaultCommit. */
143 std::string name() const;
144
145 /** Registers statistics. */
146 void regStats();
147
148 /** Sets the CPU pointer. */
148 void setCPU(O3CPU *cpu_ptr);
149 void setCPU(FullCPU *cpu_ptr);
149
150 /** Sets the list of threads. */
151 void setThreads(std::vector<Thread *> &threads);
152
153 /** Sets the main time buffer pointer, used for backwards communication. */
154 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
155
156 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);

--- 118 unchanged lines hidden (view full) ---

275 uint64_t readPC() { return PC[0]; }
276
277 /** Returns the PC of a specific thread. */
278 uint64_t readPC(unsigned tid) { return PC[tid]; }
279
280 /** Sets the PC of a specific thread. */
281 void setPC(uint64_t val, unsigned tid) { PC[tid] = val; }
282
150
151 /** Sets the list of threads. */
152 void setThreads(std::vector<Thread *> &threads);
153
154 /** Sets the main time buffer pointer, used for backwards communication. */
155 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
156
157 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);

--- 118 unchanged lines hidden (view full) ---

276 uint64_t readPC() { return PC[0]; }
277
278 /** Returns the PC of a specific thread. */
279 uint64_t readPC(unsigned tid) { return PC[tid]; }
280
281 /** Sets the PC of a specific thread. */
282 void setPC(uint64_t val, unsigned tid) { PC[tid] = val; }
283
283 /** Reads the PC of a specific thread. */
284 /** Reads the next PC of a specific thread. */
284 uint64_t readNextPC(unsigned tid) { return nextPC[tid]; }
285
286 /** Sets the next PC of a specific thread. */
287 void setNextPC(uint64_t val, unsigned tid) { nextPC[tid] = val; }
288
285 uint64_t readNextPC(unsigned tid) { return nextPC[tid]; }
286
287 /** Sets the next PC of a specific thread. */
288 void setNextPC(uint64_t val, unsigned tid) { nextPC[tid] = val; }
289
290#if THE_ISA != ALPHA_ISA
291 /** Reads the next NPC of a specific thread. */
292 uint64_t readNextPC(unsigned tid) { return nextNPC[tid]; }
293
294 /** Sets the next NPC of a specific thread. */
295 void setNextPC(uint64_t val, unsigned tid) { nextNPC[tid] = val; }
296#endif
297
289 private:
290 /** Time buffer interface. */
291 TimeBuffer<TimeStruct> *timeBuffer;
292
293 /** Wire to write information heading to previous stages. */
294 typename TimeBuffer<TimeStruct>::wire toIEW;
295
296 /** Wire to read information from IEW (for ROB). */

--- 15 unchanged lines hidden (view full) ---

312 /** Wire to read information from rename queue. */
313 typename TimeBuffer<RenameStruct>::wire fromRename;
314
315 public:
316 /** ROB interface. */
317 ROB *rob;
318
319 private:
298 private:
299 /** Time buffer interface. */
300 TimeBuffer<TimeStruct> *timeBuffer;
301
302 /** Wire to write information heading to previous stages. */
303 typename TimeBuffer<TimeStruct>::wire toIEW;
304
305 /** Wire to read information from IEW (for ROB). */

--- 15 unchanged lines hidden (view full) ---

321 /** Wire to read information from rename queue. */
322 typename TimeBuffer<RenameStruct>::wire fromRename;
323
324 public:
325 /** ROB interface. */
326 ROB *rob;
327
328 private:
320 /** Pointer to O3CPU. */
321 O3CPU *cpu;
329 /** Pointer to FullCPU. */
330 FullCPU *cpu;
322
323 /** Vector of all of the threads. */
324 std::vector<Thread *> thread;
325
326 Fault fetchFault;
327
328 int fetchTrapWait;
329

--- 62 unchanged lines hidden (view full) ---

392 /** The commit PC of each thread. Refers to the instruction that
393 * is currently being processed/committed.
394 */
395 Addr PC[Impl::MaxThreads];
396
397 /** The next PC of each thread. */
398 Addr nextPC[Impl::MaxThreads];
399
331
332 /** Vector of all of the threads. */
333 std::vector<Thread *> thread;
334
335 Fault fetchFault;
336
337 int fetchTrapWait;
338

--- 62 unchanged lines hidden (view full) ---

401 /** The commit PC of each thread. Refers to the instruction that
402 * is currently being processed/committed.
403 */
404 Addr PC[Impl::MaxThreads];
405
406 /** The next PC of each thread. */
407 Addr nextPC[Impl::MaxThreads];
408
409 /** The next NPC of each thread. */
410 Addr nextNPC[Impl::MaxThreads];
411
400 /** The sequence number of the youngest valid instruction in the ROB. */
401 InstSeqNum youngestSeqNum[Impl::MaxThreads];
402
403 /** Pointer to the list of active threads. */
404 std::list<unsigned> *activeThreads;
405
406 /** Rename map interface. */
407 RenameMap *renameMap[Impl::MaxThreads];

--- 42 unchanged lines hidden --- 		412 /** The sequence number of the youngest valid instruction in the ROB. */
413 InstSeqNum youngestSeqNum[Impl::MaxThreads];
414
415 /** Pointer to the list of active threads. */
416 std::list<unsigned> *activeThreads;
417
418 /** Rename map interface. */
419 RenameMap *renameMap[Impl::MaxThreads];

--- 42 unchanged lines hidden ---