1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#ifndef __CPU_O3_COMMIT_HH__
45#define __CPU_O3_COMMIT_HH__
46
47#include <queue>
48
49#include "base/statistics.hh"
50#include "cpu/exetrace.hh"
51#include "cpu/inst_seq.hh"
52#include "cpu/timebuf.hh"
53
54struct DerivO3CPUParams;
55
56template <class>
57struct O3ThreadState;
58
59/**
60 * DefaultCommit handles single threaded and SMT commit. Its width is
61 * specified by the parameters; each cycle it tries to commit that
62 * many instructions. The SMT policy decides which thread it tries to
63 * commit instructions from. Non- speculative instructions must reach
64 * the head of the ROB before they are ready to execute; once they
65 * reach the head, commit will broadcast the instruction's sequence
66 * number to the previous stages so that they can issue/ execute the
67 * instruction. Only one non-speculative instruction is handled per
68 * cycle. Commit is responsible for handling all back-end initiated
69 * redirects. It receives the redirect, and then broadcasts it to all
70 * stages, indicating the sequence number they should squash until,
71 * and any necessary branch misprediction information as well. It
72 * priortizes redirects by instruction's age, only broadcasting a
73 * redirect if it corresponds to an instruction that should currently
74 * be in the ROB. This is done by tracking the sequence number of the
75 * youngest instruction in the ROB, which gets updated to any
76 * squashing instruction's sequence number, and only broadcasting a
77 * redirect if it corresponds to an older instruction. Commit also
78 * supports multiple cycle squashing, to model a ROB that can only
79 * remove a certain number of instructions per cycle.
80 */
81template<class Impl>
82class DefaultCommit
83{
84 public:
85 // Typedefs from the Impl.
86 typedef typename Impl::O3CPU O3CPU;
87 typedef typename Impl::DynInstPtr DynInstPtr;
88 typedef typename Impl::CPUPol CPUPol;
89
90 typedef typename CPUPol::RenameMap RenameMap;
91 typedef typename CPUPol::ROB ROB;
92
93 typedef typename CPUPol::TimeStruct TimeStruct;
94 typedef typename CPUPol::FetchStruct FetchStruct;
95 typedef typename CPUPol::IEWStruct IEWStruct;
96 typedef typename CPUPol::RenameStruct RenameStruct;
97
98 typedef typename CPUPol::Fetch Fetch;
99 typedef typename CPUPol::IEW IEW;
100
101 typedef O3ThreadState<Impl> Thread;
102
103 /** Event class used to schedule a squash due to a trap (fault or
104 * interrupt) to happen on a specific cycle.
105 */
106 class TrapEvent : public Event {
107 private:
108 DefaultCommit<Impl> *commit;
109 ThreadID tid;
110
111 public:
112 TrapEvent(DefaultCommit<Impl> *_commit, ThreadID _tid);
113
114 void process();
115 const char *description() const;
116 };
117
118 /** Overall commit status. Used to determine if the CPU can deschedule
119 * itself due to a lack of activity.
120 */
121 enum CommitStatus{
122 Active,
123 Inactive
124 };
125
126 /** Individual thread status. */
127 enum ThreadStatus {
128 Running,
129 Idle,
130 ROBSquashing,
131 TrapPending,
132 FetchTrapPending
133 };
134
135 /** Commit policy for SMT mode. */
136 enum CommitPolicy {
137 Aggressive,
138 RoundRobin,
139 OldestReady
140 };
141
142 private:
143 /** Overall commit status. */
144 CommitStatus _status;
145 /** Next commit status, to be set at the end of the cycle. */
146 CommitStatus _nextStatus;
147 /** Per-thread status. */
148 ThreadStatus commitStatus[Impl::MaxThreads];
149 /** Commit policy used in SMT mode. */
150 CommitPolicy commitPolicy;
151
152 public:
153 /** Construct a DefaultCommit with the given parameters. */
154 DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params);
155
156 /** Returns the name of the DefaultCommit. */
157 std::string name() const;
158
159 /** Registers statistics. */
160 void regStats();
161
162 /** Sets the list of threads. */
163 void setThreads(std::vector<Thread *> &threads);
164
165 /** Sets the main time buffer pointer, used for backwards communication. */
166 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
167
168 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
169
170 /** Sets the pointer to the queue coming from rename. */
171 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
172
173 /** Sets the pointer to the queue coming from IEW. */
174 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
175
176 /** Sets the pointer to the IEW stage. */
177 void setIEWStage(IEW *iew_stage);
178
179 /** Skid buffer between rename and commit. */
180 std::queue<DynInstPtr> skidBuffer;
181
182 /** The pointer to the IEW stage. Used solely to ensure that
183 * various events (traps, interrupts, syscalls) do not occur until
184 * all stores have written back.
185 */
186 IEW *iewStage;
187
188 /** Sets pointer to list of active threads. */
189 void setActiveThreads(std::list<ThreadID> *at_ptr);
190
191 /** Sets pointer to the commited state rename map. */
192 void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
193
194 /** Sets pointer to the ROB. */
195 void setROB(ROB *rob_ptr);
196
197 /** Initializes stage by sending back the number of free entries. */
198 void initStage();
199
200 /** Initializes the draining of commit. */
201 bool drain();
202
203 /** Resumes execution after draining. */
204 void resume();
205
206 /** Completes the switch out of commit. */
207 void switchOut();
208
209 /** Takes over from another CPU's thread. */
210 void takeOverFrom();
211
212 /** Ticks the commit stage, which tries to commit instructions. */
213 void tick();
214
215 /** Handles any squashes that are sent from IEW, and adds instructions
216 * to the ROB and tries to commit instructions.
217 */
218 void commit();
219
220 /** Returns the number of free ROB entries for a specific thread. */
221 size_t numROBFreeEntries(ThreadID tid);
222
223 /** Generates an event to schedule a squash due to a trap. */
224 void generateTrapEvent(ThreadID tid);
225
226 /** Records that commit needs to initiate a squash due to an
227 * external state update through the TC.
228 */
229 void generateTCEvent(ThreadID tid);
230
231 private:
232 /** Updates the overall status of commit with the nextStatus, and
233 * tell the CPU if commit is active/inactive.
234 */
235 void updateStatus();
236
237 /** Sets the next status based on threads' statuses, which becomes the
238 * current status at the end of the cycle.
239 */
240 void setNextStatus();
241
242 /** Checks if the ROB is completed with squashing. This is for the case
243 * where the ROB can take multiple cycles to complete squashing.
244 */
245 bool robDoneSquashing();
246
247 /** Returns if any of the threads have the number of ROB entries changed
248 * on this cycle. Used to determine if the number of free ROB entries needs
249 * to be sent back to previous stages.
250 */
251 bool changedROBEntries();
252
253 /** Squashes all in flight instructions. */
254 void squashAll(ThreadID tid);
255
256 /** Handles squashing due to a trap. */
257 void squashFromTrap(ThreadID tid);
258
259 /** Handles squashing due to an TC write. */
260 void squashFromTC(ThreadID tid);
261
262 /** Handles squashing from instruction with SquashAfter set.
263 * This differs from the other squashes as it squashes following
264 * instructions instead of the current instruction and doesn't
265 * clean up various status bits about traps/tc writes pending.
266 */
267 void squashAfter(ThreadID tid, DynInstPtr &head_inst,
268 uint64_t squash_after_seq_num);
269
270 /** Handles processing an interrupt. */
271 void handleInterrupt();
272
273 /** Get fetch redirecting so we can handle an interrupt */
274 void propagateInterrupt();
275
276 /** Commits as many instructions as possible. */
277 void commitInsts();
278
279 /** Tries to commit the head ROB instruction passed in.
280 * @param head_inst The instruction to be committed.
281 */
282 bool commitHead(DynInstPtr &head_inst, unsigned inst_num);
283
284 /** Gets instructions from rename and inserts them into the ROB. */
285 void getInsts();
286
287 /** Insert all instructions from rename into skidBuffer */
288 void skidInsert();
289
290 /** Marks completed instructions using information sent from IEW. */
291 void markCompletedInsts();
292
293 /** Gets the thread to commit, based on the SMT policy. */
294 ThreadID getCommittingThread();
295
296 /** Returns the thread ID to use based on a round robin policy. */
297 ThreadID roundRobin();
298
299 /** Returns the thread ID to use based on an oldest instruction policy. */
300 ThreadID oldestReady();
301
302 public:
303 /** Reads the PC of a specific thread. */
304 TheISA::PCState pcState(ThreadID tid) { return pc[tid]; }
305
306 /** Sets the PC of a specific thread. */
307 void pcState(const TheISA::PCState &val, ThreadID tid)
308 { pc[tid] = val; }
309
310 /** Returns the PC of a specific thread. */
311 Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
312
313 /** Returns the next PC of a specific thread. */
314 Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
315
316 /** Reads the micro PC of a specific thread. */
317 Addr microPC(ThreadID tid) { return pc[tid].microPC(); }
318
319 private:
320 /** Time buffer interface. */
321 TimeBuffer<TimeStruct> *timeBuffer;
322
323 /** Wire to write information heading to previous stages. */
324 typename TimeBuffer<TimeStruct>::wire toIEW;
325
326 /** Wire to read information from IEW (for ROB). */
327 typename TimeBuffer<TimeStruct>::wire robInfoFromIEW;
328
329 TimeBuffer<FetchStruct> *fetchQueue;
330
331 typename TimeBuffer<FetchStruct>::wire fromFetch;
332
333 /** IEW instruction queue interface. */
334 TimeBuffer<IEWStruct> *iewQueue;
335
336 /** Wire to read information from IEW queue. */
337 typename TimeBuffer<IEWStruct>::wire fromIEW;
338
339 /** Rename instruction queue interface, for ROB. */
340 TimeBuffer<RenameStruct> *renameQueue;
341
342 /** Wire to read information from rename queue. */
343 typename TimeBuffer<RenameStruct>::wire fromRename;
344
345 public:
346 /** ROB interface. */
347 ROB *rob;
348
349 private:
350 /** Pointer to O3CPU. */
351 O3CPU *cpu;
352
353 /** Vector of all of the threads. */
354 std::vector<Thread *> thread;
355
356 /** Records that commit has written to the time buffer this cycle. Used for
357 * the CPU to determine if it can deschedule itself if there is no activity.
358 */
359 bool wroteToTimeBuffer;
360
361 /** Records if the number of ROB entries has changed this cycle. If it has,
362 * then the number of free entries must be re-broadcast.
363 */
364 bool changedROBNumEntries[Impl::MaxThreads];
365
366 /** A counter of how many threads are currently squashing. */
367 ThreadID squashCounter;
368
369 /** Records if a thread has to squash this cycle due to a trap. */
370 bool trapSquash[Impl::MaxThreads];
371
372 /** Records if a thread has to squash this cycle due to an XC write. */
373 bool tcSquash[Impl::MaxThreads];
374
375 /** Priority List used for Commit Policy */
376 std::list<ThreadID> priority_list;
377
| 1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#ifndef __CPU_O3_COMMIT_HH__
45#define __CPU_O3_COMMIT_HH__
46
47#include <queue>
48
49#include "base/statistics.hh"
50#include "cpu/exetrace.hh"
51#include "cpu/inst_seq.hh"
52#include "cpu/timebuf.hh"
53
54struct DerivO3CPUParams;
55
56template <class>
57struct O3ThreadState;
58
59/**
60 * DefaultCommit handles single threaded and SMT commit. Its width is
61 * specified by the parameters; each cycle it tries to commit that
62 * many instructions. The SMT policy decides which thread it tries to
63 * commit instructions from. Non- speculative instructions must reach
64 * the head of the ROB before they are ready to execute; once they
65 * reach the head, commit will broadcast the instruction's sequence
66 * number to the previous stages so that they can issue/ execute the
67 * instruction. Only one non-speculative instruction is handled per
68 * cycle. Commit is responsible for handling all back-end initiated
69 * redirects. It receives the redirect, and then broadcasts it to all
70 * stages, indicating the sequence number they should squash until,
71 * and any necessary branch misprediction information as well. It
72 * priortizes redirects by instruction's age, only broadcasting a
73 * redirect if it corresponds to an instruction that should currently
74 * be in the ROB. This is done by tracking the sequence number of the
75 * youngest instruction in the ROB, which gets updated to any
76 * squashing instruction's sequence number, and only broadcasting a
77 * redirect if it corresponds to an older instruction. Commit also
78 * supports multiple cycle squashing, to model a ROB that can only
79 * remove a certain number of instructions per cycle.
80 */
81template<class Impl>
82class DefaultCommit
83{
84 public:
85 // Typedefs from the Impl.
86 typedef typename Impl::O3CPU O3CPU;
87 typedef typename Impl::DynInstPtr DynInstPtr;
88 typedef typename Impl::CPUPol CPUPol;
89
90 typedef typename CPUPol::RenameMap RenameMap;
91 typedef typename CPUPol::ROB ROB;
92
93 typedef typename CPUPol::TimeStruct TimeStruct;
94 typedef typename CPUPol::FetchStruct FetchStruct;
95 typedef typename CPUPol::IEWStruct IEWStruct;
96 typedef typename CPUPol::RenameStruct RenameStruct;
97
98 typedef typename CPUPol::Fetch Fetch;
99 typedef typename CPUPol::IEW IEW;
100
101 typedef O3ThreadState<Impl> Thread;
102
103 /** Event class used to schedule a squash due to a trap (fault or
104 * interrupt) to happen on a specific cycle.
105 */
106 class TrapEvent : public Event {
107 private:
108 DefaultCommit<Impl> *commit;
109 ThreadID tid;
110
111 public:
112 TrapEvent(DefaultCommit<Impl> *_commit, ThreadID _tid);
113
114 void process();
115 const char *description() const;
116 };
117
118 /** Overall commit status. Used to determine if the CPU can deschedule
119 * itself due to a lack of activity.
120 */
121 enum CommitStatus{
122 Active,
123 Inactive
124 };
125
126 /** Individual thread status. */
127 enum ThreadStatus {
128 Running,
129 Idle,
130 ROBSquashing,
131 TrapPending,
132 FetchTrapPending
133 };
134
135 /** Commit policy for SMT mode. */
136 enum CommitPolicy {
137 Aggressive,
138 RoundRobin,
139 OldestReady
140 };
141
142 private:
143 /** Overall commit status. */
144 CommitStatus _status;
145 /** Next commit status, to be set at the end of the cycle. */
146 CommitStatus _nextStatus;
147 /** Per-thread status. */
148 ThreadStatus commitStatus[Impl::MaxThreads];
149 /** Commit policy used in SMT mode. */
150 CommitPolicy commitPolicy;
151
152 public:
153 /** Construct a DefaultCommit with the given parameters. */
154 DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params);
155
156 /** Returns the name of the DefaultCommit. */
157 std::string name() const;
158
159 /** Registers statistics. */
160 void regStats();
161
162 /** Sets the list of threads. */
163 void setThreads(std::vector<Thread *> &threads);
164
165 /** Sets the main time buffer pointer, used for backwards communication. */
166 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
167
168 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
169
170 /** Sets the pointer to the queue coming from rename. */
171 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
172
173 /** Sets the pointer to the queue coming from IEW. */
174 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
175
176 /** Sets the pointer to the IEW stage. */
177 void setIEWStage(IEW *iew_stage);
178
179 /** Skid buffer between rename and commit. */
180 std::queue<DynInstPtr> skidBuffer;
181
182 /** The pointer to the IEW stage. Used solely to ensure that
183 * various events (traps, interrupts, syscalls) do not occur until
184 * all stores have written back.
185 */
186 IEW *iewStage;
187
188 /** Sets pointer to list of active threads. */
189 void setActiveThreads(std::list<ThreadID> *at_ptr);
190
191 /** Sets pointer to the commited state rename map. */
192 void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
193
194 /** Sets pointer to the ROB. */
195 void setROB(ROB *rob_ptr);
196
197 /** Initializes stage by sending back the number of free entries. */
198 void initStage();
199
200 /** Initializes the draining of commit. */
201 bool drain();
202
203 /** Resumes execution after draining. */
204 void resume();
205
206 /** Completes the switch out of commit. */
207 void switchOut();
208
209 /** Takes over from another CPU's thread. */
210 void takeOverFrom();
211
212 /** Ticks the commit stage, which tries to commit instructions. */
213 void tick();
214
215 /** Handles any squashes that are sent from IEW, and adds instructions
216 * to the ROB and tries to commit instructions.
217 */
218 void commit();
219
220 /** Returns the number of free ROB entries for a specific thread. */
221 size_t numROBFreeEntries(ThreadID tid);
222
223 /** Generates an event to schedule a squash due to a trap. */
224 void generateTrapEvent(ThreadID tid);
225
226 /** Records that commit needs to initiate a squash due to an
227 * external state update through the TC.
228 */
229 void generateTCEvent(ThreadID tid);
230
231 private:
232 /** Updates the overall status of commit with the nextStatus, and
233 * tell the CPU if commit is active/inactive.
234 */
235 void updateStatus();
236
237 /** Sets the next status based on threads' statuses, which becomes the
238 * current status at the end of the cycle.
239 */
240 void setNextStatus();
241
242 /** Checks if the ROB is completed with squashing. This is for the case
243 * where the ROB can take multiple cycles to complete squashing.
244 */
245 bool robDoneSquashing();
246
247 /** Returns if any of the threads have the number of ROB entries changed
248 * on this cycle. Used to determine if the number of free ROB entries needs
249 * to be sent back to previous stages.
250 */
251 bool changedROBEntries();
252
253 /** Squashes all in flight instructions. */
254 void squashAll(ThreadID tid);
255
256 /** Handles squashing due to a trap. */
257 void squashFromTrap(ThreadID tid);
258
259 /** Handles squashing due to an TC write. */
260 void squashFromTC(ThreadID tid);
261
262 /** Handles squashing from instruction with SquashAfter set.
263 * This differs from the other squashes as it squashes following
264 * instructions instead of the current instruction and doesn't
265 * clean up various status bits about traps/tc writes pending.
266 */
267 void squashAfter(ThreadID tid, DynInstPtr &head_inst,
268 uint64_t squash_after_seq_num);
269
270 /** Handles processing an interrupt. */
271 void handleInterrupt();
272
273 /** Get fetch redirecting so we can handle an interrupt */
274 void propagateInterrupt();
275
276 /** Commits as many instructions as possible. */
277 void commitInsts();
278
279 /** Tries to commit the head ROB instruction passed in.
280 * @param head_inst The instruction to be committed.
281 */
282 bool commitHead(DynInstPtr &head_inst, unsigned inst_num);
283
284 /** Gets instructions from rename and inserts them into the ROB. */
285 void getInsts();
286
287 /** Insert all instructions from rename into skidBuffer */
288 void skidInsert();
289
290 /** Marks completed instructions using information sent from IEW. */
291 void markCompletedInsts();
292
293 /** Gets the thread to commit, based on the SMT policy. */
294 ThreadID getCommittingThread();
295
296 /** Returns the thread ID to use based on a round robin policy. */
297 ThreadID roundRobin();
298
299 /** Returns the thread ID to use based on an oldest instruction policy. */
300 ThreadID oldestReady();
301
302 public:
303 /** Reads the PC of a specific thread. */
304 TheISA::PCState pcState(ThreadID tid) { return pc[tid]; }
305
306 /** Sets the PC of a specific thread. */
307 void pcState(const TheISA::PCState &val, ThreadID tid)
308 { pc[tid] = val; }
309
310 /** Returns the PC of a specific thread. */
311 Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
312
313 /** Returns the next PC of a specific thread. */
314 Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
315
316 /** Reads the micro PC of a specific thread. */
317 Addr microPC(ThreadID tid) { return pc[tid].microPC(); }
318
319 private:
320 /** Time buffer interface. */
321 TimeBuffer<TimeStruct> *timeBuffer;
322
323 /** Wire to write information heading to previous stages. */
324 typename TimeBuffer<TimeStruct>::wire toIEW;
325
326 /** Wire to read information from IEW (for ROB). */
327 typename TimeBuffer<TimeStruct>::wire robInfoFromIEW;
328
329 TimeBuffer<FetchStruct> *fetchQueue;
330
331 typename TimeBuffer<FetchStruct>::wire fromFetch;
332
333 /** IEW instruction queue interface. */
334 TimeBuffer<IEWStruct> *iewQueue;
335
336 /** Wire to read information from IEW queue. */
337 typename TimeBuffer<IEWStruct>::wire fromIEW;
338
339 /** Rename instruction queue interface, for ROB. */
340 TimeBuffer<RenameStruct> *renameQueue;
341
342 /** Wire to read information from rename queue. */
343 typename TimeBuffer<RenameStruct>::wire fromRename;
344
345 public:
346 /** ROB interface. */
347 ROB *rob;
348
349 private:
350 /** Pointer to O3CPU. */
351 O3CPU *cpu;
352
353 /** Vector of all of the threads. */
354 std::vector<Thread *> thread;
355
356 /** Records that commit has written to the time buffer this cycle. Used for
357 * the CPU to determine if it can deschedule itself if there is no activity.
358 */
359 bool wroteToTimeBuffer;
360
361 /** Records if the number of ROB entries has changed this cycle. If it has,
362 * then the number of free entries must be re-broadcast.
363 */
364 bool changedROBNumEntries[Impl::MaxThreads];
365
366 /** A counter of how many threads are currently squashing. */
367 ThreadID squashCounter;
368
369 /** Records if a thread has to squash this cycle due to a trap. */
370 bool trapSquash[Impl::MaxThreads];
371
372 /** Records if a thread has to squash this cycle due to an XC write. */
373 bool tcSquash[Impl::MaxThreads];
374
375 /** Priority List used for Commit Policy */
376 std::list<ThreadID> priority_list;
377
|