1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_COMMIT_HH__
33#define __CPU_O3_COMMIT_HH__
34
35#include "base/statistics.hh"
| 1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 * Korey Sewell
30 */
31
32#ifndef __CPU_O3_COMMIT_HH__
33#define __CPU_O3_COMMIT_HH__
34
35#include "base/statistics.hh"
|
37#include "cpu/exetrace.hh"
38#include "cpu/inst_seq.hh"
39
40class DerivO3CPUParams;
41
42template <class>
43class O3ThreadState;
44
45/**
46 * DefaultCommit handles single threaded and SMT commit. Its width is
47 * specified by the parameters; each cycle it tries to commit that
48 * many instructions. The SMT policy decides which thread it tries to
49 * commit instructions from. Non- speculative instructions must reach
50 * the head of the ROB before they are ready to execute; once they
51 * reach the head, commit will broadcast the instruction's sequence
52 * number to the previous stages so that they can issue/ execute the
53 * instruction. Only one non-speculative instruction is handled per
54 * cycle. Commit is responsible for handling all back-end initiated
55 * redirects. It receives the redirect, and then broadcasts it to all
56 * stages, indicating the sequence number they should squash until,
57 * and any necessary branch misprediction information as well. It
58 * priortizes redirects by instruction's age, only broadcasting a
59 * redirect if it corresponds to an instruction that should currently
60 * be in the ROB. This is done by tracking the sequence number of the
61 * youngest instruction in the ROB, which gets updated to any
62 * squashing instruction's sequence number, and only broadcasting a
63 * redirect if it corresponds to an older instruction. Commit also
64 * supports multiple cycle squashing, to model a ROB that can only
65 * remove a certain number of instructions per cycle.
66 */
67template<class Impl>
68class DefaultCommit
69{
70 public:
71 // Typedefs from the Impl.
72 typedef typename Impl::O3CPU O3CPU;
73 typedef typename Impl::DynInstPtr DynInstPtr;
74 typedef typename Impl::CPUPol CPUPol;
75
76 typedef typename CPUPol::RenameMap RenameMap;
77 typedef typename CPUPol::ROB ROB;
78
79 typedef typename CPUPol::TimeStruct TimeStruct;
80 typedef typename CPUPol::FetchStruct FetchStruct;
81 typedef typename CPUPol::IEWStruct IEWStruct;
82 typedef typename CPUPol::RenameStruct RenameStruct;
83
84 typedef typename CPUPol::Fetch Fetch;
85 typedef typename CPUPol::IEW IEW;
86
87 typedef O3ThreadState<Impl> Thread;
88
89 /** Event class used to schedule a squash due to a trap (fault or
90 * interrupt) to happen on a specific cycle.
91 */
92 class TrapEvent : public Event {
93 private:
94 DefaultCommit<Impl> *commit;
95 ThreadID tid;
96
97 public:
98 TrapEvent(DefaultCommit<Impl> *_commit, ThreadID _tid);
99
100 void process();
101 const char *description() const;
102 };
103
104 /** Overall commit status. Used to determine if the CPU can deschedule
105 * itself due to a lack of activity.
106 */
107 enum CommitStatus{
108 Active,
109 Inactive
110 };
111
112 /** Individual thread status. */
113 enum ThreadStatus {
114 Running,
115 Idle,
116 ROBSquashing,
117 TrapPending,
118 FetchTrapPending
119 };
120
121 /** Commit policy for SMT mode. */
122 enum CommitPolicy {
123 Aggressive,
124 RoundRobin,
125 OldestReady
126 };
127
128 private:
129 /** Overall commit status. */
130 CommitStatus _status;
131 /** Next commit status, to be set at the end of the cycle. */
132 CommitStatus _nextStatus;
133 /** Per-thread status. */
134 ThreadStatus commitStatus[Impl::MaxThreads];
135 /** Commit policy used in SMT mode. */
136 CommitPolicy commitPolicy;
137
138 public:
139 /** Construct a DefaultCommit with the given parameters. */
140 DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params);
141
142 /** Returns the name of the DefaultCommit. */
143 std::string name() const;
144
145 /** Registers statistics. */
146 void regStats();
147
148 /** Sets the list of threads. */
149 void setThreads(std::vector<Thread *> &threads);
150
151 /** Sets the main time buffer pointer, used for backwards communication. */
152 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
153
154 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
155
156 /** Sets the pointer to the queue coming from rename. */
157 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
158
159 /** Sets the pointer to the queue coming from IEW. */
160 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
161
162 /** Sets the pointer to the IEW stage. */
163 void setIEWStage(IEW *iew_stage);
164
165 /** Skid buffer between rename and commit. */
166 std::queue<DynInstPtr> skidBuffer;
167
168 /** The pointer to the IEW stage. Used solely to ensure that
169 * various events (traps, interrupts, syscalls) do not occur until
170 * all stores have written back.
171 */
172 IEW *iewStage;
173
174 /** Sets pointer to list of active threads. */
175 void setActiveThreads(std::list<ThreadID> *at_ptr);
176
177 /** Sets pointer to the commited state rename map. */
178 void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
179
180 /** Sets pointer to the ROB. */
181 void setROB(ROB *rob_ptr);
182
183 /** Initializes stage by sending back the number of free entries. */
184 void initStage();
185
186 /** Initializes the draining of commit. */
187 bool drain();
188
189 /** Resumes execution after draining. */
190 void resume();
191
192 /** Completes the switch out of commit. */
193 void switchOut();
194
195 /** Takes over from another CPU's thread. */
196 void takeOverFrom();
197
198 /** Ticks the commit stage, which tries to commit instructions. */
199 void tick();
200
201 /** Handles any squashes that are sent from IEW, and adds instructions
202 * to the ROB and tries to commit instructions.
203 */
204 void commit();
205
206 /** Returns the number of free ROB entries for a specific thread. */
207 size_t numROBFreeEntries(ThreadID tid);
208
209 /** Generates an event to schedule a squash due to a trap. */
210 void generateTrapEvent(ThreadID tid);
211
212 /** Records that commit needs to initiate a squash due to an
213 * external state update through the TC.
214 */
215 void generateTCEvent(ThreadID tid);
216
217 private:
218 /** Updates the overall status of commit with the nextStatus, and
219 * tell the CPU if commit is active/inactive.
220 */
221 void updateStatus();
222
223 /** Sets the next status based on threads' statuses, which becomes the
224 * current status at the end of the cycle.
225 */
226 void setNextStatus();
227
228 /** Checks if the ROB is completed with squashing. This is for the case
229 * where the ROB can take multiple cycles to complete squashing.
230 */
231 bool robDoneSquashing();
232
233 /** Returns if any of the threads have the number of ROB entries changed
234 * on this cycle. Used to determine if the number of free ROB entries needs
235 * to be sent back to previous stages.
236 */
237 bool changedROBEntries();
238
239 /** Squashes all in flight instructions. */
240 void squashAll(ThreadID tid);
241
242 /** Handles squashing due to a trap. */
243 void squashFromTrap(ThreadID tid);
244
245 /** Handles squashing due to an TC write. */
246 void squashFromTC(ThreadID tid);
247
248 /** Handles squashing from instruction with SquashAfter set.
249 * This differs from the other squashes as it squashes following
250 * instructions instead of the current instruction and doesn't
251 * clean up various status bits about traps/tc writes pending.
252 */
253 void squashAfter(ThreadID tid, uint64_t squash_after_seq_num);
254
255#if FULL_SYSTEM
256 /** Handles processing an interrupt. */
257 void handleInterrupt();
258#endif // FULL_SYSTEM
259
260 /** Commits as many instructions as possible. */
261 void commitInsts();
262
263 /** Tries to commit the head ROB instruction passed in.
264 * @param head_inst The instruction to be committed.
265 */
266 bool commitHead(DynInstPtr &head_inst, unsigned inst_num);
267
268 /** Gets instructions from rename and inserts them into the ROB. */
269 void getInsts();
270
271 /** Insert all instructions from rename into skidBuffer */
272 void skidInsert();
273
274 /** Marks completed instructions using information sent from IEW. */
275 void markCompletedInsts();
276
277 /** Gets the thread to commit, based on the SMT policy. */
278 ThreadID getCommittingThread();
279
280 /** Returns the thread ID to use based on a round robin policy. */
281 ThreadID roundRobin();
282
283 /** Returns the thread ID to use based on an oldest instruction policy. */
284 ThreadID oldestReady();
285
286 public:
287 /** Reads the PC of a specific thread. */
288 TheISA::PCState pcState(ThreadID tid) { return pc[tid]; }
289
290 /** Sets the PC of a specific thread. */
291 void pcState(const TheISA::PCState &val, ThreadID tid)
292 { pc[tid] = val; }
293
294 /** Returns the PC of a specific thread. */
295 Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
296
297 /** Returns the next PC of a specific thread. */
298 Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
299
300 /** Reads the micro PC of a specific thread. */
301 Addr microPC(ThreadID tid) { return pc[tid].microPC(); }
302
303 private:
304 /** Time buffer interface. */
305 TimeBuffer<TimeStruct> *timeBuffer;
306
307 /** Wire to write information heading to previous stages. */
308 typename TimeBuffer<TimeStruct>::wire toIEW;
309
310 /** Wire to read information from IEW (for ROB). */
311 typename TimeBuffer<TimeStruct>::wire robInfoFromIEW;
312
313 TimeBuffer<FetchStruct> *fetchQueue;
314
315 typename TimeBuffer<FetchStruct>::wire fromFetch;
316
317 /** IEW instruction queue interface. */
318 TimeBuffer<IEWStruct> *iewQueue;
319
320 /** Wire to read information from IEW queue. */
321 typename TimeBuffer<IEWStruct>::wire fromIEW;
322
323 /** Rename instruction queue interface, for ROB. */
324 TimeBuffer<RenameStruct> *renameQueue;
325
326 /** Wire to read information from rename queue. */
327 typename TimeBuffer<RenameStruct>::wire fromRename;
328
329 public:
330 /** ROB interface. */
331 ROB *rob;
332
333 private:
334 /** Pointer to O3CPU. */
335 O3CPU *cpu;
336
337 /** Vector of all of the threads. */
338 std::vector<Thread *> thread;
339
340 /** Records that commit has written to the time buffer this cycle. Used for
341 * the CPU to determine if it can deschedule itself if there is no activity.
342 */
343 bool wroteToTimeBuffer;
344
345 /** Records if the number of ROB entries has changed this cycle. If it has,
346 * then the number of free entries must be re-broadcast.
347 */
348 bool changedROBNumEntries[Impl::MaxThreads];
349
350 /** A counter of how many threads are currently squashing. */
351 ThreadID squashCounter;
352
353 /** Records if a thread has to squash this cycle due to a trap. */
354 bool trapSquash[Impl::MaxThreads];
355
356 /** Records if a thread has to squash this cycle due to an XC write. */
357 bool tcSquash[Impl::MaxThreads];
358
359 /** Priority List used for Commit Policy */
360 std::list<ThreadID> priority_list;
361
362 /** IEW to Commit delay, in ticks. */
363 unsigned iewToCommitDelay;
364
365 /** Commit to IEW delay, in ticks. */
366 unsigned commitToIEWDelay;
367
368 /** Rename to ROB delay, in ticks. */
369 unsigned renameToROBDelay;
370
371 unsigned fetchToCommitDelay;
372
373 /** Rename width, in instructions. Used so ROB knows how many
374 * instructions to get from the rename instruction queue.
375 */
376 unsigned renameWidth;
377
378 /** Commit width, in instructions. */
379 unsigned commitWidth;
380
381 /** Number of Reorder Buffers */
382 unsigned numRobs;
383
384 /** Number of Active Threads */
385 ThreadID numThreads;
386
387 /** Is a drain pending. */
388 bool drainPending;
389
390 /** Is commit switched out. */
391 bool switchedOut;
392
393 /** The latency to handle a trap. Used when scheduling trap
394 * squash event.
395 */
396 Tick trapLatency;
397
398 /** The interrupt fault. */
399 Fault interrupt;
400
401 /** The commit PC state of each thread. Refers to the instruction that
402 * is currently being processed/committed.
403 */
404 TheISA::PCState pc[Impl::MaxThreads];
405
406 /** The sequence number of the youngest valid instruction in the ROB. */
407 InstSeqNum youngestSeqNum[Impl::MaxThreads];
408
409 /** Records if there is a trap currently in flight. */
410 bool trapInFlight[Impl::MaxThreads];
411
412 /** Records if there were any stores committed this cycle. */
413 bool committedStores[Impl::MaxThreads];
414
415 /** Records if commit should check if the ROB is truly empty (see
416 commit_impl.hh). */
417 bool checkEmptyROB[Impl::MaxThreads];
418
419 /** Pointer to the list of active threads. */
420 std::list<ThreadID> *activeThreads;
421
422 /** Rename map interface. */
423 RenameMap *renameMap[Impl::MaxThreads];
424
425 /** Updates commit stats based on this instruction. */
426 void updateComInstStats(DynInstPtr &inst);
427
428 /** Stat for the total number of committed instructions. */
429 Stats::Scalar commitCommittedInsts;
430 /** Stat for the total number of squashed instructions discarded by commit.
431 */
432 Stats::Scalar commitSquashedInsts;
433 /** Stat for the total number of times commit is told to squash.
434 * @todo: Actually increment this stat.
435 */
436 Stats::Scalar commitSquashEvents;
437 /** Stat for the total number of times commit has had to stall due to a non-
438 * speculative instruction reaching the head of the ROB.
439 */
440 Stats::Scalar commitNonSpecStalls;
441 /** Stat for the total number of branch mispredicts that caused a squash. */
442 Stats::Scalar branchMispredicts;
443 /** Distribution of the number of committed instructions each cycle. */
444 Stats::Distribution numCommittedDist;
445
446 /** Total number of instructions committed. */
447 Stats::Vector statComInst;
448 /** Total number of software prefetches committed. */
449 Stats::Vector statComSwp;
450 /** Stat for the total number of committed memory references. */
451 Stats::Vector statComRefs;
452 /** Stat for the total number of committed loads. */
453 Stats::Vector statComLoads;
454 /** Total number of committed memory barriers. */
455 Stats::Vector statComMembars;
456 /** Total number of committed branches. */
457 Stats::Vector statComBranches;
458
459 /** Number of cycles where the commit bandwidth limit is reached. */
460 Stats::Scalar commitEligibleSamples;
461 /** Number of instructions not committed due to bandwidth limits. */
462 Stats::Vector commitEligible;
463};
464
465#endif // __CPU_O3_COMMIT_HH__
| 37#include "cpu/exetrace.hh"
38#include "cpu/inst_seq.hh"
39
40class DerivO3CPUParams;
41
42template <class>
43class O3ThreadState;
44
45/**
46 * DefaultCommit handles single threaded and SMT commit. Its width is
47 * specified by the parameters; each cycle it tries to commit that
48 * many instructions. The SMT policy decides which thread it tries to
49 * commit instructions from. Non- speculative instructions must reach
50 * the head of the ROB before they are ready to execute; once they
51 * reach the head, commit will broadcast the instruction's sequence
52 * number to the previous stages so that they can issue/ execute the
53 * instruction. Only one non-speculative instruction is handled per
54 * cycle. Commit is responsible for handling all back-end initiated
55 * redirects. It receives the redirect, and then broadcasts it to all
56 * stages, indicating the sequence number they should squash until,
57 * and any necessary branch misprediction information as well. It
58 * priortizes redirects by instruction's age, only broadcasting a
59 * redirect if it corresponds to an instruction that should currently
60 * be in the ROB. This is done by tracking the sequence number of the
61 * youngest instruction in the ROB, which gets updated to any
62 * squashing instruction's sequence number, and only broadcasting a
63 * redirect if it corresponds to an older instruction. Commit also
64 * supports multiple cycle squashing, to model a ROB that can only
65 * remove a certain number of instructions per cycle.
66 */
67template<class Impl>
68class DefaultCommit
69{
70 public:
71 // Typedefs from the Impl.
72 typedef typename Impl::O3CPU O3CPU;
73 typedef typename Impl::DynInstPtr DynInstPtr;
74 typedef typename Impl::CPUPol CPUPol;
75
76 typedef typename CPUPol::RenameMap RenameMap;
77 typedef typename CPUPol::ROB ROB;
78
79 typedef typename CPUPol::TimeStruct TimeStruct;
80 typedef typename CPUPol::FetchStruct FetchStruct;
81 typedef typename CPUPol::IEWStruct IEWStruct;
82 typedef typename CPUPol::RenameStruct RenameStruct;
83
84 typedef typename CPUPol::Fetch Fetch;
85 typedef typename CPUPol::IEW IEW;
86
87 typedef O3ThreadState<Impl> Thread;
88
89 /** Event class used to schedule a squash due to a trap (fault or
90 * interrupt) to happen on a specific cycle.
91 */
92 class TrapEvent : public Event {
93 private:
94 DefaultCommit<Impl> *commit;
95 ThreadID tid;
96
97 public:
98 TrapEvent(DefaultCommit<Impl> *_commit, ThreadID _tid);
99
100 void process();
101 const char *description() const;
102 };
103
104 /** Overall commit status. Used to determine if the CPU can deschedule
105 * itself due to a lack of activity.
106 */
107 enum CommitStatus{
108 Active,
109 Inactive
110 };
111
112 /** Individual thread status. */
113 enum ThreadStatus {
114 Running,
115 Idle,
116 ROBSquashing,
117 TrapPending,
118 FetchTrapPending
119 };
120
121 /** Commit policy for SMT mode. */
122 enum CommitPolicy {
123 Aggressive,
124 RoundRobin,
125 OldestReady
126 };
127
128 private:
129 /** Overall commit status. */
130 CommitStatus _status;
131 /** Next commit status, to be set at the end of the cycle. */
132 CommitStatus _nextStatus;
133 /** Per-thread status. */
134 ThreadStatus commitStatus[Impl::MaxThreads];
135 /** Commit policy used in SMT mode. */
136 CommitPolicy commitPolicy;
137
138 public:
139 /** Construct a DefaultCommit with the given parameters. */
140 DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params);
141
142 /** Returns the name of the DefaultCommit. */
143 std::string name() const;
144
145 /** Registers statistics. */
146 void regStats();
147
148 /** Sets the list of threads. */
149 void setThreads(std::vector<Thread *> &threads);
150
151 /** Sets the main time buffer pointer, used for backwards communication. */
152 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
153
154 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
155
156 /** Sets the pointer to the queue coming from rename. */
157 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
158
159 /** Sets the pointer to the queue coming from IEW. */
160 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
161
162 /** Sets the pointer to the IEW stage. */
163 void setIEWStage(IEW *iew_stage);
164
165 /** Skid buffer between rename and commit. */
166 std::queue<DynInstPtr> skidBuffer;
167
168 /** The pointer to the IEW stage. Used solely to ensure that
169 * various events (traps, interrupts, syscalls) do not occur until
170 * all stores have written back.
171 */
172 IEW *iewStage;
173
174 /** Sets pointer to list of active threads. */
175 void setActiveThreads(std::list<ThreadID> *at_ptr);
176
177 /** Sets pointer to the commited state rename map. */
178 void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
179
180 /** Sets pointer to the ROB. */
181 void setROB(ROB *rob_ptr);
182
183 /** Initializes stage by sending back the number of free entries. */
184 void initStage();
185
186 /** Initializes the draining of commit. */
187 bool drain();
188
189 /** Resumes execution after draining. */
190 void resume();
191
192 /** Completes the switch out of commit. */
193 void switchOut();
194
195 /** Takes over from another CPU's thread. */
196 void takeOverFrom();
197
198 /** Ticks the commit stage, which tries to commit instructions. */
199 void tick();
200
201 /** Handles any squashes that are sent from IEW, and adds instructions
202 * to the ROB and tries to commit instructions.
203 */
204 void commit();
205
206 /** Returns the number of free ROB entries for a specific thread. */
207 size_t numROBFreeEntries(ThreadID tid);
208
209 /** Generates an event to schedule a squash due to a trap. */
210 void generateTrapEvent(ThreadID tid);
211
212 /** Records that commit needs to initiate a squash due to an
213 * external state update through the TC.
214 */
215 void generateTCEvent(ThreadID tid);
216
217 private:
218 /** Updates the overall status of commit with the nextStatus, and
219 * tell the CPU if commit is active/inactive.
220 */
221 void updateStatus();
222
223 /** Sets the next status based on threads' statuses, which becomes the
224 * current status at the end of the cycle.
225 */
226 void setNextStatus();
227
228 /** Checks if the ROB is completed with squashing. This is for the case
229 * where the ROB can take multiple cycles to complete squashing.
230 */
231 bool robDoneSquashing();
232
233 /** Returns if any of the threads have the number of ROB entries changed
234 * on this cycle. Used to determine if the number of free ROB entries needs
235 * to be sent back to previous stages.
236 */
237 bool changedROBEntries();
238
239 /** Squashes all in flight instructions. */
240 void squashAll(ThreadID tid);
241
242 /** Handles squashing due to a trap. */
243 void squashFromTrap(ThreadID tid);
244
245 /** Handles squashing due to an TC write. */
246 void squashFromTC(ThreadID tid);
247
248 /** Handles squashing from instruction with SquashAfter set.
249 * This differs from the other squashes as it squashes following
250 * instructions instead of the current instruction and doesn't
251 * clean up various status bits about traps/tc writes pending.
252 */
253 void squashAfter(ThreadID tid, uint64_t squash_after_seq_num);
254
255#if FULL_SYSTEM
256 /** Handles processing an interrupt. */
257 void handleInterrupt();
258#endif // FULL_SYSTEM
259
260 /** Commits as many instructions as possible. */
261 void commitInsts();
262
263 /** Tries to commit the head ROB instruction passed in.
264 * @param head_inst The instruction to be committed.
265 */
266 bool commitHead(DynInstPtr &head_inst, unsigned inst_num);
267
268 /** Gets instructions from rename and inserts them into the ROB. */
269 void getInsts();
270
271 /** Insert all instructions from rename into skidBuffer */
272 void skidInsert();
273
274 /** Marks completed instructions using information sent from IEW. */
275 void markCompletedInsts();
276
277 /** Gets the thread to commit, based on the SMT policy. */
278 ThreadID getCommittingThread();
279
280 /** Returns the thread ID to use based on a round robin policy. */
281 ThreadID roundRobin();
282
283 /** Returns the thread ID to use based on an oldest instruction policy. */
284 ThreadID oldestReady();
285
286 public:
287 /** Reads the PC of a specific thread. */
288 TheISA::PCState pcState(ThreadID tid) { return pc[tid]; }
289
290 /** Sets the PC of a specific thread. */
291 void pcState(const TheISA::PCState &val, ThreadID tid)
292 { pc[tid] = val; }
293
294 /** Returns the PC of a specific thread. */
295 Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
296
297 /** Returns the next PC of a specific thread. */
298 Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
299
300 /** Reads the micro PC of a specific thread. */
301 Addr microPC(ThreadID tid) { return pc[tid].microPC(); }
302
303 private:
304 /** Time buffer interface. */
305 TimeBuffer<TimeStruct> *timeBuffer;
306
307 /** Wire to write information heading to previous stages. */
308 typename TimeBuffer<TimeStruct>::wire toIEW;
309
310 /** Wire to read information from IEW (for ROB). */
311 typename TimeBuffer<TimeStruct>::wire robInfoFromIEW;
312
313 TimeBuffer<FetchStruct> *fetchQueue;
314
315 typename TimeBuffer<FetchStruct>::wire fromFetch;
316
317 /** IEW instruction queue interface. */
318 TimeBuffer<IEWStruct> *iewQueue;
319
320 /** Wire to read information from IEW queue. */
321 typename TimeBuffer<IEWStruct>::wire fromIEW;
322
323 /** Rename instruction queue interface, for ROB. */
324 TimeBuffer<RenameStruct> *renameQueue;
325
326 /** Wire to read information from rename queue. */
327 typename TimeBuffer<RenameStruct>::wire fromRename;
328
329 public:
330 /** ROB interface. */
331 ROB *rob;
332
333 private:
334 /** Pointer to O3CPU. */
335 O3CPU *cpu;
336
337 /** Vector of all of the threads. */
338 std::vector<Thread *> thread;
339
340 /** Records that commit has written to the time buffer this cycle. Used for
341 * the CPU to determine if it can deschedule itself if there is no activity.
342 */
343 bool wroteToTimeBuffer;
344
345 /** Records if the number of ROB entries has changed this cycle. If it has,
346 * then the number of free entries must be re-broadcast.
347 */
348 bool changedROBNumEntries[Impl::MaxThreads];
349
350 /** A counter of how many threads are currently squashing. */
351 ThreadID squashCounter;
352
353 /** Records if a thread has to squash this cycle due to a trap. */
354 bool trapSquash[Impl::MaxThreads];
355
356 /** Records if a thread has to squash this cycle due to an XC write. */
357 bool tcSquash[Impl::MaxThreads];
358
359 /** Priority List used for Commit Policy */
360 std::list<ThreadID> priority_list;
361
362 /** IEW to Commit delay, in ticks. */
363 unsigned iewToCommitDelay;
364
365 /** Commit to IEW delay, in ticks. */
366 unsigned commitToIEWDelay;
367
368 /** Rename to ROB delay, in ticks. */
369 unsigned renameToROBDelay;
370
371 unsigned fetchToCommitDelay;
372
373 /** Rename width, in instructions. Used so ROB knows how many
374 * instructions to get from the rename instruction queue.
375 */
376 unsigned renameWidth;
377
378 /** Commit width, in instructions. */
379 unsigned commitWidth;
380
381 /** Number of Reorder Buffers */
382 unsigned numRobs;
383
384 /** Number of Active Threads */
385 ThreadID numThreads;
386
387 /** Is a drain pending. */
388 bool drainPending;
389
390 /** Is commit switched out. */
391 bool switchedOut;
392
393 /** The latency to handle a trap. Used when scheduling trap
394 * squash event.
395 */
396 Tick trapLatency;
397
398 /** The interrupt fault. */
399 Fault interrupt;
400
401 /** The commit PC state of each thread. Refers to the instruction that
402 * is currently being processed/committed.
403 */
404 TheISA::PCState pc[Impl::MaxThreads];
405
406 /** The sequence number of the youngest valid instruction in the ROB. */
407 InstSeqNum youngestSeqNum[Impl::MaxThreads];
408
409 /** Records if there is a trap currently in flight. */
410 bool trapInFlight[Impl::MaxThreads];
411
412 /** Records if there were any stores committed this cycle. */
413 bool committedStores[Impl::MaxThreads];
414
415 /** Records if commit should check if the ROB is truly empty (see
416 commit_impl.hh). */
417 bool checkEmptyROB[Impl::MaxThreads];
418
419 /** Pointer to the list of active threads. */
420 std::list<ThreadID> *activeThreads;
421
422 /** Rename map interface. */
423 RenameMap *renameMap[Impl::MaxThreads];
424
425 /** Updates commit stats based on this instruction. */
426 void updateComInstStats(DynInstPtr &inst);
427
428 /** Stat for the total number of committed instructions. */
429 Stats::Scalar commitCommittedInsts;
430 /** Stat for the total number of squashed instructions discarded by commit.
431 */
432 Stats::Scalar commitSquashedInsts;
433 /** Stat for the total number of times commit is told to squash.
434 * @todo: Actually increment this stat.
435 */
436 Stats::Scalar commitSquashEvents;
437 /** Stat for the total number of times commit has had to stall due to a non-
438 * speculative instruction reaching the head of the ROB.
439 */
440 Stats::Scalar commitNonSpecStalls;
441 /** Stat for the total number of branch mispredicts that caused a squash. */
442 Stats::Scalar branchMispredicts;
443 /** Distribution of the number of committed instructions each cycle. */
444 Stats::Distribution numCommittedDist;
445
446 /** Total number of instructions committed. */
447 Stats::Vector statComInst;
448 /** Total number of software prefetches committed. */
449 Stats::Vector statComSwp;
450 /** Stat for the total number of committed memory references. */
451 Stats::Vector statComRefs;
452 /** Stat for the total number of committed loads. */
453 Stats::Vector statComLoads;
454 /** Total number of committed memory barriers. */
455 Stats::Vector statComMembars;
456 /** Total number of committed branches. */
457 Stats::Vector statComBranches;
458
459 /** Number of cycles where the commit bandwidth limit is reached. */
460 Stats::Scalar commitEligibleSamples;
461 /** Number of instructions not committed due to bandwidth limits. */
462 Stats::Vector commitEligible;
463};
464
465#endif // __CPU_O3_COMMIT_HH__
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