1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim
| 1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim
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| 29 * Korey Sewell
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29 */ 30 31#ifndef __CPU_O3_COMMIT_HH__ 32#define __CPU_O3_COMMIT_HH__ 33 34#include "arch/faults.hh" 35#include "base/statistics.hh" 36#include "base/timebuf.hh" 37#include "cpu/exetrace.hh" 38#include "cpu/inst_seq.hh" 39 40template <class> 41class O3ThreadState; 42 43/** 44 * DefaultCommit handles single threaded and SMT commit. Its width is 45 * specified by the parameters; each cycle it tries to commit that 46 * many instructions. The SMT policy decides which thread it tries to 47 * commit instructions from. Non- speculative instructions must reach 48 * the head of the ROB before they are ready to execute; once they 49 * reach the head, commit will broadcast the instruction's sequence 50 * number to the previous stages so that they can issue/ execute the 51 * instruction. Only one non-speculative instruction is handled per 52 * cycle. Commit is responsible for handling all back-end initiated 53 * redirects. It receives the redirect, and then broadcasts it to all 54 * stages, indicating the sequence number they should squash until, 55 * and any necessary branch misprediction information as well. It 56 * priortizes redirects by instruction's age, only broadcasting a 57 * redirect if it corresponds to an instruction that should currently 58 * be in the ROB. This is done by tracking the sequence number of the 59 * youngest instruction in the ROB, which gets updated to any 60 * squashing instruction's sequence number, and only broadcasting a 61 * redirect if it corresponds to an older instruction. Commit also 62 * supports multiple cycle squashing, to model a ROB that can only 63 * remove a certain number of instructions per cycle. 64 */ 65template<class Impl> 66class DefaultCommit 67{ 68 public: 69 // Typedefs from the Impl.
| 30 */ 31 32#ifndef __CPU_O3_COMMIT_HH__ 33#define __CPU_O3_COMMIT_HH__ 34 35#include "arch/faults.hh" 36#include "base/statistics.hh" 37#include "base/timebuf.hh" 38#include "cpu/exetrace.hh" 39#include "cpu/inst_seq.hh" 40 41template <class> 42class O3ThreadState; 43 44/** 45 * DefaultCommit handles single threaded and SMT commit. Its width is 46 * specified by the parameters; each cycle it tries to commit that 47 * many instructions. The SMT policy decides which thread it tries to 48 * commit instructions from. Non- speculative instructions must reach 49 * the head of the ROB before they are ready to execute; once they 50 * reach the head, commit will broadcast the instruction's sequence 51 * number to the previous stages so that they can issue/ execute the 52 * instruction. Only one non-speculative instruction is handled per 53 * cycle. Commit is responsible for handling all back-end initiated 54 * redirects. It receives the redirect, and then broadcasts it to all 55 * stages, indicating the sequence number they should squash until, 56 * and any necessary branch misprediction information as well. It 57 * priortizes redirects by instruction's age, only broadcasting a 58 * redirect if it corresponds to an instruction that should currently 59 * be in the ROB. This is done by tracking the sequence number of the 60 * youngest instruction in the ROB, which gets updated to any 61 * squashing instruction's sequence number, and only broadcasting a 62 * redirect if it corresponds to an older instruction. Commit also 63 * supports multiple cycle squashing, to model a ROB that can only 64 * remove a certain number of instructions per cycle. 65 */ 66template<class Impl> 67class DefaultCommit 68{ 69 public: 70 // Typedefs from the Impl.
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70 typedef typename Impl::O3CPU O3CPU;
| 71 typedef typename Impl::FullCPU FullCPU;
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71 typedef typename Impl::DynInstPtr DynInstPtr; 72 typedef typename Impl::Params Params; 73 typedef typename Impl::CPUPol CPUPol; 74 75 typedef typename CPUPol::RenameMap RenameMap; 76 typedef typename CPUPol::ROB ROB; 77 78 typedef typename CPUPol::TimeStruct TimeStruct; 79 typedef typename CPUPol::FetchStruct FetchStruct; 80 typedef typename CPUPol::IEWStruct IEWStruct; 81 typedef typename CPUPol::RenameStruct RenameStruct; 82 83 typedef typename CPUPol::Fetch Fetch; 84 typedef typename CPUPol::IEW IEW; 85 86 typedef O3ThreadState<Impl> Thread; 87 88 /** Event class used to schedule a squash due to a trap (fault or 89 * interrupt) to happen on a specific cycle. 90 */ 91 class TrapEvent : public Event { 92 private: 93 DefaultCommit<Impl> *commit; 94 unsigned tid; 95 96 public: 97 TrapEvent(DefaultCommit<Impl> *_commit, unsigned _tid); 98 99 void process(); 100 const char *description(); 101 }; 102 103 /** Overall commit status. Used to determine if the CPU can deschedule 104 * itself due to a lack of activity. 105 */ 106 enum CommitStatus{ 107 Active, 108 Inactive 109 }; 110 111 /** Individual thread status. */ 112 enum ThreadStatus { 113 Running, 114 Idle, 115 ROBSquashing, 116 TrapPending, 117 FetchTrapPending 118 }; 119 120 /** Commit policy for SMT mode. */ 121 enum CommitPolicy { 122 Aggressive, 123 RoundRobin, 124 OldestReady 125 }; 126 127 private: 128 /** Overall commit status. */ 129 CommitStatus _status; 130 /** Next commit status, to be set at the end of the cycle. */ 131 CommitStatus _nextStatus; 132 /** Per-thread status. */ 133 ThreadStatus commitStatus[Impl::MaxThreads]; 134 /** Commit policy used in SMT mode. */ 135 CommitPolicy commitPolicy; 136 137 public: 138 /** Construct a DefaultCommit with the given parameters. */ 139 DefaultCommit(Params *params); 140 141 /** Returns the name of the DefaultCommit. */ 142 std::string name() const; 143 144 /** Registers statistics. */ 145 void regStats(); 146 147 /** Sets the CPU pointer. */
| 72 typedef typename Impl::DynInstPtr DynInstPtr; 73 typedef typename Impl::Params Params; 74 typedef typename Impl::CPUPol CPUPol; 75 76 typedef typename CPUPol::RenameMap RenameMap; 77 typedef typename CPUPol::ROB ROB; 78 79 typedef typename CPUPol::TimeStruct TimeStruct; 80 typedef typename CPUPol::FetchStruct FetchStruct; 81 typedef typename CPUPol::IEWStruct IEWStruct; 82 typedef typename CPUPol::RenameStruct RenameStruct; 83 84 typedef typename CPUPol::Fetch Fetch; 85 typedef typename CPUPol::IEW IEW; 86 87 typedef O3ThreadState<Impl> Thread; 88 89 /** Event class used to schedule a squash due to a trap (fault or 90 * interrupt) to happen on a specific cycle. 91 */ 92 class TrapEvent : public Event { 93 private: 94 DefaultCommit<Impl> *commit; 95 unsigned tid; 96 97 public: 98 TrapEvent(DefaultCommit<Impl> *_commit, unsigned _tid); 99 100 void process(); 101 const char *description(); 102 }; 103 104 /** Overall commit status. Used to determine if the CPU can deschedule 105 * itself due to a lack of activity. 106 */ 107 enum CommitStatus{ 108 Active, 109 Inactive 110 }; 111 112 /** Individual thread status. */ 113 enum ThreadStatus { 114 Running, 115 Idle, 116 ROBSquashing, 117 TrapPending, 118 FetchTrapPending 119 }; 120 121 /** Commit policy for SMT mode. */ 122 enum CommitPolicy { 123 Aggressive, 124 RoundRobin, 125 OldestReady 126 }; 127 128 private: 129 /** Overall commit status. */ 130 CommitStatus _status; 131 /** Next commit status, to be set at the end of the cycle. */ 132 CommitStatus _nextStatus; 133 /** Per-thread status. */ 134 ThreadStatus commitStatus[Impl::MaxThreads]; 135 /** Commit policy used in SMT mode. */ 136 CommitPolicy commitPolicy; 137 138 public: 139 /** Construct a DefaultCommit with the given parameters. */ 140 DefaultCommit(Params *params); 141 142 /** Returns the name of the DefaultCommit. */ 143 std::string name() const; 144 145 /** Registers statistics. */ 146 void regStats(); 147 148 /** Sets the CPU pointer. */
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148 void setCPU(O3CPU *cpu_ptr);
| 149 void setCPU(FullCPU *cpu_ptr);
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149 150 /** Sets the list of threads. */ 151 void setThreads(std::vector<Thread *> &threads); 152 153 /** Sets the main time buffer pointer, used for backwards communication. */ 154 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 155 156 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 157 158 /** Sets the pointer to the queue coming from rename. */ 159 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 160 161 /** Sets the pointer to the queue coming from IEW. */ 162 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 163 164 void setFetchStage(Fetch *fetch_stage); 165 166 Fetch *fetchStage; 167 168 /** Sets the pointer to the IEW stage. */ 169 void setIEWStage(IEW *iew_stage); 170 171 /** The pointer to the IEW stage. Used solely to ensure that 172 * various events (traps, interrupts, syscalls) do not occur until 173 * all stores have written back. 174 */ 175 IEW *iewStage; 176 177 /** Sets pointer to list of active threads. */ 178 void setActiveThreads(std::list<unsigned> *at_ptr); 179 180 /** Sets pointer to the commited state rename map. */ 181 void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]); 182 183 /** Sets pointer to the ROB. */ 184 void setROB(ROB *rob_ptr); 185 186 /** Initializes stage by sending back the number of free entries. */ 187 void initStage(); 188 189 /** Initializes the switching out of commit. */ 190 void switchOut(); 191 192 /** Completes the switch out of commit. */ 193 void doSwitchOut(); 194 195 /** Takes over from another CPU's thread. */ 196 void takeOverFrom(); 197 198 /** Ticks the commit stage, which tries to commit instructions. */ 199 void tick(); 200 201 /** Handles any squashes that are sent from IEW, and adds instructions 202 * to the ROB and tries to commit instructions. 203 */ 204 void commit(); 205 206 /** Returns the number of free ROB entries for a specific thread. */ 207 unsigned numROBFreeEntries(unsigned tid); 208 209 /** Generates an event to schedule a squash due to a trap. */ 210 void generateTrapEvent(unsigned tid); 211 212 /** Records that commit needs to initiate a squash due to an 213 * external state update through the TC. 214 */ 215 void generateTCEvent(unsigned tid); 216 217 private: 218 /** Updates the overall status of commit with the nextStatus, and 219 * tell the CPU if commit is active/inactive. 220 */ 221 void updateStatus(); 222 223 /** Sets the next status based on threads' statuses, which becomes the 224 * current status at the end of the cycle. 225 */ 226 void setNextStatus(); 227 228 /** Checks if the ROB is completed with squashing. This is for the case 229 * where the ROB can take multiple cycles to complete squashing. 230 */ 231 bool robDoneSquashing(); 232 233 /** Returns if any of the threads have the number of ROB entries changed 234 * on this cycle. Used to determine if the number of free ROB entries needs 235 * to be sent back to previous stages. 236 */ 237 bool changedROBEntries(); 238 239 /** Squashes all in flight instructions. */ 240 void squashAll(unsigned tid); 241 242 /** Handles squashing due to a trap. */ 243 void squashFromTrap(unsigned tid); 244 245 /** Handles squashing due to an TC write. */ 246 void squashFromTC(unsigned tid); 247 248 /** Commits as many instructions as possible. */ 249 void commitInsts(); 250 251 /** Tries to commit the head ROB instruction passed in. 252 * @param head_inst The instruction to be committed. 253 */ 254 bool commitHead(DynInstPtr &head_inst, unsigned inst_num); 255 256 /** Gets instructions from rename and inserts them into the ROB. */ 257 void getInsts(); 258 259 /** Marks completed instructions using information sent from IEW. */ 260 void markCompletedInsts(); 261 262 /** Gets the thread to commit, based on the SMT policy. */ 263 int getCommittingThread(); 264 265 /** Returns the thread ID to use based on a round robin policy. */ 266 int roundRobin(); 267 268 /** Returns the thread ID to use based on an oldest instruction policy. */ 269 int oldestReady(); 270 271 public: 272 /** Returns the PC of the head instruction of the ROB. 273 * @todo: Probably remove this function as it returns only thread 0. 274 */ 275 uint64_t readPC() { return PC[0]; } 276 277 /** Returns the PC of a specific thread. */ 278 uint64_t readPC(unsigned tid) { return PC[tid]; } 279 280 /** Sets the PC of a specific thread. */ 281 void setPC(uint64_t val, unsigned tid) { PC[tid] = val; } 282
| 150 151 /** Sets the list of threads. */ 152 void setThreads(std::vector<Thread *> &threads); 153 154 /** Sets the main time buffer pointer, used for backwards communication. */ 155 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 156 157 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 158 159 /** Sets the pointer to the queue coming from rename. */ 160 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 161 162 /** Sets the pointer to the queue coming from IEW. */ 163 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 164 165 void setFetchStage(Fetch *fetch_stage); 166 167 Fetch *fetchStage; 168 169 /** Sets the pointer to the IEW stage. */ 170 void setIEWStage(IEW *iew_stage); 171 172 /** The pointer to the IEW stage. Used solely to ensure that 173 * various events (traps, interrupts, syscalls) do not occur until 174 * all stores have written back. 175 */ 176 IEW *iewStage; 177 178 /** Sets pointer to list of active threads. */ 179 void setActiveThreads(std::list<unsigned> *at_ptr); 180 181 /** Sets pointer to the commited state rename map. */ 182 void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]); 183 184 /** Sets pointer to the ROB. */ 185 void setROB(ROB *rob_ptr); 186 187 /** Initializes stage by sending back the number of free entries. */ 188 void initStage(); 189 190 /** Initializes the switching out of commit. */ 191 void switchOut(); 192 193 /** Completes the switch out of commit. */ 194 void doSwitchOut(); 195 196 /** Takes over from another CPU's thread. */ 197 void takeOverFrom(); 198 199 /** Ticks the commit stage, which tries to commit instructions. */ 200 void tick(); 201 202 /** Handles any squashes that are sent from IEW, and adds instructions 203 * to the ROB and tries to commit instructions. 204 */ 205 void commit(); 206 207 /** Returns the number of free ROB entries for a specific thread. */ 208 unsigned numROBFreeEntries(unsigned tid); 209 210 /** Generates an event to schedule a squash due to a trap. */ 211 void generateTrapEvent(unsigned tid); 212 213 /** Records that commit needs to initiate a squash due to an 214 * external state update through the TC. 215 */ 216 void generateTCEvent(unsigned tid); 217 218 private: 219 /** Updates the overall status of commit with the nextStatus, and 220 * tell the CPU if commit is active/inactive. 221 */ 222 void updateStatus(); 223 224 /** Sets the next status based on threads' statuses, which becomes the 225 * current status at the end of the cycle. 226 */ 227 void setNextStatus(); 228 229 /** Checks if the ROB is completed with squashing. This is for the case 230 * where the ROB can take multiple cycles to complete squashing. 231 */ 232 bool robDoneSquashing(); 233 234 /** Returns if any of the threads have the number of ROB entries changed 235 * on this cycle. Used to determine if the number of free ROB entries needs 236 * to be sent back to previous stages. 237 */ 238 bool changedROBEntries(); 239 240 /** Squashes all in flight instructions. */ 241 void squashAll(unsigned tid); 242 243 /** Handles squashing due to a trap. */ 244 void squashFromTrap(unsigned tid); 245 246 /** Handles squashing due to an TC write. */ 247 void squashFromTC(unsigned tid); 248 249 /** Commits as many instructions as possible. */ 250 void commitInsts(); 251 252 /** Tries to commit the head ROB instruction passed in. 253 * @param head_inst The instruction to be committed. 254 */ 255 bool commitHead(DynInstPtr &head_inst, unsigned inst_num); 256 257 /** Gets instructions from rename and inserts them into the ROB. */ 258 void getInsts(); 259 260 /** Marks completed instructions using information sent from IEW. */ 261 void markCompletedInsts(); 262 263 /** Gets the thread to commit, based on the SMT policy. */ 264 int getCommittingThread(); 265 266 /** Returns the thread ID to use based on a round robin policy. */ 267 int roundRobin(); 268 269 /** Returns the thread ID to use based on an oldest instruction policy. */ 270 int oldestReady(); 271 272 public: 273 /** Returns the PC of the head instruction of the ROB. 274 * @todo: Probably remove this function as it returns only thread 0. 275 */ 276 uint64_t readPC() { return PC[0]; } 277 278 /** Returns the PC of a specific thread. */ 279 uint64_t readPC(unsigned tid) { return PC[tid]; } 280 281 /** Sets the PC of a specific thread. */ 282 void setPC(uint64_t val, unsigned tid) { PC[tid] = val; } 283
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283 /** Reads the PC of a specific thread. */
| 284 /** Reads the next PC of a specific thread. */
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284 uint64_t readNextPC(unsigned tid) { return nextPC[tid]; } 285 286 /** Sets the next PC of a specific thread. */ 287 void setNextPC(uint64_t val, unsigned tid) { nextPC[tid] = val; } 288
| 285 uint64_t readNextPC(unsigned tid) { return nextPC[tid]; } 286 287 /** Sets the next PC of a specific thread. */ 288 void setNextPC(uint64_t val, unsigned tid) { nextPC[tid] = val; } 289
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| 290#if THE_ISA != ALPHA_ISA 291 /** Reads the next NPC of a specific thread. */ 292 uint64_t readNextPC(unsigned tid) { return nextNPC[tid]; } 293 294 /** Sets the next NPC of a specific thread. */ 295 void setNextPC(uint64_t val, unsigned tid) { nextNPC[tid] = val; } 296#endif 297
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289 private: 290 /** Time buffer interface. */ 291 TimeBuffer<TimeStruct> *timeBuffer; 292 293 /** Wire to write information heading to previous stages. */ 294 typename TimeBuffer<TimeStruct>::wire toIEW; 295 296 /** Wire to read information from IEW (for ROB). */ 297 typename TimeBuffer<TimeStruct>::wire robInfoFromIEW; 298 299 TimeBuffer<FetchStruct> *fetchQueue; 300 301 typename TimeBuffer<FetchStruct>::wire fromFetch; 302 303 /** IEW instruction queue interface. */ 304 TimeBuffer<IEWStruct> *iewQueue; 305 306 /** Wire to read information from IEW queue. */ 307 typename TimeBuffer<IEWStruct>::wire fromIEW; 308 309 /** Rename instruction queue interface, for ROB. */ 310 TimeBuffer<RenameStruct> *renameQueue; 311 312 /** Wire to read information from rename queue. */ 313 typename TimeBuffer<RenameStruct>::wire fromRename; 314 315 public: 316 /** ROB interface. */ 317 ROB *rob; 318 319 private:
| 298 private: 299 /** Time buffer interface. */ 300 TimeBuffer<TimeStruct> *timeBuffer; 301 302 /** Wire to write information heading to previous stages. */ 303 typename TimeBuffer<TimeStruct>::wire toIEW; 304 305 /** Wire to read information from IEW (for ROB). */ 306 typename TimeBuffer<TimeStruct>::wire robInfoFromIEW; 307 308 TimeBuffer<FetchStruct> *fetchQueue; 309 310 typename TimeBuffer<FetchStruct>::wire fromFetch; 311 312 /** IEW instruction queue interface. */ 313 TimeBuffer<IEWStruct> *iewQueue; 314 315 /** Wire to read information from IEW queue. */ 316 typename TimeBuffer<IEWStruct>::wire fromIEW; 317 318 /** Rename instruction queue interface, for ROB. */ 319 TimeBuffer<RenameStruct> *renameQueue; 320 321 /** Wire to read information from rename queue. */ 322 typename TimeBuffer<RenameStruct>::wire fromRename; 323 324 public: 325 /** ROB interface. */ 326 ROB *rob; 327 328 private:
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320 /** Pointer to O3CPU. */ 321 O3CPU *cpu;
| 329 /** Pointer to FullCPU. */ 330 FullCPU *cpu;
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322 323 /** Vector of all of the threads. */ 324 std::vector<Thread *> thread; 325 326 Fault fetchFault; 327 328 int fetchTrapWait; 329 330 /** Records that commit has written to the time buffer this cycle. Used for 331 * the CPU to determine if it can deschedule itself if there is no activity. 332 */ 333 bool wroteToTimeBuffer; 334 335 /** Records if the number of ROB entries has changed this cycle. If it has, 336 * then the number of free entries must be re-broadcast. 337 */ 338 bool changedROBNumEntries[Impl::MaxThreads]; 339 340 /** A counter of how many threads are currently squashing. */ 341 int squashCounter; 342 343 /** Records if a thread has to squash this cycle due to a trap. */ 344 bool trapSquash[Impl::MaxThreads]; 345 346 /** Records if a thread has to squash this cycle due to an XC write. */ 347 bool tcSquash[Impl::MaxThreads]; 348 349 /** Priority List used for Commit Policy */ 350 std::list<unsigned> priority_list; 351 352 /** IEW to Commit delay, in ticks. */ 353 unsigned iewToCommitDelay; 354 355 /** Commit to IEW delay, in ticks. */ 356 unsigned commitToIEWDelay; 357 358 /** Rename to ROB delay, in ticks. */ 359 unsigned renameToROBDelay; 360 361 unsigned fetchToCommitDelay; 362 363 /** Rename width, in instructions. Used so ROB knows how many 364 * instructions to get from the rename instruction queue. 365 */ 366 unsigned renameWidth; 367 368 /** Commit width, in instructions. */ 369 unsigned commitWidth; 370 371 /** Number of Reorder Buffers */ 372 unsigned numRobs; 373 374 /** Number of Active Threads */ 375 unsigned numThreads; 376 377 /** Is a switch out pending. */ 378 bool switchPending; 379 380 /** Is commit switched out. */ 381 bool switchedOut; 382 383 /** The latency to handle a trap. Used when scheduling trap 384 * squash event. 385 */ 386 Tick trapLatency; 387 388 Tick fetchTrapLatency; 389 390 Tick fetchFaultTick; 391 392 /** The commit PC of each thread. Refers to the instruction that 393 * is currently being processed/committed. 394 */ 395 Addr PC[Impl::MaxThreads]; 396 397 /** The next PC of each thread. */ 398 Addr nextPC[Impl::MaxThreads]; 399
| 331 332 /** Vector of all of the threads. */ 333 std::vector<Thread *> thread; 334 335 Fault fetchFault; 336 337 int fetchTrapWait; 338 339 /** Records that commit has written to the time buffer this cycle. Used for 340 * the CPU to determine if it can deschedule itself if there is no activity. 341 */ 342 bool wroteToTimeBuffer; 343 344 /** Records if the number of ROB entries has changed this cycle. If it has, 345 * then the number of free entries must be re-broadcast. 346 */ 347 bool changedROBNumEntries[Impl::MaxThreads]; 348 349 /** A counter of how many threads are currently squashing. */ 350 int squashCounter; 351 352 /** Records if a thread has to squash this cycle due to a trap. */ 353 bool trapSquash[Impl::MaxThreads]; 354 355 /** Records if a thread has to squash this cycle due to an XC write. */ 356 bool tcSquash[Impl::MaxThreads]; 357 358 /** Priority List used for Commit Policy */ 359 std::list<unsigned> priority_list; 360 361 /** IEW to Commit delay, in ticks. */ 362 unsigned iewToCommitDelay; 363 364 /** Commit to IEW delay, in ticks. */ 365 unsigned commitToIEWDelay; 366 367 /** Rename to ROB delay, in ticks. */ 368 unsigned renameToROBDelay; 369 370 unsigned fetchToCommitDelay; 371 372 /** Rename width, in instructions. Used so ROB knows how many 373 * instructions to get from the rename instruction queue. 374 */ 375 unsigned renameWidth; 376 377 /** Commit width, in instructions. */ 378 unsigned commitWidth; 379 380 /** Number of Reorder Buffers */ 381 unsigned numRobs; 382 383 /** Number of Active Threads */ 384 unsigned numThreads; 385 386 /** Is a switch out pending. */ 387 bool switchPending; 388 389 /** Is commit switched out. */ 390 bool switchedOut; 391 392 /** The latency to handle a trap. Used when scheduling trap 393 * squash event. 394 */ 395 Tick trapLatency; 396 397 Tick fetchTrapLatency; 398 399 Tick fetchFaultTick; 400 401 /** The commit PC of each thread. Refers to the instruction that 402 * is currently being processed/committed. 403 */ 404 Addr PC[Impl::MaxThreads]; 405 406 /** The next PC of each thread. */ 407 Addr nextPC[Impl::MaxThreads]; 408
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| 409 /** The next NPC of each thread. */ 410 Addr nextNPC[Impl::MaxThreads]; 411
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400 /** The sequence number of the youngest valid instruction in the ROB. */ 401 InstSeqNum youngestSeqNum[Impl::MaxThreads]; 402 403 /** Pointer to the list of active threads. */ 404 std::list<unsigned> *activeThreads; 405 406 /** Rename map interface. */ 407 RenameMap *renameMap[Impl::MaxThreads]; 408 409 /** Updates commit stats based on this instruction. */ 410 void updateComInstStats(DynInstPtr &inst); 411 412 /** Stat for the total number of committed instructions. */ 413 Stats::Scalar<> commitCommittedInsts; 414 /** Stat for the total number of squashed instructions discarded by commit. 415 */ 416 Stats::Scalar<> commitSquashedInsts; 417 /** Stat for the total number of times commit is told to squash. 418 * @todo: Actually increment this stat. 419 */ 420 Stats::Scalar<> commitSquashEvents; 421 /** Stat for the total number of times commit has had to stall due to a non- 422 * speculative instruction reaching the head of the ROB. 423 */ 424 Stats::Scalar<> commitNonSpecStalls; 425 /** Stat for the total number of branch mispredicts that caused a squash. */ 426 Stats::Scalar<> branchMispredicts; 427 /** Distribution of the number of committed instructions each cycle. */ 428 Stats::Distribution<> numCommittedDist; 429 430 /** Total number of instructions committed. */ 431 Stats::Vector<> statComInst; 432 /** Total number of software prefetches committed. */ 433 Stats::Vector<> statComSwp; 434 /** Stat for the total number of committed memory references. */ 435 Stats::Vector<> statComRefs; 436 /** Stat for the total number of committed loads. */ 437 Stats::Vector<> statComLoads; 438 /** Total number of committed memory barriers. */ 439 Stats::Vector<> statComMembars; 440 /** Total number of committed branches. */ 441 Stats::Vector<> statComBranches; 442 443 /** Number of cycles where the commit bandwidth limit is reached. */ 444 Stats::Scalar<> commitEligibleSamples; 445 /** Number of instructions not committed due to bandwidth limits. */ 446 Stats::Vector<> commitEligible; 447}; 448 449#endif // __CPU_O3_COMMIT_HH__
| 412 /** The sequence number of the youngest valid instruction in the ROB. */ 413 InstSeqNum youngestSeqNum[Impl::MaxThreads]; 414 415 /** Pointer to the list of active threads. */ 416 std::list<unsigned> *activeThreads; 417 418 /** Rename map interface. */ 419 RenameMap *renameMap[Impl::MaxThreads]; 420 421 /** Updates commit stats based on this instruction. */ 422 void updateComInstStats(DynInstPtr &inst); 423 424 /** Stat for the total number of committed instructions. */ 425 Stats::Scalar<> commitCommittedInsts; 426 /** Stat for the total number of squashed instructions discarded by commit. 427 */ 428 Stats::Scalar<> commitSquashedInsts; 429 /** Stat for the total number of times commit is told to squash. 430 * @todo: Actually increment this stat. 431 */ 432 Stats::Scalar<> commitSquashEvents; 433 /** Stat for the total number of times commit has had to stall due to a non- 434 * speculative instruction reaching the head of the ROB. 435 */ 436 Stats::Scalar<> commitNonSpecStalls; 437 /** Stat for the total number of branch mispredicts that caused a squash. */ 438 Stats::Scalar<> branchMispredicts; 439 /** Distribution of the number of committed instructions each cycle. */ 440 Stats::Distribution<> numCommittedDist; 441 442 /** Total number of instructions committed. */ 443 Stats::Vector<> statComInst; 444 /** Total number of software prefetches committed. */ 445 Stats::Vector<> statComSwp; 446 /** Stat for the total number of committed memory references. */ 447 Stats::Vector<> statComRefs; 448 /** Stat for the total number of committed loads. */ 449 Stats::Vector<> statComLoads; 450 /** Total number of committed memory barriers. */ 451 Stats::Vector<> statComMembars; 452 /** Total number of committed branches. */ 453 Stats::Vector<> statComBranches; 454 455 /** Number of cycles where the commit bandwidth limit is reached. */ 456 Stats::Scalar<> commitEligibleSamples; 457 /** Number of instructions not committed due to bandwidth limits. */ 458 Stats::Vector<> commitEligible; 459}; 460 461#endif // __CPU_O3_COMMIT_HH__
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