1/*
2 * Copyright (c) 2010-2012, 2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#ifndef __CPU_O3_COMMIT_HH__
45#define __CPU_O3_COMMIT_HH__
46
47#include <queue>
48
49#include "base/statistics.hh"
50#include "cpu/exetrace.hh"
51#include "cpu/inst_seq.hh"
52#include "cpu/timebuf.hh"
53#include "sim/probe/probe.hh"
54
55struct DerivO3CPUParams;
56
57template <class>
58struct O3ThreadState;
59
60/**
61 * DefaultCommit handles single threaded and SMT commit. Its width is
62 * specified by the parameters; each cycle it tries to commit that
63 * many instructions. The SMT policy decides which thread it tries to
64 * commit instructions from. Non- speculative instructions must reach
65 * the head of the ROB before they are ready to execute; once they
66 * reach the head, commit will broadcast the instruction's sequence
67 * number to the previous stages so that they can issue/ execute the
68 * instruction. Only one non-speculative instruction is handled per
69 * cycle. Commit is responsible for handling all back-end initiated
70 * redirects. It receives the redirect, and then broadcasts it to all
71 * stages, indicating the sequence number they should squash until,
72 * and any necessary branch misprediction information as well. It
73 * priortizes redirects by instruction's age, only broadcasting a
74 * redirect if it corresponds to an instruction that should currently
75 * be in the ROB. This is done by tracking the sequence number of the
76 * youngest instruction in the ROB, which gets updated to any
77 * squashing instruction's sequence number, and only broadcasting a
78 * redirect if it corresponds to an older instruction. Commit also
79 * supports multiple cycle squashing, to model a ROB that can only
80 * remove a certain number of instructions per cycle.
81 */
82template<class Impl>
83class DefaultCommit
84{
85 public:
86 // Typedefs from the Impl.
87 typedef typename Impl::O3CPU O3CPU;
88 typedef typename Impl::DynInstPtr DynInstPtr;
89 typedef typename Impl::CPUPol CPUPol;
90
91 typedef typename CPUPol::RenameMap RenameMap;
92 typedef typename CPUPol::ROB ROB;
93
94 typedef typename CPUPol::TimeStruct TimeStruct;
95 typedef typename CPUPol::FetchStruct FetchStruct;
96 typedef typename CPUPol::IEWStruct IEWStruct;
97 typedef typename CPUPol::RenameStruct RenameStruct;
98
99 typedef typename CPUPol::Fetch Fetch;
100 typedef typename CPUPol::IEW IEW;
101
102 typedef O3ThreadState<Impl> Thread;
103
104 /** Event class used to schedule a squash due to a trap (fault or
105 * interrupt) to happen on a specific cycle.
106 */
107 class TrapEvent : public Event {
108 private:
109 DefaultCommit<Impl> *commit;
110 ThreadID tid;
111
112 public:
113 TrapEvent(DefaultCommit<Impl> *_commit, ThreadID _tid);
114
115 void process();
116 const char *description() const;
117 };
118
119 /** Overall commit status. Used to determine if the CPU can deschedule
120 * itself due to a lack of activity.
121 */
122 enum CommitStatus{
123 Active,
124 Inactive
125 };
126
127 /** Individual thread status. */
128 enum ThreadStatus {
129 Running,
130 Idle,
131 ROBSquashing,
132 TrapPending,
133 FetchTrapPending,
134 SquashAfterPending, //< Committing instructions before a squash.
135 };
136
137 /** Commit policy for SMT mode. */
138 enum CommitPolicy {
139 Aggressive,
140 RoundRobin,
141 OldestReady
142 };
143
144 private:
145 /** Overall commit status. */
146 CommitStatus _status;
147 /** Next commit status, to be set at the end of the cycle. */
148 CommitStatus _nextStatus;
149 /** Per-thread status. */
150 ThreadStatus commitStatus[Impl::MaxThreads];
151 /** Commit policy used in SMT mode. */
152 CommitPolicy commitPolicy;
153
154 /** Probe Points. */
155 ProbePointArg<DynInstPtr> *ppCommit;
156 ProbePointArg<DynInstPtr> *ppCommitStall;
157 /** To probe when an instruction is squashed */
158 ProbePointArg<DynInstPtr> *ppSquash;
159
160 public:
161 /** Construct a DefaultCommit with the given parameters. */
162 DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params);
163
164 /** Returns the name of the DefaultCommit. */
165 std::string name() const;
166
167 /** Registers statistics. */
168 void regStats();
169
170 /** Registers probes. */
171 void regProbePoints();
172
173 /** Sets the list of threads. */
174 void setThreads(std::vector<Thread *> &threads);
175
176 /** Sets the main time buffer pointer, used for backwards communication. */
177 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
178
179 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
180
181 /** Sets the pointer to the queue coming from rename. */
182 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
183
184 /** Sets the pointer to the queue coming from IEW. */
185 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
186
187 /** Sets the pointer to the IEW stage. */
188 void setIEWStage(IEW *iew_stage);
189
190 /** The pointer to the IEW stage. Used solely to ensure that
191 * various events (traps, interrupts, syscalls) do not occur until
192 * all stores have written back.
193 */
194 IEW *iewStage;
195
196 /** Sets pointer to list of active threads. */
197 void setActiveThreads(std::list<ThreadID> *at_ptr);
198
199 /** Sets pointer to the commited state rename map. */
200 void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
201
202 /** Sets pointer to the ROB. */
203 void setROB(ROB *rob_ptr);
204
205 /** Initializes stage by sending back the number of free entries. */
206 void startupStage();
207
208 /** Initializes the draining of commit. */
209 void drain();
210
211 /** Resumes execution after draining. */
212 void drainResume();
213
214 /** Perform sanity checks after a drain. */
215 void drainSanityCheck() const;
216
217 /** Has the stage drained? */
218 bool isDrained() const;
219
220 /** Takes over from another CPU's thread. */
221 void takeOverFrom();
222
223 /** Deschedules a thread from scheduling */
224 void deactivateThread(ThreadID tid);
225
226 /** Ticks the commit stage, which tries to commit instructions. */
227 void tick();
228
229 /** Handles any squashes that are sent from IEW, and adds instructions
230 * to the ROB and tries to commit instructions.
231 */
232 void commit();
233
234 /** Returns the number of free ROB entries for a specific thread. */
235 size_t numROBFreeEntries(ThreadID tid);
236
237 /** Generates an event to schedule a squash due to a trap. */
238 void generateTrapEvent(ThreadID tid, Fault inst_fault);
239
240 /** Records that commit needs to initiate a squash due to an
241 * external state update through the TC.
242 */
243 void generateTCEvent(ThreadID tid);
244
245 private:
246 /** Updates the overall status of commit with the nextStatus, and
247 * tell the CPU if commit is active/inactive.
248 */
249 void updateStatus();
250
251 /** Returns if any of the threads have the number of ROB entries changed
252 * on this cycle. Used to determine if the number of free ROB entries needs
253 * to be sent back to previous stages.
254 */
255 bool changedROBEntries();
256
257 /** Squashes all in flight instructions. */
258 void squashAll(ThreadID tid);
259
260 /** Handles squashing due to a trap. */
261 void squashFromTrap(ThreadID tid);
262
263 /** Handles squashing due to an TC write. */
264 void squashFromTC(ThreadID tid);
265
266 /** Handles a squash from a squashAfter() request. */
267 void squashFromSquashAfter(ThreadID tid);
268
269 /**
270 * Handle squashing from instruction with SquashAfter set.
271 *
272 * This differs from the other squashes as it squashes following
273 * instructions instead of the current instruction and doesn't
274 * clean up various status bits about traps/tc writes
275 * pending. Since there might have been instructions committed by
276 * the commit stage before the squashing instruction was reached
277 * and we can't commit and squash in the same cycle, we have to
278 * squash in two steps:
279 *
280 * <ol>
281 * <li>Immediately set the commit status of the thread of
282 * SquashAfterPending. This forces the thread to stop
283 * committing instructions in this cycle. The last
284 * instruction to be committed in this cycle will be the
285 * SquashAfter instruction.
286 * <li>In the next cycle, commit() checks for the
287 * SquashAfterPending state and squashes <i>all</i>
288 * in-flight instructions. Since the SquashAfter instruction
289 * was the last instruction to be committed in the previous
290 * cycle, this causes all subsequent instructions to be
291 * squashed.
292 * </ol>
293 *
294 * @param tid ID of the thread to squash.
295 * @param head_inst Instruction that requested the squash.
296 */
297 void squashAfter(ThreadID tid, DynInstPtr &head_inst);
298
299 /** Handles processing an interrupt. */
300 void handleInterrupt();
301
302 /** Get fetch redirecting so we can handle an interrupt */
303 void propagateInterrupt();
304
305 /** Commits as many instructions as possible. */
306 void commitInsts();
307
308 /** Tries to commit the head ROB instruction passed in.
309 * @param head_inst The instruction to be committed.
310 */
311 bool commitHead(DynInstPtr &head_inst, unsigned inst_num);
312
313 /** Gets instructions from rename and inserts them into the ROB. */
314 void getInsts();
315
316 /** Marks completed instructions using information sent from IEW. */
317 void markCompletedInsts();
318
319 /** Gets the thread to commit, based on the SMT policy. */
320 ThreadID getCommittingThread();
321
322 /** Returns the thread ID to use based on a round robin policy. */
323 ThreadID roundRobin();
324
325 /** Returns the thread ID to use based on an oldest instruction policy. */
326 ThreadID oldestReady();
327
328 public:
329 /** Reads the PC of a specific thread. */
330 TheISA::PCState pcState(ThreadID tid) { return pc[tid]; }
331
332 /** Sets the PC of a specific thread. */
333 void pcState(const TheISA::PCState &val, ThreadID tid)
334 { pc[tid] = val; }
335
336 /** Returns the PC of a specific thread. */
337 Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
338
339 /** Returns the next PC of a specific thread. */
340 Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
341
342 /** Reads the micro PC of a specific thread. */
343 Addr microPC(ThreadID tid) { return pc[tid].microPC(); }
344
345 private:
346 /** Time buffer interface. */
347 TimeBuffer<TimeStruct> *timeBuffer;
348
349 /** Wire to write information heading to previous stages. */
350 typename TimeBuffer<TimeStruct>::wire toIEW;
351
352 /** Wire to read information from IEW (for ROB). */
353 typename TimeBuffer<TimeStruct>::wire robInfoFromIEW;
354
355 TimeBuffer<FetchStruct> *fetchQueue;
356
357 typename TimeBuffer<FetchStruct>::wire fromFetch;
358
359 /** IEW instruction queue interface. */
360 TimeBuffer<IEWStruct> *iewQueue;
361
362 /** Wire to read information from IEW queue. */
363 typename TimeBuffer<IEWStruct>::wire fromIEW;
364
365 /** Rename instruction queue interface, for ROB. */
366 TimeBuffer<RenameStruct> *renameQueue;
367
368 /** Wire to read information from rename queue. */
369 typename TimeBuffer<RenameStruct>::wire fromRename;
370
371 public:
372 /** ROB interface. */
373 ROB *rob;
374
375 private:
376 /** Pointer to O3CPU. */
377 O3CPU *cpu;
378
379 /** Vector of all of the threads. */
380 std::vector<Thread *> thread;
381
382 /** Records that commit has written to the time buffer this cycle. Used for
383 * the CPU to determine if it can deschedule itself if there is no activity.
384 */
385 bool wroteToTimeBuffer;
386
387 /** Records if the number of ROB entries has changed this cycle. If it has,
388 * then the number of free entries must be re-broadcast.
389 */
390 bool changedROBNumEntries[Impl::MaxThreads];
391
392 /** Records if a thread has to squash this cycle due to a trap. */
393 bool trapSquash[Impl::MaxThreads];
394
395 /** Records if a thread has to squash this cycle due to an XC write. */
396 bool tcSquash[Impl::MaxThreads];
397
398 /**
399 * Instruction passed to squashAfter().
400 *
401 * The squash after implementation needs to buffer the instruction
402 * that caused a squash since this needs to be passed to the fetch
403 * stage once squashing starts.
404 */
405 DynInstPtr squashAfterInst[Impl::MaxThreads];
406
407 /** Priority List used for Commit Policy */
408 std::list<ThreadID> priority_list;
409
410 /** IEW to Commit delay. */
411 const Cycles iewToCommitDelay;
412
413 /** Commit to IEW delay. */
414 const Cycles commitToIEWDelay;
415
416 /** Rename to ROB delay. */
417 const Cycles renameToROBDelay;
418
419 const Cycles fetchToCommitDelay;
420
421 /** Rename width, in instructions. Used so ROB knows how many
422 * instructions to get from the rename instruction queue.
423 */
424 const unsigned renameWidth;
425
426 /** Commit width, in instructions. */
427 const unsigned commitWidth;
428
429 /** Number of Reorder Buffers */
430 unsigned numRobs;
431
432 /** Number of Active Threads */
433 const ThreadID numThreads;
434
435 /** Is a drain pending? Commit is looking for an instruction boundary while
436 * there are no pending interrupts
437 */
438 bool drainPending;
439
440 /** Is a drain imminent? Commit has found an instruction boundary while no
441 * interrupts were present or in flight. This was the last architecturally
442 * committed instruction. Interrupts disabled and pipeline flushed.
443 * Waiting for structures to finish draining.
444 */
445 bool drainImminent;
446
447 /** The latency to handle a trap. Used when scheduling trap
448 * squash event.
449 */
450 const Cycles trapLatency;
451
452 /** The interrupt fault. */
453 Fault interrupt;
454
455 /** The commit PC state of each thread. Refers to the instruction that
456 * is currently being processed/committed.
457 */
458 TheISA::PCState pc[Impl::MaxThreads];
459
460 /** The sequence number of the youngest valid instruction in the ROB. */
461 InstSeqNum youngestSeqNum[Impl::MaxThreads];
462
463 /** The sequence number of the last commited instruction. */
464 InstSeqNum lastCommitedSeqNum[Impl::MaxThreads];
465
466 /** Records if there is a trap currently in flight. */
467 bool trapInFlight[Impl::MaxThreads];
468
469 /** Records if there were any stores committed this cycle. */
470 bool committedStores[Impl::MaxThreads];
471
472 /** Records if commit should check if the ROB is truly empty (see
473 commit_impl.hh). */
474 bool checkEmptyROB[Impl::MaxThreads];
475
476 /** Pointer to the list of active threads. */
477 std::list<ThreadID> *activeThreads;
478
479 /** Rename map interface. */
480 RenameMap *renameMap[Impl::MaxThreads];
481
482 /** True if last committed microop can be followed by an interrupt */
483 bool canHandleInterrupts;
484
485 /** Have we had an interrupt pending and then seen it de-asserted because
486 of a masking change? In this case the variable is set and the next time
487 interrupts are enabled and pending the pipeline will squash to avoid
488 a possible livelock senario. */
489 bool avoidQuiesceLiveLock;
490
491 /** Updates commit stats based on this instruction. */
492 void updateComInstStats(DynInstPtr &inst);
493
494 /** Stat for the total number of squashed instructions discarded by commit.
495 */
496 Stats::Scalar commitSquashedInsts;
497 /** Stat for the total number of times commit has had to stall due to a non-
498 * speculative instruction reaching the head of the ROB.
499 */
500 Stats::Scalar commitNonSpecStalls;
501 /** Stat for the total number of branch mispredicts that caused a squash. */
502 Stats::Scalar branchMispredicts;
503 /** Distribution of the number of committed instructions each cycle. */
504 Stats::Distribution numCommittedDist;
505
506 /** Total number of instructions committed. */
507 Stats::Vector instsCommitted;
508 /** Total number of ops (including micro ops) committed. */
509 Stats::Vector opsCommitted;
510 /** Total number of software prefetches committed. */
511 Stats::Vector statComSwp;
512 /** Stat for the total number of committed memory references. */
513 Stats::Vector statComRefs;
514 /** Stat for the total number of committed loads. */
515 Stats::Vector statComLoads;
516 /** Total number of committed memory barriers. */
517 Stats::Vector statComMembars;
518 /** Total number of committed branches. */
519 Stats::Vector statComBranches;
| 1/*
2 * Copyright (c) 2010-2012, 2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 * Korey Sewell
42 */
43
44#ifndef __CPU_O3_COMMIT_HH__
45#define __CPU_O3_COMMIT_HH__
46
47#include <queue>
48
49#include "base/statistics.hh"
50#include "cpu/exetrace.hh"
51#include "cpu/inst_seq.hh"
52#include "cpu/timebuf.hh"
53#include "sim/probe/probe.hh"
54
55struct DerivO3CPUParams;
56
57template <class>
58struct O3ThreadState;
59
60/**
61 * DefaultCommit handles single threaded and SMT commit. Its width is
62 * specified by the parameters; each cycle it tries to commit that
63 * many instructions. The SMT policy decides which thread it tries to
64 * commit instructions from. Non- speculative instructions must reach
65 * the head of the ROB before they are ready to execute; once they
66 * reach the head, commit will broadcast the instruction's sequence
67 * number to the previous stages so that they can issue/ execute the
68 * instruction. Only one non-speculative instruction is handled per
69 * cycle. Commit is responsible for handling all back-end initiated
70 * redirects. It receives the redirect, and then broadcasts it to all
71 * stages, indicating the sequence number they should squash until,
72 * and any necessary branch misprediction information as well. It
73 * priortizes redirects by instruction's age, only broadcasting a
74 * redirect if it corresponds to an instruction that should currently
75 * be in the ROB. This is done by tracking the sequence number of the
76 * youngest instruction in the ROB, which gets updated to any
77 * squashing instruction's sequence number, and only broadcasting a
78 * redirect if it corresponds to an older instruction. Commit also
79 * supports multiple cycle squashing, to model a ROB that can only
80 * remove a certain number of instructions per cycle.
81 */
82template<class Impl>
83class DefaultCommit
84{
85 public:
86 // Typedefs from the Impl.
87 typedef typename Impl::O3CPU O3CPU;
88 typedef typename Impl::DynInstPtr DynInstPtr;
89 typedef typename Impl::CPUPol CPUPol;
90
91 typedef typename CPUPol::RenameMap RenameMap;
92 typedef typename CPUPol::ROB ROB;
93
94 typedef typename CPUPol::TimeStruct TimeStruct;
95 typedef typename CPUPol::FetchStruct FetchStruct;
96 typedef typename CPUPol::IEWStruct IEWStruct;
97 typedef typename CPUPol::RenameStruct RenameStruct;
98
99 typedef typename CPUPol::Fetch Fetch;
100 typedef typename CPUPol::IEW IEW;
101
102 typedef O3ThreadState<Impl> Thread;
103
104 /** Event class used to schedule a squash due to a trap (fault or
105 * interrupt) to happen on a specific cycle.
106 */
107 class TrapEvent : public Event {
108 private:
109 DefaultCommit<Impl> *commit;
110 ThreadID tid;
111
112 public:
113 TrapEvent(DefaultCommit<Impl> *_commit, ThreadID _tid);
114
115 void process();
116 const char *description() const;
117 };
118
119 /** Overall commit status. Used to determine if the CPU can deschedule
120 * itself due to a lack of activity.
121 */
122 enum CommitStatus{
123 Active,
124 Inactive
125 };
126
127 /** Individual thread status. */
128 enum ThreadStatus {
129 Running,
130 Idle,
131 ROBSquashing,
132 TrapPending,
133 FetchTrapPending,
134 SquashAfterPending, //< Committing instructions before a squash.
135 };
136
137 /** Commit policy for SMT mode. */
138 enum CommitPolicy {
139 Aggressive,
140 RoundRobin,
141 OldestReady
142 };
143
144 private:
145 /** Overall commit status. */
146 CommitStatus _status;
147 /** Next commit status, to be set at the end of the cycle. */
148 CommitStatus _nextStatus;
149 /** Per-thread status. */
150 ThreadStatus commitStatus[Impl::MaxThreads];
151 /** Commit policy used in SMT mode. */
152 CommitPolicy commitPolicy;
153
154 /** Probe Points. */
155 ProbePointArg<DynInstPtr> *ppCommit;
156 ProbePointArg<DynInstPtr> *ppCommitStall;
157 /** To probe when an instruction is squashed */
158 ProbePointArg<DynInstPtr> *ppSquash;
159
160 public:
161 /** Construct a DefaultCommit with the given parameters. */
162 DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params);
163
164 /** Returns the name of the DefaultCommit. */
165 std::string name() const;
166
167 /** Registers statistics. */
168 void regStats();
169
170 /** Registers probes. */
171 void regProbePoints();
172
173 /** Sets the list of threads. */
174 void setThreads(std::vector<Thread *> &threads);
175
176 /** Sets the main time buffer pointer, used for backwards communication. */
177 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
178
179 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
180
181 /** Sets the pointer to the queue coming from rename. */
182 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
183
184 /** Sets the pointer to the queue coming from IEW. */
185 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
186
187 /** Sets the pointer to the IEW stage. */
188 void setIEWStage(IEW *iew_stage);
189
190 /** The pointer to the IEW stage. Used solely to ensure that
191 * various events (traps, interrupts, syscalls) do not occur until
192 * all stores have written back.
193 */
194 IEW *iewStage;
195
196 /** Sets pointer to list of active threads. */
197 void setActiveThreads(std::list<ThreadID> *at_ptr);
198
199 /** Sets pointer to the commited state rename map. */
200 void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
201
202 /** Sets pointer to the ROB. */
203 void setROB(ROB *rob_ptr);
204
205 /** Initializes stage by sending back the number of free entries. */
206 void startupStage();
207
208 /** Initializes the draining of commit. */
209 void drain();
210
211 /** Resumes execution after draining. */
212 void drainResume();
213
214 /** Perform sanity checks after a drain. */
215 void drainSanityCheck() const;
216
217 /** Has the stage drained? */
218 bool isDrained() const;
219
220 /** Takes over from another CPU's thread. */
221 void takeOverFrom();
222
223 /** Deschedules a thread from scheduling */
224 void deactivateThread(ThreadID tid);
225
226 /** Ticks the commit stage, which tries to commit instructions. */
227 void tick();
228
229 /** Handles any squashes that are sent from IEW, and adds instructions
230 * to the ROB and tries to commit instructions.
231 */
232 void commit();
233
234 /** Returns the number of free ROB entries for a specific thread. */
235 size_t numROBFreeEntries(ThreadID tid);
236
237 /** Generates an event to schedule a squash due to a trap. */
238 void generateTrapEvent(ThreadID tid, Fault inst_fault);
239
240 /** Records that commit needs to initiate a squash due to an
241 * external state update through the TC.
242 */
243 void generateTCEvent(ThreadID tid);
244
245 private:
246 /** Updates the overall status of commit with the nextStatus, and
247 * tell the CPU if commit is active/inactive.
248 */
249 void updateStatus();
250
251 /** Returns if any of the threads have the number of ROB entries changed
252 * on this cycle. Used to determine if the number of free ROB entries needs
253 * to be sent back to previous stages.
254 */
255 bool changedROBEntries();
256
257 /** Squashes all in flight instructions. */
258 void squashAll(ThreadID tid);
259
260 /** Handles squashing due to a trap. */
261 void squashFromTrap(ThreadID tid);
262
263 /** Handles squashing due to an TC write. */
264 void squashFromTC(ThreadID tid);
265
266 /** Handles a squash from a squashAfter() request. */
267 void squashFromSquashAfter(ThreadID tid);
268
269 /**
270 * Handle squashing from instruction with SquashAfter set.
271 *
272 * This differs from the other squashes as it squashes following
273 * instructions instead of the current instruction and doesn't
274 * clean up various status bits about traps/tc writes
275 * pending. Since there might have been instructions committed by
276 * the commit stage before the squashing instruction was reached
277 * and we can't commit and squash in the same cycle, we have to
278 * squash in two steps:
279 *
280 * <ol>
281 * <li>Immediately set the commit status of the thread of
282 * SquashAfterPending. This forces the thread to stop
283 * committing instructions in this cycle. The last
284 * instruction to be committed in this cycle will be the
285 * SquashAfter instruction.
286 * <li>In the next cycle, commit() checks for the
287 * SquashAfterPending state and squashes <i>all</i>
288 * in-flight instructions. Since the SquashAfter instruction
289 * was the last instruction to be committed in the previous
290 * cycle, this causes all subsequent instructions to be
291 * squashed.
292 * </ol>
293 *
294 * @param tid ID of the thread to squash.
295 * @param head_inst Instruction that requested the squash.
296 */
297 void squashAfter(ThreadID tid, DynInstPtr &head_inst);
298
299 /** Handles processing an interrupt. */
300 void handleInterrupt();
301
302 /** Get fetch redirecting so we can handle an interrupt */
303 void propagateInterrupt();
304
305 /** Commits as many instructions as possible. */
306 void commitInsts();
307
308 /** Tries to commit the head ROB instruction passed in.
309 * @param head_inst The instruction to be committed.
310 */
311 bool commitHead(DynInstPtr &head_inst, unsigned inst_num);
312
313 /** Gets instructions from rename and inserts them into the ROB. */
314 void getInsts();
315
316 /** Marks completed instructions using information sent from IEW. */
317 void markCompletedInsts();
318
319 /** Gets the thread to commit, based on the SMT policy. */
320 ThreadID getCommittingThread();
321
322 /** Returns the thread ID to use based on a round robin policy. */
323 ThreadID roundRobin();
324
325 /** Returns the thread ID to use based on an oldest instruction policy. */
326 ThreadID oldestReady();
327
328 public:
329 /** Reads the PC of a specific thread. */
330 TheISA::PCState pcState(ThreadID tid) { return pc[tid]; }
331
332 /** Sets the PC of a specific thread. */
333 void pcState(const TheISA::PCState &val, ThreadID tid)
334 { pc[tid] = val; }
335
336 /** Returns the PC of a specific thread. */
337 Addr instAddr(ThreadID tid) { return pc[tid].instAddr(); }
338
339 /** Returns the next PC of a specific thread. */
340 Addr nextInstAddr(ThreadID tid) { return pc[tid].nextInstAddr(); }
341
342 /** Reads the micro PC of a specific thread. */
343 Addr microPC(ThreadID tid) { return pc[tid].microPC(); }
344
345 private:
346 /** Time buffer interface. */
347 TimeBuffer<TimeStruct> *timeBuffer;
348
349 /** Wire to write information heading to previous stages. */
350 typename TimeBuffer<TimeStruct>::wire toIEW;
351
352 /** Wire to read information from IEW (for ROB). */
353 typename TimeBuffer<TimeStruct>::wire robInfoFromIEW;
354
355 TimeBuffer<FetchStruct> *fetchQueue;
356
357 typename TimeBuffer<FetchStruct>::wire fromFetch;
358
359 /** IEW instruction queue interface. */
360 TimeBuffer<IEWStruct> *iewQueue;
361
362 /** Wire to read information from IEW queue. */
363 typename TimeBuffer<IEWStruct>::wire fromIEW;
364
365 /** Rename instruction queue interface, for ROB. */
366 TimeBuffer<RenameStruct> *renameQueue;
367
368 /** Wire to read information from rename queue. */
369 typename TimeBuffer<RenameStruct>::wire fromRename;
370
371 public:
372 /** ROB interface. */
373 ROB *rob;
374
375 private:
376 /** Pointer to O3CPU. */
377 O3CPU *cpu;
378
379 /** Vector of all of the threads. */
380 std::vector<Thread *> thread;
381
382 /** Records that commit has written to the time buffer this cycle. Used for
383 * the CPU to determine if it can deschedule itself if there is no activity.
384 */
385 bool wroteToTimeBuffer;
386
387 /** Records if the number of ROB entries has changed this cycle. If it has,
388 * then the number of free entries must be re-broadcast.
389 */
390 bool changedROBNumEntries[Impl::MaxThreads];
391
392 /** Records if a thread has to squash this cycle due to a trap. */
393 bool trapSquash[Impl::MaxThreads];
394
395 /** Records if a thread has to squash this cycle due to an XC write. */
396 bool tcSquash[Impl::MaxThreads];
397
398 /**
399 * Instruction passed to squashAfter().
400 *
401 * The squash after implementation needs to buffer the instruction
402 * that caused a squash since this needs to be passed to the fetch
403 * stage once squashing starts.
404 */
405 DynInstPtr squashAfterInst[Impl::MaxThreads];
406
407 /** Priority List used for Commit Policy */
408 std::list<ThreadID> priority_list;
409
410 /** IEW to Commit delay. */
411 const Cycles iewToCommitDelay;
412
413 /** Commit to IEW delay. */
414 const Cycles commitToIEWDelay;
415
416 /** Rename to ROB delay. */
417 const Cycles renameToROBDelay;
418
419 const Cycles fetchToCommitDelay;
420
421 /** Rename width, in instructions. Used so ROB knows how many
422 * instructions to get from the rename instruction queue.
423 */
424 const unsigned renameWidth;
425
426 /** Commit width, in instructions. */
427 const unsigned commitWidth;
428
429 /** Number of Reorder Buffers */
430 unsigned numRobs;
431
432 /** Number of Active Threads */
433 const ThreadID numThreads;
434
435 /** Is a drain pending? Commit is looking for an instruction boundary while
436 * there are no pending interrupts
437 */
438 bool drainPending;
439
440 /** Is a drain imminent? Commit has found an instruction boundary while no
441 * interrupts were present or in flight. This was the last architecturally
442 * committed instruction. Interrupts disabled and pipeline flushed.
443 * Waiting for structures to finish draining.
444 */
445 bool drainImminent;
446
447 /** The latency to handle a trap. Used when scheduling trap
448 * squash event.
449 */
450 const Cycles trapLatency;
451
452 /** The interrupt fault. */
453 Fault interrupt;
454
455 /** The commit PC state of each thread. Refers to the instruction that
456 * is currently being processed/committed.
457 */
458 TheISA::PCState pc[Impl::MaxThreads];
459
460 /** The sequence number of the youngest valid instruction in the ROB. */
461 InstSeqNum youngestSeqNum[Impl::MaxThreads];
462
463 /** The sequence number of the last commited instruction. */
464 InstSeqNum lastCommitedSeqNum[Impl::MaxThreads];
465
466 /** Records if there is a trap currently in flight. */
467 bool trapInFlight[Impl::MaxThreads];
468
469 /** Records if there were any stores committed this cycle. */
470 bool committedStores[Impl::MaxThreads];
471
472 /** Records if commit should check if the ROB is truly empty (see
473 commit_impl.hh). */
474 bool checkEmptyROB[Impl::MaxThreads];
475
476 /** Pointer to the list of active threads. */
477 std::list<ThreadID> *activeThreads;
478
479 /** Rename map interface. */
480 RenameMap *renameMap[Impl::MaxThreads];
481
482 /** True if last committed microop can be followed by an interrupt */
483 bool canHandleInterrupts;
484
485 /** Have we had an interrupt pending and then seen it de-asserted because
486 of a masking change? In this case the variable is set and the next time
487 interrupts are enabled and pending the pipeline will squash to avoid
488 a possible livelock senario. */
489 bool avoidQuiesceLiveLock;
490
491 /** Updates commit stats based on this instruction. */
492 void updateComInstStats(DynInstPtr &inst);
493
494 /** Stat for the total number of squashed instructions discarded by commit.
495 */
496 Stats::Scalar commitSquashedInsts;
497 /** Stat for the total number of times commit has had to stall due to a non-
498 * speculative instruction reaching the head of the ROB.
499 */
500 Stats::Scalar commitNonSpecStalls;
501 /** Stat for the total number of branch mispredicts that caused a squash. */
502 Stats::Scalar branchMispredicts;
503 /** Distribution of the number of committed instructions each cycle. */
504 Stats::Distribution numCommittedDist;
505
506 /** Total number of instructions committed. */
507 Stats::Vector instsCommitted;
508 /** Total number of ops (including micro ops) committed. */
509 Stats::Vector opsCommitted;
510 /** Total number of software prefetches committed. */
511 Stats::Vector statComSwp;
512 /** Stat for the total number of committed memory references. */
513 Stats::Vector statComRefs;
514 /** Stat for the total number of committed loads. */
515 Stats::Vector statComLoads;
516 /** Total number of committed memory barriers. */
517 Stats::Vector statComMembars;
518 /** Total number of committed branches. */
519 Stats::Vector statComBranches;
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