1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#include "cpu/checker/cpu_impl.hh"
44#include "cpu/o3/checker.hh"
45#include "params/O3Checker.hh"
46
47class MemObject;
48
49template
50class Checker<O3CPUImpl>;
51
52////////////////////////////////////////////////////////////////////////
53//
54// CheckerCPU Simulation Object
55//
56O3Checker *
57O3CheckerParams::create()
58{
59 O3Checker::Params *params = new O3Checker::Params();
60 params->name = name;
61 params->numThreads = numThreads;
62 params->max_insts_any_thread = 0;
63 params->max_insts_all_threads = 0;
64 params->max_loads_any_thread = 0;
65 params->max_loads_all_threads = 0;
66 params->exitOnError = exitOnError;
67 params->updateOnError = updateOnError;
68 params->warnOnlyOnLoadError = warnOnlyOnLoadError;
69 params->clock = clock;
70 params->tracer = tracer;
71 // Hack to touch all parameters. Consider not deriving Checker
72 // from BaseCPU..it's not really a CPU in the end.
73 Counter temp;
74 temp = max_insts_any_thread;
75 temp = max_insts_all_threads;
76 temp = max_loads_any_thread;
77 temp = max_loads_all_threads;
78 temp++;
79 Tick temp2 = progress_interval;
80 params->progress_interval = 0;
81 temp2++;
82
83 params->itb = itb;
84 params->dtb = dtb;
| 1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43#include "cpu/checker/cpu_impl.hh"
44#include "cpu/o3/checker.hh"
45#include "params/O3Checker.hh"
46
47class MemObject;
48
49template
50class Checker<O3CPUImpl>;
51
52////////////////////////////////////////////////////////////////////////
53//
54// CheckerCPU Simulation Object
55//
56O3Checker *
57O3CheckerParams::create()
58{
59 O3Checker::Params *params = new O3Checker::Params();
60 params->name = name;
61 params->numThreads = numThreads;
62 params->max_insts_any_thread = 0;
63 params->max_insts_all_threads = 0;
64 params->max_loads_any_thread = 0;
65 params->max_loads_all_threads = 0;
66 params->exitOnError = exitOnError;
67 params->updateOnError = updateOnError;
68 params->warnOnlyOnLoadError = warnOnlyOnLoadError;
69 params->clock = clock;
70 params->tracer = tracer;
71 // Hack to touch all parameters. Consider not deriving Checker
72 // from BaseCPU..it's not really a CPU in the end.
73 Counter temp;
74 temp = max_insts_any_thread;
75 temp = max_insts_all_threads;
76 temp = max_loads_any_thread;
77 temp = max_loads_all_threads;
78 temp++;
79 Tick temp2 = progress_interval;
80 params->progress_interval = 0;
81 temp2++;
82
83 params->itb = itb;
84 params->dtb = dtb;
|