SConscript (9919:803903a8dac1) | SConscript (10426:cba563d00376) |
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1# -*- mode:python -*- 2 3# Copyright (c) 2006 The Regents of The University of Michigan 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright --- 18 unchanged lines hidden (view full) --- 27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28# 29# Authors: Nathan Binkert 30 31import sys 32 33Import('*') 34 | 1# -*- mode:python -*- 2 3# Copyright (c) 2006 The Regents of The University of Michigan 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright --- 18 unchanged lines hidden (view full) --- 27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28# 29# Authors: Nathan Binkert 30 31import sys 32 33Import('*') 34 |
35if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']: 36 DebugFlag('CommitRate') 37 DebugFlag('IEW') 38 DebugFlag('IQ') 39 | |
40if 'O3CPU' in env['CPU_MODELS']: 41 SimObject('FUPool.py') 42 SimObject('FuncUnitConfig.py') 43 SimObject('O3CPU.py') 44 45 Source('base_dyn_inst.cc') 46 Source('commit.cc') 47 Source('cpu.cc') --- 11 unchanged lines hidden (view full) --- 59 Source('regfile.cc') 60 Source('rename.cc') 61 Source('rename_map.cc') 62 Source('rob.cc') 63 Source('scoreboard.cc') 64 Source('store_set.cc') 65 Source('thread_context.cc') 66 | 35if 'O3CPU' in env['CPU_MODELS']: 36 SimObject('FUPool.py') 37 SimObject('FuncUnitConfig.py') 38 SimObject('O3CPU.py') 39 40 Source('base_dyn_inst.cc') 41 Source('commit.cc') 42 Source('cpu.cc') --- 11 unchanged lines hidden (view full) --- 54 Source('regfile.cc') 55 Source('rename.cc') 56 Source('rename_map.cc') 57 Source('rob.cc') 58 Source('scoreboard.cc') 59 Source('store_set.cc') 60 Source('thread_context.cc') 61 |
62 DebugFlag('CommitRate') 63 DebugFlag('IEW') 64 DebugFlag('IQ') |
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67 DebugFlag('LSQ') 68 DebugFlag('LSQUnit') 69 DebugFlag('MemDepUnit') 70 DebugFlag('O3CPU') 71 DebugFlag('ROB') 72 DebugFlag('Rename') 73 DebugFlag('Scoreboard') 74 DebugFlag('StoreSet') 75 DebugFlag('Writeback') 76 77 CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', 78 'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit', 79 'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ]) 80 81 SimObject('O3Checker.py') 82 Source('checker.cc') | 65 DebugFlag('LSQ') 66 DebugFlag('LSQUnit') 67 DebugFlag('MemDepUnit') 68 DebugFlag('O3CPU') 69 DebugFlag('ROB') 70 DebugFlag('Rename') 71 DebugFlag('Scoreboard') 72 DebugFlag('StoreSet') 73 DebugFlag('Writeback') 74 75 CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', 76 'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit', 77 'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ]) 78 79 SimObject('O3Checker.py') 80 Source('checker.cc') |