SConscript (6184:c947586b3d9e) SConscript (8335:9228e00459d4)
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

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28#
29# Authors: Nathan Binkert
30
31import sys
32
33Import('*')
34
35if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

--- 19 unchanged lines hidden (view full) ---

28#
29# Authors: Nathan Binkert
30
31import sys
32
33Import('*')
34
35if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
36 TraceFlag('CommitRate')
37 TraceFlag('IEW')
38 TraceFlag('IQ')
36 DebugFlag('CommitRate')
37 DebugFlag('IEW')
38 DebugFlag('IQ')
39
40if 'O3CPU' in env['CPU_MODELS']:
41 SimObject('FUPool.py')
42 SimObject('FuncUnitConfig.py')
43 SimObject('O3CPU.py')
44
45 Source('base_dyn_inst.cc')
46 Source('bpred_unit.cc')

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59 Source('mem_dep_unit.cc')
60 Source('rename.cc')
61 Source('rename_map.cc')
62 Source('rob.cc')
63 Source('scoreboard.cc')
64 Source('store_set.cc')
65 Source('thread_context.cc')
66
39
40if 'O3CPU' in env['CPU_MODELS']:
41 SimObject('FUPool.py')
42 SimObject('FuncUnitConfig.py')
43 SimObject('O3CPU.py')
44
45 Source('base_dyn_inst.cc')
46 Source('bpred_unit.cc')

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59 Source('mem_dep_unit.cc')
60 Source('rename.cc')
61 Source('rename_map.cc')
62 Source('rob.cc')
63 Source('scoreboard.cc')
64 Source('store_set.cc')
65 Source('thread_context.cc')
66
67 TraceFlag('LSQ')
68 TraceFlag('LSQUnit')
69 TraceFlag('MemDepUnit')
70 TraceFlag('O3CPU')
71 TraceFlag('ROB')
72 TraceFlag('Rename')
73 TraceFlag('Scoreboard')
74 TraceFlag('StoreSet')
75 TraceFlag('Writeback')
67 DebugFlag('LSQ')
68 DebugFlag('LSQUnit')
69 DebugFlag('MemDepUnit')
70 DebugFlag('O3CPU')
71 DebugFlag('ROB')
72 DebugFlag('Rename')
73 DebugFlag('Scoreboard')
74 DebugFlag('StoreSet')
75 DebugFlag('Writeback')
76
77 CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit',
78 'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit',
79 'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ])
80
81 if env['USE_CHECKER']:
82 SimObject('O3Checker.py')
83 Source('checker_builder.cc')
76
77 CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit',
78 'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit',
79 'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ])
80
81 if env['USE_CHECKER']:
82 SimObject('O3Checker.py')
83 Source('checker_builder.cc')