SConscript (5597:e2983d751be4) | SConscript (6184:c947586b3d9e) |
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1# -*- mode:python -*- 2 3# Copyright (c) 2006 The Regents of The University of Michigan 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright --- 19 unchanged lines hidden (view full) --- 28# 29# Authors: Nathan Binkert 30 31import sys 32 33Import('*') 34 35if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']: | 1# -*- mode:python -*- 2 3# Copyright (c) 2006 The Regents of The University of Michigan 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright --- 19 unchanged lines hidden (view full) --- 28# 29# Authors: Nathan Binkert 30 31import sys 32 33Import('*') 34 35if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']: |
36 Source('2bit_local_pred.cc') 37 Source('btb.cc') 38 Source('ras.cc') 39 Source('tournament_pred.cc') 40 | |
41 TraceFlag('CommitRate') 42 TraceFlag('IEW') 43 TraceFlag('IQ') 44 45if 'O3CPU' in env['CPU_MODELS']: 46 SimObject('FUPool.py') 47 SimObject('FuncUnitConfig.py') 48 SimObject('O3CPU.py') --- 15 unchanged lines hidden (view full) --- 64 Source('mem_dep_unit.cc') 65 Source('rename.cc') 66 Source('rename_map.cc') 67 Source('rob.cc') 68 Source('scoreboard.cc') 69 Source('store_set.cc') 70 Source('thread_context.cc') 71 | 36 TraceFlag('CommitRate') 37 TraceFlag('IEW') 38 TraceFlag('IQ') 39 40if 'O3CPU' in env['CPU_MODELS']: 41 SimObject('FUPool.py') 42 SimObject('FuncUnitConfig.py') 43 SimObject('O3CPU.py') --- 15 unchanged lines hidden (view full) --- 59 Source('mem_dep_unit.cc') 60 Source('rename.cc') 61 Source('rename_map.cc') 62 Source('rob.cc') 63 Source('scoreboard.cc') 64 Source('store_set.cc') 65 Source('thread_context.cc') 66 |
72 TraceFlag('FreeList') | |
73 TraceFlag('LSQ') 74 TraceFlag('LSQUnit') 75 TraceFlag('MemDepUnit') 76 TraceFlag('O3CPU') 77 TraceFlag('ROB') 78 TraceFlag('Rename') 79 TraceFlag('Scoreboard') 80 TraceFlag('StoreSet') 81 TraceFlag('Writeback') 82 83 CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', 84 'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit', 85 'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ]) 86 87 if env['USE_CHECKER']: 88 SimObject('O3Checker.py') 89 Source('checker_builder.cc') | 67 TraceFlag('LSQ') 68 TraceFlag('LSQUnit') 69 TraceFlag('MemDepUnit') 70 TraceFlag('O3CPU') 71 TraceFlag('ROB') 72 TraceFlag('Rename') 73 TraceFlag('Scoreboard') 74 TraceFlag('StoreSet') 75 TraceFlag('Writeback') 76 77 CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit', 78 'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit', 79 'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ]) 80 81 if env['USE_CHECKER']: 82 SimObject('O3Checker.py') 83 Source('checker_builder.cc') |