SConscript (5192:582e583f8e7e) SConscript (5597:e2983d751be4)
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

--- 37 unchanged lines hidden (view full) ---

46 SimObject('FUPool.py')
47 SimObject('FuncUnitConfig.py')
48 SimObject('O3CPU.py')
49
50 Source('base_dyn_inst.cc')
51 Source('bpred_unit.cc')
52 Source('commit.cc')
53 Source('cpu.cc')
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

--- 37 unchanged lines hidden (view full) ---

46 SimObject('FUPool.py')
47 SimObject('FuncUnitConfig.py')
48 SimObject('O3CPU.py')
49
50 Source('base_dyn_inst.cc')
51 Source('bpred_unit.cc')
52 Source('commit.cc')
53 Source('cpu.cc')
54 Source('cpu_builder.cc')
54 Source('decode.cc')
55 Source('decode.cc')
56 Source('dyn_inst.cc')
55 Source('fetch.cc')
56 Source('free_list.cc')
57 Source('fu_pool.cc')
58 Source('iew.cc')
59 Source('inst_queue.cc')
60 Source('lsq.cc')
61 Source('lsq_unit.cc')
62 Source('mem_dep_unit.cc')
63 Source('rename.cc')
64 Source('rename_map.cc')
65 Source('rob.cc')
66 Source('scoreboard.cc')
67 Source('store_set.cc')
57 Source('fetch.cc')
58 Source('free_list.cc')
59 Source('fu_pool.cc')
60 Source('iew.cc')
61 Source('inst_queue.cc')
62 Source('lsq.cc')
63 Source('lsq_unit.cc')
64 Source('mem_dep_unit.cc')
65 Source('rename.cc')
66 Source('rename_map.cc')
67 Source('rob.cc')
68 Source('scoreboard.cc')
69 Source('store_set.cc')
70 Source('thread_context.cc')
68
69 TraceFlag('FreeList')
70 TraceFlag('LSQ')
71 TraceFlag('LSQUnit')
72 TraceFlag('MemDepUnit')
73 TraceFlag('O3CPU')
74 TraceFlag('ROB')
75 TraceFlag('Rename')
76 TraceFlag('Scoreboard')
77 TraceFlag('StoreSet')
78 TraceFlag('Writeback')
79
80 CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit',
81 'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit',
82 'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ])
83
71
72 TraceFlag('FreeList')
73 TraceFlag('LSQ')
74 TraceFlag('LSQUnit')
75 TraceFlag('MemDepUnit')
76 TraceFlag('O3CPU')
77 TraceFlag('ROB')
78 TraceFlag('Rename')
79 TraceFlag('Scoreboard')
80 TraceFlag('StoreSet')
81 TraceFlag('Writeback')
82
83 CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit',
84 'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit',
85 'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ])
86
84 if env['TARGET_ISA'] == 'alpha':
85 Source('alpha/cpu.cc')
86 Source('alpha/cpu_builder.cc')
87 Source('alpha/dyn_inst.cc')
88 Source('alpha/thread_context.cc')
89 elif env['TARGET_ISA'] == 'mips':
90 Source('mips/cpu.cc')
91 Source('mips/cpu_builder.cc')
92 Source('mips/dyn_inst.cc')
93 Source('mips/thread_context.cc')
94 elif env['TARGET_ISA'] == 'sparc':
95 Source('sparc/cpu.cc')
96 Source('sparc/cpu_builder.cc')
97 Source('sparc/dyn_inst.cc')
98 Source('sparc/thread_context.cc')
99 else:
100 sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA'])
101
102 if env['USE_CHECKER']:
103 SimObject('O3Checker.py')
104 Source('checker_builder.cc')
87 if env['USE_CHECKER']:
88 SimObject('O3Checker.py')
89 Source('checker_builder.cc')