SConscript (4497:17e34dbcc8b3) SConscript (5192:582e583f8e7e)
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

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27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29# Authors: Nathan Binkert
30
31import sys
32
33Import('*')
34
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

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27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29# Authors: Nathan Binkert
30
31import sys
32
33Import('*')
34
35if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
36 Source('2bit_local_pred.cc')
37 Source('btb.cc')
38 Source('ras.cc')
39 Source('tournament_pred.cc')
40
41 TraceFlag('CommitRate')
42 TraceFlag('IEW')
43 TraceFlag('IQ')
44
35if 'O3CPU' in env['CPU_MODELS']:
36 SimObject('FUPool.py')
37 SimObject('FuncUnitConfig.py')
38 SimObject('O3CPU.py')
39
40 Source('base_dyn_inst.cc')
41 Source('bpred_unit.cc')
42 Source('commit.cc')

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51 Source('lsq_unit.cc')
52 Source('mem_dep_unit.cc')
53 Source('rename.cc')
54 Source('rename_map.cc')
55 Source('rob.cc')
56 Source('scoreboard.cc')
57 Source('store_set.cc')
58
45if 'O3CPU' in env['CPU_MODELS']:
46 SimObject('FUPool.py')
47 SimObject('FuncUnitConfig.py')
48 SimObject('O3CPU.py')
49
50 Source('base_dyn_inst.cc')
51 Source('bpred_unit.cc')
52 Source('commit.cc')

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61 Source('lsq_unit.cc')
62 Source('mem_dep_unit.cc')
63 Source('rename.cc')
64 Source('rename_map.cc')
65 Source('rob.cc')
66 Source('scoreboard.cc')
67 Source('store_set.cc')
68
69 TraceFlag('FreeList')
70 TraceFlag('LSQ')
71 TraceFlag('LSQUnit')
72 TraceFlag('MemDepUnit')
73 TraceFlag('O3CPU')
74 TraceFlag('ROB')
75 TraceFlag('Rename')
76 TraceFlag('Scoreboard')
77 TraceFlag('StoreSet')
78 TraceFlag('Writeback')
79
80 CompoundFlag('O3CPUAll', [ 'Fetch', 'Decode', 'Rename', 'IEW', 'Commit',
81 'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit',
82 'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ])
83
59 if env['TARGET_ISA'] == 'alpha':
60 Source('alpha/cpu.cc')
61 Source('alpha/cpu_builder.cc')
62 Source('alpha/dyn_inst.cc')
63 Source('alpha/thread_context.cc')
64 elif env['TARGET_ISA'] == 'mips':
65 Source('mips/cpu.cc')
66 Source('mips/cpu_builder.cc')

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72 Source('sparc/dyn_inst.cc')
73 Source('sparc/thread_context.cc')
74 else:
75 sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA'])
76
77 if env['USE_CHECKER']:
78 SimObject('O3Checker.py')
79 Source('checker_builder.cc')
84 if env['TARGET_ISA'] == 'alpha':
85 Source('alpha/cpu.cc')
86 Source('alpha/cpu_builder.cc')
87 Source('alpha/dyn_inst.cc')
88 Source('alpha/thread_context.cc')
89 elif env['TARGET_ISA'] == 'mips':
90 Source('mips/cpu.cc')
91 Source('mips/cpu_builder.cc')

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97 Source('sparc/dyn_inst.cc')
98 Source('sparc/thread_context.cc')
99 else:
100 sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA'])
101
102 if env['USE_CHECKER']:
103 SimObject('O3Checker.py')
104 Source('checker_builder.cc')
80
81if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']:
82 Source('2bit_local_pred.cc')
83 Source('btb.cc')
84 Source('ras.cc')
85 Source('tournament_pred.cc')
86