SConscript (4202:f7a05daec670) | SConscript (4486:aaeb03a8a6e1) |
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1# -*- mode:python -*- 2 3# Copyright (c) 2006 The Regents of The University of Michigan 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright --- 19 unchanged lines hidden (view full) --- 28# 29# Authors: Nathan Binkert 30 31import sys 32 33Import('*') 34 35if 'O3CPU' in env['CPU_MODELS']: | 1# -*- mode:python -*- 2 3# Copyright (c) 2006 The Regents of The University of Michigan 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright --- 19 unchanged lines hidden (view full) --- 28# 29# Authors: Nathan Binkert 30 31import sys 32 33Import('*') 34 35if 'O3CPU' in env['CPU_MODELS']: |
36 SimObject('FUPool.py') 37 SimObject('FuncUnitConfig.py') 38 SimObject('O3CPU.py') 39 |
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36 Source('base_dyn_inst.cc') 37 Source('bpred_unit.cc') 38 Source('commit.cc') 39 Source('cpu.cc') 40 Source('decode.cc') 41 Source('fetch.cc') 42 Source('free_list.cc') 43 Source('fu_pool.cc') --- 22 unchanged lines hidden (view full) --- 66 Source('sparc/cpu.cc') 67 Source('sparc/cpu_builder.cc') 68 Source('sparc/dyn_inst.cc') 69 Source('sparc/thread_context.cc') 70 else: 71 sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA']) 72 73 if env['USE_CHECKER']: | 40 Source('base_dyn_inst.cc') 41 Source('bpred_unit.cc') 42 Source('commit.cc') 43 Source('cpu.cc') 44 Source('decode.cc') 45 Source('fetch.cc') 46 Source('free_list.cc') 47 Source('fu_pool.cc') --- 22 unchanged lines hidden (view full) --- 70 Source('sparc/cpu.cc') 71 Source('sparc/cpu_builder.cc') 72 Source('sparc/dyn_inst.cc') 73 Source('sparc/thread_context.cc') 74 else: 75 sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA']) 76 77 if env['USE_CHECKER']: |
78 SimObject('m5/objects/O3Checker.py') |
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74 Source('checker_builder.cc') 75 76if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']: 77 Source('2bit_local_pred.cc') 78 Source('btb.cc') 79 Source('ras.cc') 80 Source('tournament_pred.cc') 81 | 79 Source('checker_builder.cc') 80 81if 'O3CPU' in env['CPU_MODELS'] or 'OzoneCPU' in env['CPU_MODELS']: 82 Source('2bit_local_pred.cc') 83 Source('btb.cc') 84 Source('ras.cc') 85 Source('tournament_pred.cc') 86 |