53a54
> Source('cpu_builder.cc')
54a56
> Source('dyn_inst.cc')
67a70
> Source('thread_context.cc')
84,101d86
< if env['TARGET_ISA'] == 'alpha':
< Source('alpha/cpu.cc')
< Source('alpha/cpu_builder.cc')
< Source('alpha/dyn_inst.cc')
< Source('alpha/thread_context.cc')
< elif env['TARGET_ISA'] == 'mips':
< Source('mips/cpu.cc')
< Source('mips/cpu_builder.cc')
< Source('mips/dyn_inst.cc')
< Source('mips/thread_context.cc')
< elif env['TARGET_ISA'] == 'sparc':
< Source('sparc/cpu.cc')
< Source('sparc/cpu_builder.cc')
< Source('sparc/dyn_inst.cc')
< Source('sparc/thread_context.cc')
< else:
< sys.exit('O3 CPU does not support the \'%s\' ISA' % env['TARGET_ISA'])
<