O3CPU.py (9518:8faae62af8c3) O3CPU.py (9849:603e2ed487f3)
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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120 smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy")
121 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter")
122 smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy")
123 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter")
124 smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy")
125 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
126 smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
127
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 111 unchanged lines hidden (view full) ---

120 smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy")
121 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter")
122 smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy")
123 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter")
124 smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy")
125 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
126 smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
127
128 branchPred = BranchPredictor(numThreads = Parent.numThreads)
128 branchPred = Param.BranchPredictor(BranchPredictor(numThreads =
129 Parent.numThreads),
130 "Branch Predictor")
129 needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86',
130 "Enable TSO Memory model")
131
132 def addCheckerCpu(self):
133 if buildEnv['TARGET_ISA'] in ['arm']:
134 from ArmTLB import ArmTLB
135
136 self.checker = O3Checker(workload=self.workload,
137 exitOnError=False,
138 updateOnError=True,
139 warnOnlyOnLoadError=True)
140 self.checker.itb = ArmTLB(size = self.itb.size)
141 self.checker.dtb = ArmTLB(size = self.dtb.size)
142 self.checker.cpu_id = self.cpu_id
143
144 else:
145 print "ERROR: Checker only supported under ARM ISA!"
146 exit(1)
131 needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86',
132 "Enable TSO Memory model")
133
134 def addCheckerCpu(self):
135 if buildEnv['TARGET_ISA'] in ['arm']:
136 from ArmTLB import ArmTLB
137
138 self.checker = O3Checker(workload=self.workload,
139 exitOnError=False,
140 updateOnError=True,
141 warnOnlyOnLoadError=True)
142 self.checker.itb = ArmTLB(size = self.itb.size)
143 self.checker.dtb = ArmTLB(size = self.dtb.size)
144 self.checker.cpu_id = self.cpu_id
145
146 else:
147 print "ERROR: Checker only supported under ARM ISA!"
148 exit(1)