O3CPU.py (9341:a0eff1e9c773) | O3CPU.py (9480:d059f8a95a42) |
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1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 18 unchanged lines hidden (view full) --- 27# Authors: Kevin Lim 28 29from m5.defines import buildEnv 30from m5.params import * 31from m5.proxy import * 32from BaseCPU import BaseCPU 33from FUPool import * 34from O3Checker import O3Checker | 1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 18 unchanged lines hidden (view full) --- 27# Authors: Kevin Lim 28 29from m5.defines import buildEnv 30from m5.params import * 31from m5.proxy import * 32from BaseCPU import BaseCPU 33from FUPool import * 34from O3Checker import O3Checker |
35from BranchPredictor import BranchPredictor |
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35 36class DerivO3CPU(BaseCPU): 37 type = 'DerivO3CPU' 38 cxx_header = 'cpu/o3/deriv.hh' 39 40 activity = Param.Unsigned(0, "Initial count") 41 42 cachePorts = Param.Unsigned(200, "Cache Ports") --- 36 unchanged lines hidden (view full) --- 79 commitWidth = Param.Unsigned(8, "Commit width") 80 squashWidth = Param.Unsigned(8, "Squash width") 81 trapLatency = Param.Cycles(13, "Trap latency") 82 fetchTrapLatency = Param.Cycles(1, "Fetch trap latency") 83 84 backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") 85 forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") 86 | 36 37class DerivO3CPU(BaseCPU): 38 type = 'DerivO3CPU' 39 cxx_header = 'cpu/o3/deriv.hh' 40 41 activity = Param.Unsigned(0, "Initial count") 42 43 cachePorts = Param.Unsigned(200, "Cache Ports") --- 36 unchanged lines hidden (view full) --- 80 commitWidth = Param.Unsigned(8, "Commit width") 81 squashWidth = Param.Unsigned(8, "Squash width") 82 trapLatency = Param.Cycles(13, "Trap latency") 83 fetchTrapLatency = Param.Cycles(1, "Fetch trap latency") 84 85 backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") 86 forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") 87 |
87 predType = Param.String("tournament", "Branch predictor type ('local', 'tournament')") 88 localPredictorSize = Param.Unsigned(2048, "Size of local predictor") 89 localCtrBits = Param.Unsigned(2, "Bits per counter") 90 localHistoryTableSize = Param.Unsigned(2048, "Size of local history table") 91 localHistoryBits = Param.Unsigned(11, "Bits for the local history") 92 globalPredictorSize = Param.Unsigned(8192, "Size of global predictor") 93 globalCtrBits = Param.Unsigned(2, "Bits per counter") 94 globalHistoryBits = Param.Unsigned(13, "Bits of history") 95 choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor") 96 choiceCtrBits = Param.Unsigned(2, "Bits of choice counters") 97 98 BTBEntries = Param.Unsigned(4096, "Number of BTB entries") 99 BTBTagSize = Param.Unsigned(16, "Size of the BTB tags, in bits") 100 101 RASSize = Param.Unsigned(16, "RAS size") 102 | |
103 LQEntries = Param.Unsigned(32, "Number of load queue entries") 104 SQEntries = Param.Unsigned(32, "Number of store queue entries") 105 LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check") 106 LSQCheckLoads = Param.Bool(True, 107 "Should dependency violations be checked for loads & stores or just stores") 108 store_set_clear_period = Param.Unsigned(250000, 109 "Number of load/store insts before the dep predictor should be invalidated") 110 LFSTSize = Param.Unsigned(1024, "Last fetched store table size") 111 SSITSize = Param.Unsigned(1024, "Store set ID table size") 112 113 numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); 114 115 numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") 116 numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " 117 "registers") 118 numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 119 numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 120 | 88 LQEntries = Param.Unsigned(32, "Number of load queue entries") 89 SQEntries = Param.Unsigned(32, "Number of store queue entries") 90 LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check") 91 LSQCheckLoads = Param.Bool(True, 92 "Should dependency violations be checked for loads & stores or just stores") 93 store_set_clear_period = Param.Unsigned(250000, 94 "Number of load/store insts before the dep predictor should be invalidated") 95 LFSTSize = Param.Unsigned(1024, "Last fetched store table size") 96 SSITSize = Param.Unsigned(1024, "Store set ID table size") 97 98 numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); 99 100 numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") 101 numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " 102 "registers") 103 numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 104 numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 105 |
121 instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by") 122 | |
123 smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") 124 smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy") 125 smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy") 126 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") 127 smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy") 128 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 129 smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy") 130 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 131 smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") 132 | 106 smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") 107 smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy") 108 smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy") 109 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") 110 smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy") 111 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 112 smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy") 113 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 114 smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") 115 |
116 branchPred = BranchPredictor(numThreads = Parent.numThreads) |
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133 needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', 134 "Enable TSO Memory model") 135 136 def addCheckerCpu(self): 137 if buildEnv['TARGET_ISA'] in ['arm']: 138 from ArmTLB import ArmTLB 139 140 self.checker = O3Checker(workload=self.workload, 141 exitOnError=False, 142 updateOnError=True, 143 warnOnlyOnLoadError=True) 144 self.checker.itb = ArmTLB(size = self.itb.size) 145 self.checker.dtb = ArmTLB(size = self.dtb.size) 146 self.checker.cpu_id = self.cpu_id 147 148 else: 149 print "ERROR: Checker only supported under ARM ISA!" 150 exit(1) | 117 needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', 118 "Enable TSO Memory model") 119 120 def addCheckerCpu(self): 121 if buildEnv['TARGET_ISA'] in ['arm']: 122 from ArmTLB import ArmTLB 123 124 self.checker = O3Checker(workload=self.workload, 125 exitOnError=False, 126 updateOnError=True, 127 warnOnlyOnLoadError=True) 128 self.checker.itb = ArmTLB(size = self.itb.size) 129 self.checker.dtb = ArmTLB(size = self.dtb.size) 130 self.checker.cpu_id = self.cpu_id 131 132 else: 133 print "ERROR: Checker only supported under ARM ISA!" 134 exit(1) |