O3CPU.py (8809:bb10807da889) | O3CPU.py (8887:20ea02da9c53) |
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1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 17 unchanged lines hidden (view full) --- 26# 27# Authors: Kevin Lim 28 29from m5.defines import buildEnv 30from m5.params import * 31from m5.proxy import * 32from BaseCPU import BaseCPU 33from FUPool import * | 1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 17 unchanged lines hidden (view full) --- 26# 27# Authors: Kevin Lim 28 29from m5.defines import buildEnv 30from m5.params import * 31from m5.proxy import * 32from BaseCPU import BaseCPU 33from FUPool import * |
34from O3Checker import O3Checker |
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34 | 35 |
35if buildEnv['USE_CHECKER']: 36 from O3Checker import O3Checker 37 | |
38class DerivO3CPU(BaseCPU): 39 type = 'DerivO3CPU' 40 activity = Param.Unsigned(0, "Initial count") 41 | 36class DerivO3CPU(BaseCPU): 37 type = 'DerivO3CPU' 38 activity = Param.Unsigned(0, "Initial count") 39 |
42 if buildEnv['USE_CHECKER']: 43 # FIXME: Shouldn't need to derefernce Parent.workload 44 # Somewhere in the param parsing code 45 # src/python/m5/params.py is and error that 46 # has trouble converting the workload parameter properly. 47 checker = Param.BaseCPU(O3Checker(workload=Parent.workload[0], 48 exitOnError=False, 49 updateOnError=True, 50 warnOnlyOnLoadError=True), 51 "checker") 52 checker.itb = Parent.itb 53 checker.dtb = Parent.dtb 54 | |
55 cachePorts = Param.Unsigned(200, "Cache Ports") 56 57 decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay") 58 renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay") 59 iewToFetchDelay = Param.Unsigned(1, "Issue/Execute/Writeback to fetch " 60 "delay") 61 commitToFetchDelay = Param.Unsigned(1, "Commit to fetch delay") 62 fetchWidth = Param.Unsigned(8, "Fetch width") --- 77 unchanged lines hidden (view full) --- 140 smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy") 141 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 142 smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy") 143 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 144 smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") 145 146 needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', 147 "Enable TSO Memory model") | 40 cachePorts = Param.Unsigned(200, "Cache Ports") 41 42 decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay") 43 renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay") 44 iewToFetchDelay = Param.Unsigned(1, "Issue/Execute/Writeback to fetch " 45 "delay") 46 commitToFetchDelay = Param.Unsigned(1, "Commit to fetch delay") 47 fetchWidth = Param.Unsigned(8, "Fetch width") --- 77 unchanged lines hidden (view full) --- 125 smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy") 126 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 127 smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy") 128 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 129 smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") 130 131 needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', 132 "Enable TSO Memory model") |
133 134 def addCheckerCpu(self): 135 if buildEnv['TARGET_ISA'] in ['arm']: 136 from ArmTLB import ArmTLB 137 138 self.checker = O3Checker(workload=self.workload, 139 exitOnError=False, 140 updateOnError=True, 141 warnOnlyOnLoadError=True) 142 self.checker.itb = ArmTLB(size = self.itb.size) 143 self.checker.dtb = ArmTLB(size = self.dtb.size) 144 145 else: 146 print "ERROR: Checker only supported under ARM ISA!" 147 exit(1) |
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