O3CPU.py (8519:ef35ce2bd73f) O3CPU.py (8631:8c038d4cd210)
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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141 smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy")
142 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter")
143 smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy")
144 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter")
145 smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy")
146 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
147 smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
148
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 132 unchanged lines hidden (view full) ---

141 smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy")
142 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter")
143 smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy")
144 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter")
145 smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy")
146 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
147 smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
148
149 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
150 BaseCPU.addPrivateSplitL1Caches(self, ic, dc, iwc, dwc)
151 self.icache.tgts_per_mshr = 20
152 self.dcache.tgts_per_mshr = 20