O3CPU.py (6654:4c84e771cca7) O3CPU.py (7868:6029008db669)
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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136 smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy")
137 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter")
138 smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy")
139 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter")
140 smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy")
141 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
142 smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
143
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 127 unchanged lines hidden (view full) ---

136 smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy")
137 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter")
138 smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy")
139 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter")
140 smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy")
141 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
142 smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
143
144 def addPrivateSplitL1Caches(self, ic, dc):
145 BaseCPU.addPrivateSplitL1Caches(self, ic, dc)
144 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
145 BaseCPU.addPrivateSplitL1Caches(self, ic, dc, iwc, dwc)
146 self.icache.tgts_per_mshr = 20
147 self.dcache.tgts_per_mshr = 20
146 self.icache.tgts_per_mshr = 20
147 self.dcache.tgts_per_mshr = 20