O3CPU.py (5236:0050ad4fb3ef) | O3CPU.py (5529:9ae69b9cd7fd) |
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1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 24 unchanged lines hidden (view full) --- 33from FUPool import * 34 35if build_env['USE_CHECKER']: 36 from O3Checker import O3Checker 37 38class DerivO3CPU(BaseCPU): 39 type = 'DerivO3CPU' 40 activity = Param.Unsigned(0, "Initial count") | 1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 24 unchanged lines hidden (view full) --- 33from FUPool import * 34 35if build_env['USE_CHECKER']: 36 from O3Checker import O3Checker 37 38class DerivO3CPU(BaseCPU): 39 type = 'DerivO3CPU' 40 activity = Param.Unsigned(0, "Initial count") |
41 numThreads = Param.Unsigned(1, "number of HW thread contexts") | |
42 | 41 |
43 if build_env['FULL_SYSTEM']: 44 profile = Param.Latency('0ns', "trace the kernel stack") | |
45 if build_env['USE_CHECKER']: 46 if not build_env['FULL_SYSTEM']: 47 checker = Param.BaseCPU(O3Checker(workload=Parent.workload, 48 exitOnError=False, 49 updateOnError=True, 50 warnOnlyOnLoadError=False), 51 "checker") 52 else: --- 76 unchanged lines hidden (view full) --- 129 numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") 130 numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " 131 "registers") 132 numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 133 numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 134 135 instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by") 136 | 42 if build_env['USE_CHECKER']: 43 if not build_env['FULL_SYSTEM']: 44 checker = Param.BaseCPU(O3Checker(workload=Parent.workload, 45 exitOnError=False, 46 updateOnError=True, 47 warnOnlyOnLoadError=False), 48 "checker") 49 else: --- 76 unchanged lines hidden (view full) --- 126 numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") 127 numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " 128 "registers") 129 numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 130 numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 131 132 instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by") 133 |
137 function_trace = Param.Bool(False, "Enable function trace") 138 function_trace_start = Param.Tick(0, "Cycle to start function trace") 139 | |
140 smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") 141 smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy") 142 smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy") 143 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") 144 smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy") 145 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 146 smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy") 147 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 148 smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") 149 150 def addPrivateSplitL1Caches(self, ic, dc): 151 BaseCPU.addPrivateSplitL1Caches(self, ic, dc) 152 self.icache.tgts_per_mshr = 20 153 self.dcache.tgts_per_mshr = 20 | 134 smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") 135 smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy") 136 smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy") 137 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") 138 smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy") 139 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 140 smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy") 141 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 142 smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") 143 144 def addPrivateSplitL1Caches(self, ic, dc): 145 BaseCPU.addPrivateSplitL1Caches(self, ic, dc) 146 self.icache.tgts_per_mshr = 20 147 self.dcache.tgts_per_mshr = 20 |