O3CPU.py (4597:063f25d13229) O3CPU.py (4997:e7380529bd2d)
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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47 checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
48 exitOnError=False,
49 updateOnError=True,
50 warnOnlyOnLoadError=False),
51 "checker")
52 else:
53 checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True,
54 warnOnlyOnLoadError=False), "checker")
1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

--- 38 unchanged lines hidden (view full) ---

47 checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
48 exitOnError=False,
49 updateOnError=True,
50 warnOnlyOnLoadError=False),
51 "checker")
52 else:
53 checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True,
54 warnOnlyOnLoadError=False), "checker")
55 checker.itb = Parent.itb
56 checker.dtb = Parent.dtb
55 checker.itb = Parent.itb
56 checker.dtb = Parent.dtb
57
58 cachePorts = Param.Unsigned(200, "Cache Ports")
59 icache_port = Port("Instruction Port")
60 dcache_port = Port("Data Port")
61 _mem_ports = ['icache_port', 'dcache_port']
62
63 decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay")
64 renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay")

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58 cachePorts = Param.Unsigned(200, "Cache Ports")
59 icache_port = Port("Instruction Port")
60 dcache_port = Port("Data Port")
61 _mem_ports = ['icache_port', 'dcache_port']
62
63 decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay")
64 renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay")

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