O3CPU.py (4486:aaeb03a8a6e1) | O3CPU.py (4597:063f25d13229) |
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1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 41 unchanged lines hidden (view full) --- 50 warnOnlyOnLoadError=False), 51 "checker") 52 else: 53 checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True, 54 warnOnlyOnLoadError=False), "checker") 55 checker.itb = Parent.itb 56 checker.dtb = Parent.dtb 57 | 1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 41 unchanged lines hidden (view full) --- 50 warnOnlyOnLoadError=False), 51 "checker") 52 else: 53 checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True, 54 warnOnlyOnLoadError=False), "checker") 55 checker.itb = Parent.itb 56 checker.dtb = Parent.dtb 57 |
58 cachePorts = Param.Unsigned("Cache Ports") | 58 cachePorts = Param.Unsigned(200, "Cache Ports") |
59 icache_port = Port("Instruction Port") 60 dcache_port = Port("Data Port") 61 _mem_ports = ['icache_port', 'dcache_port'] 62 63 decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay") 64 renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay") 65 iewToFetchDelay = Param.Unsigned(1, "Issue/Execute/Writeback to fetch " 66 "delay") --- 65 unchanged lines hidden (view full) --- 132 numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 133 numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 134 135 instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by") 136 137 function_trace = Param.Bool(False, "Enable function trace") 138 function_trace_start = Param.Tick(0, "Cycle to start function trace") 139 | 59 icache_port = Port("Instruction Port") 60 dcache_port = Port("Data Port") 61 _mem_ports = ['icache_port', 'dcache_port'] 62 63 decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay") 64 renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay") 65 iewToFetchDelay = Param.Unsigned(1, "Issue/Execute/Writeback to fetch " 66 "delay") --- 65 unchanged lines hidden (view full) --- 132 numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") 133 numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") 134 135 instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by") 136 137 function_trace = Param.Bool(False, "Enable function trace") 138 function_trace_start = Param.Tick(0, "Cycle to start function trace") 139 |
140 smtNumFetchingThreads = Param.Unsigned("SMT Number of Fetching Threads") 141 smtFetchPolicy = Param.String("SMT Fetch policy") 142 smtLSQPolicy = Param.String("SMT LSQ Sharing Policy") 143 smtLSQThreshold = Param.String("SMT LSQ Threshold Sharing Parameter") 144 smtIQPolicy = Param.String("SMT IQ Sharing Policy") 145 smtIQThreshold = Param.String("SMT IQ Threshold Sharing Parameter") 146 smtROBPolicy = Param.String("SMT ROB Sharing Policy") 147 smtROBThreshold = Param.String("SMT ROB Threshold Sharing Parameter") 148 smtCommitPolicy = Param.String("SMT Commit Policy") | 140 smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads") 141 smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy") 142 smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy") 143 smtLSQThreshold = Param.Int(100, "SMT LSQ Threshold Sharing Parameter") 144 smtIQPolicy = Param.String('Partitioned', "SMT IQ Sharing Policy") 145 smtIQThreshold = Param.Int(100, "SMT IQ Threshold Sharing Parameter") 146 smtROBPolicy = Param.String('Partitioned', "SMT ROB Sharing Policy") 147 smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter") 148 smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy") |
149 150 def addPrivateSplitL1Caches(self, ic, dc): 151 BaseCPU.addPrivateSplitL1Caches(self, ic, dc) 152 self.icache.tgts_per_mshr = 20 153 self.dcache.tgts_per_mshr = 20 | 149 150 def addPrivateSplitL1Caches(self, ic, dc): 151 BaseCPU.addPrivateSplitL1Caches(self, ic, dc) 152 self.icache.tgts_per_mshr = 20 153 self.dcache.tgts_per_mshr = 20 |